Discovered a handful of strings in python scripts that use backslashes for regular expressions but do not prefix the string with 'r'. Although there was a concerted effort some time ago to fix all the script, a handful of lines were missed. Thanks to Brad Minch for reporting the error!
diff --git a/VERSION b/VERSION index d1e8534..2cc2aa0 100644 --- a/VERSION +++ b/VERSION
@@ -1 +1 @@ -1.0.539 +1.0.540
diff --git a/gf180mcu/custom/scripts/convert_sc_cdl.py b/gf180mcu/custom/scripts/convert_sc_cdl.py index a03b225..26f3c7a 100755 --- a/gf180mcu/custom/scripts/convert_sc_cdl.py +++ b/gf180mcu/custom/scripts/convert_sc_cdl.py
@@ -41,7 +41,7 @@ # 3) Uppercase diode "d" for consistency fixedline = re.sub('^d', 'D', fixedline) # 4) Convert $m to M - fixedline = re.sub('\$m=', 'M=', fixedline, flags=re.IGNORECASE) + fixedline = re.sub(r'\$m=', 'M=', fixedline, flags=re.IGNORECASE) # 5) Fix incorrect endcap (endcap does not have VNW VPW) fixedline = re.sub('endcap VDD VNW VPW', 'endcap VDD', fixedline, flags=re.IGNORECASE) # 6) Fix incorrect diode properties in antenna cell (missing key)
diff --git a/gf180mcu/custom/scripts/convert_sram_cdl.py b/gf180mcu/custom/scripts/convert_sram_cdl.py index b07c09b..ae1a8d7 100755 --- a/gf180mcu/custom/scripts/convert_sram_cdl.py +++ b/gf180mcu/custom/scripts/convert_sram_cdl.py
@@ -36,10 +36,10 @@ # 2) 5V transistor models --> change to 6V fixedline = re.sub('_05v0', '_06v0', fixedline, flags=re.IGNORECASE) # 3) Remove $X, $Y, $D, and $T parameters - fixedline = re.sub('\$X=-?[0-9]+', '', fixedline, flags=re.IGNORECASE) - fixedline = re.sub('\$Y=-?[0-9]+', '', fixedline, flags=re.IGNORECASE) - fixedline = re.sub('\$D=-?[0-9]+', '', fixedline, flags=re.IGNORECASE) - fixedline = re.sub('\$T=-?[0-9]+ -?[0-9]+ -?[0-9]+ -?[0-9]+', '', + fixedline = re.sub(r'\$X=-?[0-9]+', '', fixedline, flags=re.IGNORECASE) + fixedline = re.sub(r'\$Y=-?[0-9]+', '', fixedline, flags=re.IGNORECASE) + fixedline = re.sub(r'\$D=-?[0-9]+', '', fixedline, flags=re.IGNORECASE) + fixedline = re.sub(r'\$T=-?[0-9]+ -?[0-9]+ -?[0-9]+ -?[0-9]+', '', fixedline, flags=re.IGNORECASE) if line != fixedline:
diff --git a/sky130/custom/scripts/rename_models.py b/sky130/custom/scripts/rename_models.py index f95f5ba..002fafc 100755 --- a/sky130/custom/scripts/rename_models.py +++ b/sky130/custom/scripts/rename_models.py
@@ -49,7 +49,7 @@ for line in spilines: # Modify: Replace "../cells/<name>/" with "../../libs.ref/sky130_fd_pr/spice/" - fixedline = re.sub('\.\./cells/[^/]+/', '../../libs.ref/' + libpath, line) + fixedline = re.sub(r'\.\./cells/[^/]+/', '../../libs.ref/' + libpath, line) fixedlines.append(fixedline) if fixedline != line: modified = True