tree 4f5fc20b52a9e8a370952a7286042906a9ca2427
parent 14a2389f9d2ed521fffd3e69928763ddb07bc434
author Tim Edwards <tim@opencircuitdesign.com> 1629991422 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1629991422 -0400

Added processing to the SRAM core device model files to remove
parameters that are both unnecessary/unused and incompatible with
Xyce.