)]}'
{
  "commit": "bba9bd1996f59687c5ed2cc669407d978b244c1a",
  "tree": "62497b9a13858779f759f6467c8a6e24d3b86283",
  "parents": [
    "48e7c84da13a38824385e7b809bb1f023e535993"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Dec 22 17:16:09 2020 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Dec 22 17:16:09 2020 -0500"
  },
  "message": "Added support in the magic tech file for ESD devices of the 5V nFET\nand pFET varieties.  These are essentially just standard 5V FETs with\na marker layer used for LVS purposes;  however, as these are the devices\nwith angled gates, they can be used to suppress DRC errors in the\ndevice layouts (which has not yet been done).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "97cf5a47945e6c42b9efca75fbe4961e0d8f449b",
      "old_mode": 33188,
      "old_path": "sky130/magic/sky130.tech",
      "new_id": "72ba8f7196fb418cd13f189316009e378b37ec4c",
      "new_mode": 33188,
      "new_path": "sky130/magic/sky130.tech"
    }
  ]
}