Added verilog file for the "fake diode" cell used by openlane in sky130_fd_sc_hd.
diff --git a/scripts/configure b/scripts/configure
index 4c9eda5..41644f1 100755
--- a/scripts/configure
+++ b/scripts/configure
@@ -1877,7 +1877,7 @@
elif test "$enableval" == "no" -o "$enableval" == "NO"; then
echo "Disabling sky130..."
else
- export SKY130_SOURCE_PATH=$enableval
+ SKY130_SOURCE_PATH=$enableval
fi
else
@@ -1888,14 +1888,9 @@
fi
# # Require this argument
- # AC_MSG_NOTICE([Checking whether source path is specified for 'pdk'])
- # if test "x$[]pdkvar[]_SOURCE_PATH" == "x" ; then
- # AC_MSG_ERROR([Option --with-pdk-source=<path> not specified!])
- # fi
if [ "$SKY130_SOURCE_PATH" != "" ]; then
SKY130_SOURCE_PATH=`readlink -f $SKY130_SOURCE_PATH`
-
# basic check that the PDK exists there (the path must exist in any case)
{ $as_echo "$as_me:${as_lineno-$LINENO}: Checking specified path for 'sky130' at $SKY130_SOURCE_PATH" >&5
$as_echo "$as_me: Checking specified path for 'sky130' at $SKY130_SOURCE_PATH" >&6;}
@@ -2516,7 +2511,7 @@
$as_echo_n "(cached) " >&6
else
- for am_cv_pathless_PYTHON in python python2 python3 python3.9 python3.8 python3.7 python3.6 python3.5 python3.4 python3.3 python3.2 python3.1 python3.0 python2.7 python2.6 python2.5 python2.4 python2.3 python2.2 python2.1 python2.0 none; do
+ for am_cv_pathless_PYTHON in python python2 python3 python3.3 python3.2 python3.1 python3.0 python2.7 python2.6 python2.5 python2.4 python2.3 python2.2 python2.1 python2.0 none; do
test "$am_cv_pathless_PYTHON" = none && break
prog="import sys
# split strings by '.' and convert to numeric. Append some zeros
@@ -2739,33 +2734,28 @@
if test -z $PYTHON;
then
- if test -z "";
- then
- PYTHON="python3"
- else
- PYTHON=""
- fi
+ PYTHON="python"
fi
PYTHON_NAME=`basename $PYTHON`
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking $PYTHON_NAME module: distutils" >&5
$as_echo_n "checking $PYTHON_NAME module: distutils... " >&6; }
- $PYTHON -c "import distutils" 2>/dev/null
- if test $? -eq 0;
- then
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+ $PYTHON -c "import distutils" 2>/dev/null
+ if test $? -eq 0;
+ then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
$as_echo "yes" >&6; }
- eval HAVE_PYMOD_DISTUTILS=yes
- else
- { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+ eval HAVE_PYMOD_DISTUTILS=yes
+ else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
$as_echo "no" >&6; }
- eval HAVE_PYMOD_DISTUTILS=no
- #
- if test -n ""
- then
- as_fn_error $? "failed to find required module distutils" "$LINENO" 5
- exit 1
- fi
- fi
+ eval HAVE_PYMOD_DISTUTILS=no
+ #
+ if test -n ""
+ then
+ as_fn_error $? "failed to find required module distutils" "$LINENO" 5
+ exit 1
+ fi
+ fi
# Check for "--with-ef-style"
diff --git a/scripts/configure.ac b/scripts/configure.ac
index df39b39..c6a0c53 100755
--- a/scripts/configure.ac
+++ b/scripts/configure.ac
@@ -63,23 +63,18 @@
elif test "$enableval" == "no" -o "$enableval" == "NO"; then
echo "Disabling pdk..."
else
- export pdkvar[]_SOURCE_PATH=$enableval
+ pdkvar[]_SOURCE_PATH=$enableval
fi
], [
pdk_find
]
)
# # Require this argument
- # AC_MSG_NOTICE([Checking whether source path is specified for 'pdk'])
- # if test "x$[]pdkvar[]_SOURCE_PATH" == "x" ; then
- # AC_MSG_ERROR([Option --with-pdk-source=<path> not specified!])
- # fi
if @<:@ "$[]pdkvar[]_SOURCE_PATH" != "" @:>@; then
pdkvar[]_SOURCE_PATH=`readlink -f $[]pdkvar[]_SOURCE_PATH`
-
# basic check that the PDK exists there (the path must exist in any case)
- AC_MSG_NOTICE([Checking specified path for 'pdk' at $pdkvar[]_SOURCE_PATH])
+ AC_MSG_NOTICE([Checking specified path for 'pdk' at $[]pdkvar[]_SOURCE_PATH])
AC_CHECK_FILE($pdkvar[]_SOURCE_PATH,[
AC_MSG_NOTICE(['pdk' source path found at $pdkvar[]_SOURCE_PATH])
], [
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index 321a98d..d8fe84b 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -499,6 +499,7 @@
${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
-gds %l/gds/*.gds \
-lef %l/lef/*.lef \
+ -verilog %l/verilog/*.v \
-library digital sky130_fd_sc_hd |& tee -a ${SKY130A}_install.log
# Add a maskhint set for the GPIO pad .mag view to prevent problems writing
# when writing HVI to GDS during hierarchical adjustments.
diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__diode_2.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__diode_2.v
new file mode 100644
index 0000000..4ddd77a
--- /dev/null
+++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__diode_2.v
@@ -0,0 +1,97 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_EF_SC_HD__FAKEDIODE_2_V
+`define SKY130_EF_SC_HD__FAKEDIODE_2_V
+
+/**
+ * fakediode: Antenna tie-down diode with no connection between the DIODE
+ * pin and the diode. This is just the sky130_fd_sc_hd__diode_2 cell with
+ * the contacts removed between the diode and the pin. It is used by the
+ * openlane synthesis flow to preemptively put antenna tie-downs close to
+ * every pin without making a connection. If the net needs an antenna
+ * tiedown, the fakediode cell can be replaced by the real diode cell.
+ *
+ * Verilog wrapper for diode with size of 2 units. Note that the wrapper
+ * is around the original SkyWater diode base cell; because the diode
+ * has no function in verilog, there is no difference between the verilog
+ * definitions of the diode and fake diode other than the cell name.
+ *
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_ef_sc_hd__fakediode_2 (
+ DIODE,
+ VPWR ,
+ VGND ,
+ VPB ,
+ VNB
+);
+
+ input DIODE;
+ input VPWR ;
+ input VGND ;
+ input VPB ;
+ input VNB ;
+ sky130_fd_sc_hd__diode base (
+ .DIODE(DIODE),
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPB),
+ .VNB(VNB)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_ef_sc_hd__fakediode_2 (
+ DIODE
+);
+
+ input DIODE;
+
+ // Voltage supply signals
+ supply1 VPWR;
+ supply0 VGND;
+ supply1 VPB ;
+ supply0 VNB ;
+
+ sky130_fd_sc_hd__diode base (
+ .DIODE(DIODE)
+ );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_EF_SC_HD__FAKEDIODE_2_V
