diff --git a/sky130/qflow/sky130osu.sh b/sky130/qflow/sky130osu.sh
index 4afd9bd..168bb64 100644
--- a/sky130/qflow/sky130osu.sh
+++ b/sky130/qflow/sky130osu.sh
@@ -9,21 +9,21 @@
 #ifdef EF_FORMAT
 set leffile=STAGING_PATH/TECHNAME/libs.ref/lef/sky130_osu130/sky130_osu130.lef
 #else (!EF_FORMAT)
-set leffile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/lef/sky130_osu130.lef
+set leffile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/lef/sky130_osu130.lef
 #endif (!EF_FORMAT)
 
 # The SPICE netlist containing subcell definitions for all the standard cells
 #ifdef EF_FORMAT
 set spicefile=STAGING_PATH/TECHNAME/libs.ref/spice/sky130_osu130/sky130_osu130.spice
 #else (!EF_FORMAT)
-set spicefile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/spice/sky130_osu130.spice
+set spicefile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/spice/sky130_osu130.spice
 #endif (!EF_FORMAT)
 
 # The liberty format file containing standard cell timing and function information
 #ifdef EF_FORMAT
 set libertyfile=STAGING_PATH/TECHNAME/libs.ref/lib/sky130_osu130/sky130_osu130.lib
 #else (!EF_FORMAT)
-set libertyfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/lib/sky130_osu130.lib
+set libertyfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/lib/sky130_osu130.lib
 #endif (!EF_FORMAT)
 
 # If there is another LEF file containing technology information
@@ -34,7 +34,7 @@
 #ifdef EF_FORMAT
 set techleffile=STAGING_PATH/TECHNAME/libs.ref/techLEF/sky130_osu130/sky130_osu130_tech.lef
 #else (!EF_FORMAT)
-set techleffile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/techLEF/sky130_osu130_tech.lef
+set techleffile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/techLEF/sky130_osu130_tech.lef
 #endif (!EF_FORMAT)
 #else
 # NOTE:  There is no technology LEF file for the 3-metal stack!
@@ -52,16 +52,16 @@
 set clkbufpin_out=Y		;# Name of output port to buffer cell
 
 set fillcell=FILL		;# Spacer (filler) cell (prefix, if more than one)
-set decapcell=""		;# Decap (filler) cell (prefix, if more than one)
-set antennacell=""		;# Antenna (filler) cell (prefix, if more than one)
-set antennapin_in=""		;# Antenna cell input connection
+set decapcell="DECAP"		;# Decap (filler) cell (prefix, if more than one)
+set antennacell="ANT"		;# Antenna (filler) cell (prefix, if more than one)
+set antennapin_in="A"		;# Antenna cell input connection
 set bodytiecell=""		;# Body tie (filler) cell (prefix, if more than one)
 
 # yosys tries to eliminate use of these; depends on source .v
-set tiehi=""			;# Cell to connect to power, if one exists
-set tiehipin_out=""		;# Output pin name of tiehi cell, if it exists
-set tielo=""			;# Cell to connect to ground, if one exists
-set tielopin_out=""		;# Output pin name of tielo cell, if it exists
+set tiehi="TIEHI"		;# Cell to connect to power, if one exists
+set tiehipin_out="Y"		;# Output pin name of tiehi cell, if it exists
+set tielo="TIELO"		;# Cell to connect to ground, if one exists
+set tielopin_out="Y"		;# Output pin name of tielo cell, if it exists
 
 set gndnet="vdd"		;# Name used for ground pins in standard cells
 set vddnet="vss"		;# Name used for power pins in standard cells
@@ -72,11 +72,11 @@
 set magic_display="XR" 	;# magic display, defeat display query and OGL preference
 set netgen_setup=STAGING_PATH/TECHNAME/libs.tech/netgen/TECHNAME_setup.tcl	;# netgen setup file for LVS
 #ifdef EF_FORMAT
-set gdsfile=STAGING_PATH/TECHNAME/libs.ref/gds/sky130_osu130/sky130_osu130.gds	;# GDS database of standard cells
-set verilogfile=STAGING_PATH/TECHNAME/libs.ref/verilog/sky130_osu130/sky130_osu130.v	;# Verilog models of standard cells
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/gds/LIBRARY/sky130_osu130.gds	;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/verilog/LIBRARY/sky130_osu130.v	;# Verilog models of standard cells
 #else (!EF_FORMAT)
-set gdsfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/gds/sky130_osu130.gds	;# GDS database of standard cells
-set verilogfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/verilog/sky130_osu130.v	;# Verilog models of standard cells
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/gds/sky130_osu130.gds	;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/verilog/sky130_osu130.v	;# Verilog models of standard cells
 #endif (!EF_FORMAT)
 
 # Set a conditional default in the project_vars.sh file for this process