tree da839df9d49d6be642f37ffe1da1061d506faf25
parent 7e29496eecf3ee8e1766f1b7f9441f97204d4735
author Tim Edwards <tim@opencircuitdesign.com> 1620239910 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1620239910 -0400

Modified the techfile to not add nwell under pfetarea in cifinput
when in the SRAM core cell (modification requested by Jesse
Cirimelli-Low).