)]}'
{
  "commit": "a12a941772e6267fc62b81dd27e95d34c83783ba",
  "tree": "da839df9d49d6be642f37ffe1da1061d506faf25",
  "parents": [
    "7e29496eecf3ee8e1766f1b7f9441f97204d4735"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed May 05 14:38:30 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed May 05 14:38:30 2021 -0400"
  },
  "message": "Modified the techfile to not add nwell under pfetarea in cifinput\nwhen in the SRAM core cell (modification requested by Jesse\nCirimelli-Low).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "aa8006b4cde467fc479415f303b34488f86327bd",
      "old_mode": 33188,
      "old_path": "VERSION",
      "new_id": "9740ddf91aa7ef9bfcb1778c7ce190876bfdb2a3",
      "new_mode": 33188,
      "new_path": "VERSION"
    },
    {
      "type": "modify",
      "old_id": "9e288ad771fcd6baa1ec9267b358472c4ed0e8ed",
      "old_mode": 33188,
      "old_path": "sky130/magic/sky130.tech",
      "new_id": "bfc96358a49c16a25bd84773604c84a4881aec91",
      "new_mode": 33188,
      "new_path": "sky130/magic/sky130.tech"
    }
  ]
}