diff --git a/gf180mcu/Makefile.in b/gf180mcu/Makefile.in
index 2cf37a6..63d4711 100644
--- a/gf180mcu/Makefile.in
+++ b/gf180mcu/Makefile.in
@@ -1295,6 +1295,9 @@
 	rm -rf ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3/cdl
 	mkdir -p ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3/cdl
 	cp -rp ${AVALON_REF_SOURCE}/cdl ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3
+	rm -rf ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3/spice
+	mkdir -p ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3/spice
+	cp -rp ${AVALON_REF_SOURCE}/spice ${STAGING_PATH}/${GF180MCU$*}/libs.ref/gf180mcu_as_sc_mcu7t3v3
 
 	# This library is done the right way and has its own librelane setup.
 	mkdir -p ${OPENLANETOP_STAGING_$*}
diff --git a/gf180mcu/netgen/gf180mcu_setup.tcl b/gf180mcu/netgen/gf180mcu_setup.tcl
index 08e3ca0..1bd4c0e 100644
--- a/gf180mcu/netgen/gf180mcu_setup.tcl
+++ b/gf180mcu/netgen/gf180mcu_setup.tcl
@@ -411,9 +411,6 @@
 #---------------------------------------------------------------
 
 foreach cell $cells1 {
-#   if {[regexp {gf180mcu_fd_sc_[^_]+__fillcap_[[:digit:]]+} $cell match]} {
-#       ignore class "-circuit1 $cell"
-#   }
     if {[regexp {gf180mcu_fd_sc_[^_]+__endcap} $cell match]} {
         ignore class "-circuit1 $cell"
     }
@@ -426,9 +423,6 @@
 }
 
 foreach cell $cells2 {
-#   if {[regexp {gf180mcu_fd_sc_[^_]+__fillcap_[[:digit:]]+} $cell match]} {
-#       ignore class "-circuit2 $cell"
-#   }
     if {[regexp {gf180mcu_fd_sc_[^_]+__endcap} $cell match]} {
         ignore class "-circuit2 $cell"
     }
@@ -454,6 +448,20 @@
     }
 }
 
+# And the Avalon Semiconductor cell libraries
+
+foreach cell $cells1 {
+    if {[regexp {gf180mcu_as_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+        ignore class "-circuit1 $cell"
+    }
+}
+
+foreach cell $cells2 {
+    if {[regexp {gf180mcu_as_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+        ignore class "-circuit2 $cell"
+    }
+}
+
 #---------------------------------------------------------------
 # Allow the fill, decap, etc., cells to be parallelized
 #---------------------------------------------------------------
@@ -508,6 +516,32 @@
     }
 }
 
+# And do the same for the Avalon semiconductor 3.3V standard cell library.
+
+foreach cell $cells1 {
+    if {[regexp {gf180mcu_as_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+        property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {gf180mcu_as_sc_[^_]+__fillcap_[[:digit:]]+} $cell match]} {
+        property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {gf180mcu_as_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+        property "-circuit1 $cell" parallel enable
+    }
+}
+
+foreach cell $cells2 {
+    if {[regexp {gf180mcu_as_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+        property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {gf180mcu_as_sc_[^_]+__fillcap_[[:digit:]]+} $cell match]} {
+        property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {gf180mcu_as_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+        property "-circuit2 $cell" parallel enable
+    }
+}
+
 # Match pins on black-box cells if LVS is called with "-blackbox"
 if {[model blackbox]} {
     foreach cell $cells1 {
@@ -520,17 +554,4 @@
     }
 }
 
-# Allow parallel reduction of fillcap (decap fill) cells
-
-foreach cell $cells1 {
-    if {[regexp {.*gf180mcu_fd_sc_.*__fillcap_[[:digit:]]+} $cell match]} {
-	property "-circuit1 $cell" parallel enable
-    }
-}
-
-foreach cell $cells2 {
-    if {[regexp {gf180mcu_fd_sc_.*__fillcap_[[:digit:]]+} $cell match]} {
-	property "-circuit2 $cell" parallel enable
-    }
-}
 #---------------------------------------------------------------