diff --git a/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fill_12.gds b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fill_12.gds
new file mode 100644
index 0000000..91e9769
--- /dev/null
+++ b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fill_12.gds
Binary files differ
diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef
new file mode 100644
index 0000000..1087873
--- /dev/null
+++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fill_12.lef
@@ -0,0 +1,57 @@
+VERSION 5.7 ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+MACRO sky130_ef_sc_hd__fill_12
+  CLASS CORE ;
+  FOREIGN sky130_ef_sc_hd__fill_12 ;
+  ORIGIN 0.000 0.000 ;
+  SIZE 5.520 BY 2.720 ;
+  SYMMETRY X Y R90 ;
+  SITE unithd ;
+  OBS
+      LAYER nwell ;
+        RECT -0.190 1.305 5.710 2.910 ;
+      LAYER pwell ;
+        RECT 0.145 -0.085 0.315 0.085 ;
+        RECT 2.935 -0.060 3.045 0.060 ;
+        RECT 4.755 -0.050 4.915 0.060 ;
+      LAYER li1 ;
+        RECT 0.000 2.635 5.520 2.805 ;
+        RECT 0.085 1.545 2.675 2.635 ;
+        RECT 0.085 0.855 1.295 1.375 ;
+        RECT 1.465 1.025 2.675 1.545 ;
+        RECT 0.085 0.085 2.675 0.855 ;
+        RECT 0.000 -0.085 5.520 0.085 ;
+      LAYER mcon ;
+        RECT 0.145 2.635 0.315 2.805 ;
+        RECT 0.605 2.635 0.775 2.805 ;
+        RECT 1.065 2.635 1.235 2.805 ;
+        RECT 1.525 2.635 1.695 2.805 ;
+        RECT 1.985 2.635 2.155 2.805 ;
+        RECT 2.445 2.635 2.615 2.805 ;
+        RECT 2.905 2.635 3.075 2.805 ;
+        RECT 3.365 2.635 3.535 2.805 ;
+        RECT 3.825 2.635 3.995 2.805 ;
+        RECT 4.285 2.635 4.455 2.805 ;
+        RECT 4.745 2.635 4.915 2.805 ;
+        RECT 5.205 2.635 5.375 2.805 ;
+        RECT 0.145 -0.085 0.315 0.085 ;
+        RECT 0.605 -0.085 0.775 0.085 ;
+        RECT 1.065 -0.085 1.235 0.085 ;
+        RECT 1.525 -0.085 1.695 0.085 ;
+        RECT 1.985 -0.085 2.155 0.085 ;
+        RECT 2.445 -0.085 2.615 0.085 ;
+        RECT 2.905 -0.085 3.075 0.085 ;
+        RECT 3.365 -0.085 3.535 0.085 ;
+        RECT 3.825 -0.085 3.995 0.085 ;
+        RECT 4.285 -0.085 4.455 0.085 ;
+        RECT 4.745 -0.085 4.915 0.085 ;
+        RECT 5.205 -0.085 5.375 0.085 ;
+      LAYER met1 ;
+        RECT 0.000 2.480 5.520 2.960 ;
+        RECT 0.000 -0.240 5.520 0.240 ;
+  END
+END sky130_ef_sc_hd__fill_12
+END LIBRARY
+
diff --git a/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_12.v b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_12.v
new file mode 100644
index 0000000..dffe4c5
--- /dev/null
+++ b/sky130/custom/sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fill_12.v
@@ -0,0 +1,82 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_EF_SC_HD__FILL_12_V
+`define SKY130_EF_SC_HD__FILL_12_V
+
+/**
+ * fill_12:  Designed to replace the decap_12 cell while reducing the
+ * amount of local interconnect;  this is just a decap_6, fill_4, and
+ * fill_2 cell juxtaposed, making up the same width as the decap_12
+ * but with half the amount of decap.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_ef_sc_hd__fill_12 (
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_hd__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_ef_sc_hd__fill_12 (
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hd__fill base (
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_EF_SC_HD__FILL_12_V