diff --git a/sky130/openlane/common_pdn.tcl b/sky130/openlane/common_pdn.tcl
index 3333054..af6cc4c 100644
--- a/sky130/openlane/common_pdn.tcl
+++ b/sky130/openlane/common_pdn.tcl
@@ -27,6 +27,8 @@
     }
 }
 
+set pdngen::voltage_domains { CORE { primary_power VPWR primary_ground VGND } } 
+
 # Used if the design is the core of the chip
 set stdcell_core {
     name grid