Added "endcap" to "filltie" for digital standard cells that should
not have the well and substrate pins added to them.

gf180mcu/custom/scripts/fix_digital_lef.py

diff --git a/gf180mcu/custom/scripts/fix_digital_lef.py b/gf180mcu/custom/scripts/fix_digital_lef.py
index 74d6275..1bb9ad1 100755
--- a/gf180mcu/custom/scripts/fix_digital_lef.py
+++ b/gf180mcu/custom/scripts/fix_digital_lef.py
@@ -36,8 +36,8 @@
     for line in llines:
 
         # Check for MACRO line and record the macro name
-        # NOTE:  The "filltie" cell connects the biases to the power supplies
-        # and must be excluded from this modification.
+        # NOTE:  The "filltie" and "endcap" cells connect the biases to
+	# the power supplies and must be excluded from this modification.
 
         mmatch = macrorex.match(line)
         if mmatch:
@@ -47,7 +47,7 @@
 
         # Check for end of VSS pin in file
         ematch = endrex.match(line)
-        if ematch and 'filltie' not in inname:
+        if ematch and 'filltie' not in inname and 'endcap' not in inname:
             fixedlines.append('  PIN VPW')
             fixedlines.append('    DIRECTION INOUT ;')
             fixedlines.append('    USE ground ;')