diff --git a/sky130/custom/sky130_fd_io/lib/sky130_ef_io__analog_stubs.lib b/sky130/custom/sky130_fd_io/lib/sky130_ef_io__analog_stubs.lib
new file mode 100644
index 0000000..4bc6f3c
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/lib/sky130_ef_io__analog_stubs.lib
@@ -0,0 +1,627 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+library ("sky130_ef_io__analog_stubs") {
+  define(driver_model,library,string);
+  define(clk_width,library,string);
+  define(sim_opt,library,string);
+  define(simulator,library,string);
+  define(signal_voltage_type,pin,string);
+  technology ( cmos ) ;
+  delay_model : table_lookup;
+  revision : 1.0 ;
+  date : "Fri Oct 14 13:32:54 MST 2011";
+  voltage_unit  		: "1V"   ; 
+  current_unit  		: "1mA"  ;
+  leakage_power_unit		: "1nW"  ;
+  pulling_resistance_unit	: "1kohm" ;
+  time_unit			: "1ns"  ;
+  resistance_unit		: "1ohm" ;
+  capacitive_load_unit  	   (1,pf)  ;
+  
+  nom_process                   : 1.0 ;
+  nom_temperature               : 100	;
+  nom_voltage                   : 1.60	;
+
+  default_leakage_power_density : 0.0;
+  default_cell_leakage_power    : 0.0;
+  bus_naming_style              : "%s[%d]" ;
+  default_fanout_load	        : 0.0  ;  
+  default_inout_pin_cap 	: 0.0  ;  
+  default_input_pin_cap 	: 0.0  ;  
+  default_output_pin_cap	: 0.0  ;  
+  default_max_transition        : 25.00 ;
+  input_threshold_pct_rise      : 50.0 ;
+  input_threshold_pct_fall      : 50.0 ;
+  output_threshold_pct_rise     : 50.0 ;
+  output_threshold_pct_fall     : 50.0 ;
+  slew_lower_threshold_pct_fall : 20.0 ;
+  slew_lower_threshold_pct_rise : 20.0 ;
+  slew_upper_threshold_pct_fall : 80.0 ;
+  slew_upper_threshold_pct_rise : 80.0 ;
+  slew_derate_from_library 	:  1 ;
+  in_place_swap_mode            : match_footprint ;
+
+  library_features (report_delay_calculation);
+  define (always_on, pin, boolean) ;
+
+cell (sky130_ef_io__analog_esd_pad) {
+    cell_leakage_power :  2.9860000e+05 ;  
+    area :   14850.0 ;
+    pad_cell : true;
+
+    dont_touch : true ;      /* don't optimize this cell */
+is_macro_cell : true;
+    dont_use : true ;	     /* don't infer this cell	 */
+    interface_timing : true; /* this is a black box - a complex cell*/
+
+		pg_pin (VDDA) {
+			voltage_name : "VDDA";
+			pg_type : "primary_power";
+		}
+		pg_pin ("VDDIO_Q") {
+			voltage_name : "VDDIO_Q";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSWITCH) {
+			voltage_name : "VSWITCH";
+			pg_type : "primary_power";
+		}
+		pg_pin (VDDIO) {
+			voltage_name : "VDDIO";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCD) {
+			voltage_name : "VCCD";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCHIB) {
+			voltage_name : "VCCHIB";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSSD) {
+			voltage_name : "VSSD";
+			pg_type : "primary_ground";
+		}
+		pg_pin ("VSSIO_Q") {
+			voltage_name : "VSSIO_Q";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSA) {
+			voltage_name : "VSSA";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSIO) {
+			voltage_name : "VSSIO";
+			pg_type : "primary_ground";
+		}
+
+    pin (P_PAD) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+
+    pin (P_CORE) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_A") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_B") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+  }
+cell (sky130_ef_io__analog_minesd_pad) {
+    cell_leakage_power :  2.9860000e+05 ;  
+    area :   14850.0 ;
+    pad_cell : true;
+
+    dont_touch : true ;      /* don't optimize this cell */
+is_macro_cell : true;
+    dont_use : true ;	     /* don't infer this cell	 */
+    interface_timing : true; /* this is a black box - a complex cell*/
+
+		pg_pin (VDDA) {
+			voltage_name : "VDDA";
+			pg_type : "primary_power";
+		}
+		pg_pin ("VDDIO_Q") {
+			voltage_name : "VDDIO_Q";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSWITCH) {
+			voltage_name : "VSWITCH";
+			pg_type : "primary_power";
+		}
+		pg_pin (VDDIO) {
+			voltage_name : "VDDIO";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCD) {
+			voltage_name : "VCCD";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCHIB) {
+			voltage_name : "VCCHIB";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSSD) {
+			voltage_name : "VSSD";
+			pg_type : "primary_ground";
+		}
+		pg_pin ("VSSIO_Q") {
+			voltage_name : "VSSIO_Q";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSA) {
+			voltage_name : "VSSA";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSIO) {
+			voltage_name : "VSSIO";
+			pg_type : "primary_ground";
+		}
+
+    pin (P_PAD) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+
+    pin (P_CORE) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_A") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_B") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+  }
+cell (sky130_ef_io__analog_minesd_pad_short) {
+    cell_leakage_power :  2.9860000e+05 ;  
+    area :   14850.0 ;
+    pad_cell : true;
+
+    dont_touch : true ;      /* don't optimize this cell */
+is_macro_cell : true;
+    dont_use : true ;	     /* don't infer this cell	 */
+    interface_timing : true; /* this is a black box - a complex cell*/
+
+		pg_pin (VDDA) {
+			voltage_name : "VDDA";
+			pg_type : "primary_power";
+		}
+		pg_pin ("VDDIO_Q") {
+			voltage_name : "VDDIO_Q";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSWITCH) {
+			voltage_name : "VSWITCH";
+			pg_type : "primary_power";
+		}
+		pg_pin (VDDIO) {
+			voltage_name : "VDDIO";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCD) {
+			voltage_name : "VCCD";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCHIB) {
+			voltage_name : "VCCHIB";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSSD) {
+			voltage_name : "VSSD";
+			pg_type : "primary_ground";
+		}
+		pg_pin ("VSSIO_Q") {
+			voltage_name : "VSSIO_Q";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSA) {
+			voltage_name : "VSSA";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSIO) {
+			voltage_name : "VSSIO";
+			pg_type : "primary_ground";
+		}
+
+    pin (P_PAD) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+
+    pin (P_CORE) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_A") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_B") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+  }
+cell (sky130_ef_io__analog_noesd_pad) {
+    cell_leakage_power :  2.9860000e+05 ;  
+    area :   14850.0 ;
+    pad_cell : true;
+
+    dont_touch : true ;      /* don't optimize this cell */
+is_macro_cell : true;
+    dont_use : true ;	     /* don't infer this cell	 */
+    interface_timing : true; /* this is a black box - a complex cell*/
+
+		pg_pin (VDDA) {
+			voltage_name : "VDDA";
+			pg_type : "primary_power";
+		}
+		pg_pin ("VDDIO_Q") {
+			voltage_name : "VDDIO_Q";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSWITCH) {
+			voltage_name : "VSWITCH";
+			pg_type : "primary_power";
+		}
+		pg_pin (VDDIO) {
+			voltage_name : "VDDIO";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCD) {
+			voltage_name : "VCCD";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCHIB) {
+			voltage_name : "VCCHIB";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSSD) {
+			voltage_name : "VSSD";
+			pg_type : "primary_ground";
+		}
+		pg_pin ("VSSIO_Q") {
+			voltage_name : "VSSIO_Q";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSA) {
+			voltage_name : "VSSA";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSIO) {
+			voltage_name : "VSSIO";
+			pg_type : "primary_ground";
+		}
+
+    pin (P_PAD) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+
+    pin (P_CORE) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_A") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_B") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+  }
+cell (sky130_ef_io__analog_pad) {
+    cell_leakage_power :  2.9860000e+05 ;  
+    area :   14850.0 ;
+    pad_cell : true;
+
+    dont_touch : true ;      /* don't optimize this cell */
+is_macro_cell : true;
+    dont_use : true ;	     /* don't infer this cell	 */
+    interface_timing : true; /* this is a black box - a complex cell*/
+
+		pg_pin (VDDA) {
+			voltage_name : "VDDA";
+			pg_type : "primary_power";
+		}
+		pg_pin ("VDDIO_Q") {
+			voltage_name : "VDDIO_Q";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSWITCH) {
+			voltage_name : "VSWITCH";
+			pg_type : "primary_power";
+		}
+		pg_pin (VDDIO) {
+			voltage_name : "VDDIO";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCD) {
+			voltage_name : "VCCD";
+			pg_type : "primary_power";
+		}
+		pg_pin (VCCHIB) {
+			voltage_name : "VCCHIB";
+			pg_type : "primary_power";
+		}
+		pg_pin (VSSD) {
+			voltage_name : "VSSD";
+			pg_type : "primary_ground";
+		}
+		pg_pin ("VSSIO_Q") {
+			voltage_name : "VSSIO_Q";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSA) {
+			voltage_name : "VSSA";
+			pg_type : "primary_ground";
+		}
+		pg_pin (VSSIO) {
+			voltage_name : "VSSIO";
+			pg_type : "primary_ground";
+		}
+
+    pin (P_PAD) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+
+    pin (P_CORE) {
+    	    direction : "inout";
+    	    related_power_pin : "vddio";
+    	    related_ground_pin : "vssio";
+    	    always_on : false ;
+    	    is_pad : true;
+    	    capacitance : 1.061130;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_A") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+    pin ("AMUXBUS_B") {
+    	    direction : "inout";
+    	    related_power_pin : "VDDIO";
+    	    related_ground_pin : "VSSD";
+    	    always_on : true;
+    	    signal_voltage_type : "analog";
+    	    rise_capacitance : 0.069348;
+    	    capacitance : 0.070467;
+    	    fall_capacitance : 0.071586;
+        ccsn_first_stage() { 
+            is_needed : false ; 
+        } 
+        ccsn_last_stage() { 
+            is_needed : false ; 
+        } 
+    }
+  }
+}
diff --git a/sky130/librelane/config.tcl b/sky130/librelane/config.tcl
index 6f92d9a..49a2f0d 100755
--- a/sky130/librelane/config.tcl
+++ b/sky130/librelane/config.tcl
@@ -70,6 +70,7 @@
 set ::env(PAD_GDS) "\
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_fd_io.gds\
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_ef_io.gds\
+    $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_ef_io__analog.gds\
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.gds\
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/gds/sky130_ef_io__connect_vdda_vddio_and_vssa_vssio_slice_20um.gds\
 "
diff --git a/sky130/librelane/sky130_ef_io/config.tcl b/sky130/librelane/sky130_ef_io/config.tcl
index 6fd9c02..eea6319 100644
--- a/sky130/librelane/sky130_ef_io/config.tcl
+++ b/sky130/librelane/sky130_ef_io/config.tcl
@@ -32,6 +32,7 @@
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssio_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib \
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib \
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/slices_stubs.lib \
+    $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__analog_stubs.lib \
 "
 dict set ::env(PAD_LIBS) "*_ff_n40C_1v95" "\
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib \
@@ -40,6 +41,7 @@
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssio_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib \
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_ff_ff_n40C_1v95_5v50.lib \
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/slices_stubs.lib \
+    $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__analog_stubs.lib \
 "
 dict set ::env(PAD_LIBS) "*_ss_100C_1v60" "\
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib \
@@ -48,6 +50,7 @@
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssio_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib \
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_ss_ss_100C_1v60_3v00.lib \
     $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/slices_stubs.lib \
+    $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__analog_stubs.lib \
 "
 
 # Pad bondpad information (if needed)
@@ -64,6 +67,11 @@
     sky130_ef_io__vssd_lvc_clamped_pad/VSSD_PAD\
     sky130_ef_io__vddio_hvc_clamped_pad/VDDIO_PAD\
     sky130_ef_io__vssio_hvc_clamped_pad/VSSIO_PAD\
+    sky130_ef_io__analog_esd_pad/P_PAD\
+    sky130_ef_io__analog_minesd_pad/P_PAD\
+    sky130_ef_io__analog_minesd_pad_short/P_PAD\
+    sky130_ef_io__analog_noesd_pad/P_PAD\
+    sky130_ef_io__analog_pad/P_PAD\
 "
 
 # Sealring is added afterwards