)]}'
{
  "commit": "8f01d8f4d17110a53080cafc52c7762b94101f1d",
  "tree": "6cb633968274b8774f36db126f9a3759165758d5",
  "parents": [
    "8eda618f79b4465b2c3692be1959bcbdc543f42c"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Dec 11 10:05:48 2022 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Dec 11 10:05:48 2022 -0500"
  },
  "message": "Corrected an error in the remove_redundant_* routines in the\nverilog and SPICE library generator scripts.  This corrects an\nerror in generating the sky130 PDK that was caused by updating\nthe verilog library generator script in the previous commit.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "498ea1a46969cde5e52faf957be0919efbba65ae",
      "old_mode": 33261,
      "old_path": "common/create_spice_library.py",
      "new_id": "2f87a528206e093b14d46a1d3cb6df8698d59dde",
      "new_mode": 33261,
      "new_path": "common/create_spice_library.py"
    },
    {
      "type": "modify",
      "old_id": "d67c72b1df3d1f11e4dc7f123825da1cb2e31094",
      "old_mode": 33261,
      "old_path": "common/create_verilog_library.py",
      "new_id": "fce0c2a44e7b5ffec35d1b68824bbf1445c429c5",
      "new_mode": 33261,
      "new_path": "common/create_verilog_library.py"
    }
  ]
}