Corrected an error in the magic techfile which was left over from an early implementation of MiM caps and will erase the metal layers from a MiM cap on GDS read. Also: Corrected the netlists for the I/O power and ground cells to work around an error with the OGC* pins, which are internally connected. Modified the netgen setup file to allow the number of columns to be adjusted through use of an external environment variable NETGEN_COLUMNS.
diff --git a/VERSION b/VERSION index 1f4f633..32f6174 100644 --- a/VERSION +++ b/VERSION
@@ -1 +1 @@ -1.0.104 +1.0.105
diff --git a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl index 73dbe47..ed68dd6 100644 --- a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl +++ b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
@@ -13,7 +13,7 @@ * Instantiate the underlying power pad (connects P_PAD to VCCD) Xsky130_fd_io__top_power_hvc_base -+ AMUXBUS_A AMUXBUS_B DRN_HVC OGC_HVC ++ AMUXBUS_A AMUXBUS_B DRN_HVC VDDIO + VCCD VCCD + SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -33,7 +33,7 @@ * Instantiate the underlying power pad (connects P_PAD to VCCD) Xsky130_fd_io__top_power_lvc_base -+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 OGC_LVC ++ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 VDDIO + VCCD VCCD + SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -55,7 +55,7 @@ * Instantiate the underlying power pad (connects P_PAD to VDDA) Xsky130_fd_io__top_power_lvc_base -+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 OGC_LVC ++ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 VDDIO + VDDA VDDA + SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -75,7 +75,7 @@ * Instantiate the underlying power pad (connects P_PAD to VDDA) Xsky130_fd_io__top_power_hvc_base -+ AMUXBUS_A AMUXBUS_B DRN_HVC OGC_HVC ++ AMUXBUS_A AMUXBUS_B DRN_HVC VDDIO + VDDA VDDA + SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -96,7 +96,7 @@ * Instantiate the underlying power pad (connects P_PAD and VDDIO_Q to VDDIO) Xsky130_fd_io__top_power_lvc_base -+ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 OGC_LVC ++ AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 VDDIO + VDDIO VDDIO + SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -116,7 +116,7 @@ * Instantiate the underlying power pad (connects P_PAD and VDDIO_Q to VDDIO) Xsky130_fd_io__top_power_hvc_base -+ AMUXBUS_A AMUXBUS_B DRN_HVC OGC_HVC ++ AMUXBUS_A AMUXBUS_B DRN_HVC VDDIO + VDDIO VDDIO + SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -139,7 +139,7 @@ Xsky130_fd_io__top_ground_lvc_base + AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 + VSSD VSSD -+ OGC_LVC SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_lvc_wpad @@ -159,7 +159,7 @@ Xsky130_fd_io__top_ground_hvc_base + AMUXBUS_A AMUXBUS_B DRN_HVC + VSSD VSSD -+ OGC_HVC SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_hvc_wpad @@ -180,7 +180,7 @@ Xsky130_fd_io__top_ground_lvc_base + AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 + VSSIO VSSIO -+ OGC_LVC SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_lvc_wpad @@ -200,7 +200,7 @@ Xsky130_fd_io__top_ground_hvc_base + AMUXBUS_A AMUXBUS_B DRN_HVC + VSSIO VSSIO -+ OGC_HVC SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_hvc_wpad @@ -221,7 +221,7 @@ Xsky130_fd_io__top_ground_lvc_base + AMUXBUS_A AMUXBUS_B BDY2_B2B DRN_LVC1 DRN_LVC2 + VSSA VSSA -+ OGC_LVC SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO SRC_BDY_LVC1 SRC_BDY_LVC2 VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_lvc_wpad @@ -241,7 +241,7 @@ Xsky130_fd_io__top_ground_hvc_base + AMUXBUS_A AMUXBUS_B DRN_HVC + VSSA VSSA -+ OGC_HVC SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_hvc_wpad .ENDS @@ -358,7 +358,7 @@ * Instantiate the underlying power pad (connects P_PAD and VDDIO_Q to VDDIO) Xsky130_fd_io__top_power_hvc_base -+ AMUXBUS_A AMUXBUS_B VDDIO OGC_HVC ++ AMUXBUS_A AMUXBUS_B VDDIO VDDIO + VDDIO VDDIO + VSSIO VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -380,7 +380,7 @@ Xsky130_fd_io__top_ground_hvc_base + AMUXBUS_A AMUXBUS_B VDDIO + VSSIO VSSIO -+ OGC_HVC VSSIO VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO VSSIO VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_hvc_wpad @@ -398,7 +398,7 @@ * Instantiate the underlying power pad (connects P_PAD to VDDA) Xsky130_fd_io__top_power_hvc_base -+ AMUXBUS_A AMUXBUS_B VDDA OGC_HVC ++ AMUXBUS_A AMUXBUS_B VDDA VDDIO + VDDA VDDA + VSSA VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -420,7 +420,7 @@ Xsky130_fd_io__top_ground_hvc_base + AMUXBUS_A AMUXBUS_B VDDA + VSSA VSSA -+ OGC_HVC VSSA VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO VSSA VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_hvc_wpad @@ -439,7 +439,7 @@ * Instantiate the underlying power pad (connects P_PAD to VCCD) Xsky130_fd_io__top_power_lvc_base -+ AMUXBUS_A AMUXBUS_B VSSA VCCD VCCD OGC_LVC ++ AMUXBUS_A AMUXBUS_B VSSA VCCD VCCD VDDIO + VCCD VCCD + VSSIO VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -462,7 +462,7 @@ Xsky130_fd_io__top_ground_lvc_base + AMUXBUS_A AMUXBUS_B VSSA VCCD VCCD + VSSD VSSD -+ OGC_LVC VSSIO VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO VSSIO VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_lvc_wpad @@ -481,7 +481,7 @@ * Instantiate the underlying power pad (connects P_PAD to VCCD) Xsky130_fd_io__top_power_lvc_base -+ AMUXBUS_A AMUXBUS_B VSSIO VCCD VCCD OGC_LVC ++ AMUXBUS_A AMUXBUS_B VSSIO VCCD VCCD VDDIO + VCCD VCCD + VSSD VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH @@ -504,7 +504,7 @@ Xsky130_fd_io__top_ground_lvc_base + AMUXBUS_A AMUXBUS_B VSSIO VCCD VCCD + VSSD VSSD -+ OGC_LVC VSSD VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q ++ VDDIO VSSD VSSD VCCD VCCHIB VDDA VDDIO VDDIO_Q + VSSA VSSD VSSIO VSSIO_Q VSWITCH + sky130_fd_io__top_ground_lvc_wpad
diff --git a/sky130/magic/sky130.tech b/sky130/magic/sky130.tech index 5818bb0..fe37ce2 100644 --- a/sky130/magic/sky130.tech +++ b/sky130/magic/sky130.tech
@@ -2029,6 +2029,7 @@ #--------------------------------------------------- # MET3 fill #--------------------------------------------------- +XXX templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4 grow 3000 templayer met3fill_coarse topbox @@ -3300,9 +3301,6 @@ layer m3 MET3,MET3TXT,MET3PIN and-not MET3RES,MET3SHORT -#ifdef MIM - and-not CAPM -#endif (MIM) labels MET3 variants (vendor) labels MET3TXT port @@ -3335,9 +3333,6 @@ layer m4 MET4,MET4TXT,MET4PIN and-not MET4RES,MET4SHORT -#ifdef MIM - and-not CAPM2 -#endif (MIM) labels MET4 variants (vendor) labels MET4TXT port
diff --git a/sky130/netgen/sky130_setup.tcl b/sky130/netgen/sky130_setup.tcl index a67f7dc..e2447ec 100644 --- a/sky130/netgen/sky130_setup.tcl +++ b/sky130/netgen/sky130_setup.tcl
@@ -10,6 +10,9 @@ property default property parallel none +# Allow override of default #columns in the output format. +catch {format $env(NETGEN_COLUMNS)} + #--------------------------------------------------------------- # For the following, get the cell lists from # circuit1 and circuit2.