Fixes for OpenLane config files ~ Default SCL moved to PDK config file instead of being inside OpenLane itself ~ Reformatted `gf180mcu.json` ~ Updated cell names for gf180mcuC ~ `GLB_RT_LAYER_ADJUSTMENTS` -> `GRT_LAYER_ADJUSTMENTS` Git merge of PR #282 originating with Donn's modifications in efabless/open_pdks.
diff --git a/gf180mcu/gf180mcu.json b/gf180mcu/gf180mcu.json index 4d29029..fc7ad68 100644 --- a/gf180mcu/gf180mcu.json +++ b/gf180mcu/gf180mcu.json
@@ -1,3 +1,4 @@ +{ #define DESCRIPTION Global Foundries 0.18um MCU CMOS, 2fF MiM + 1k high sheet rho poly #ifdef METALS3 #define OPTION1 + 3 metal layer backend stack @@ -34,7 +35,6 @@ #else #define OPTION5 #endif (REDISTRIBUTION) -{ "foundry": "GF", "foundry-name": "Global Foundries", "node": "TECHNAME", @@ -63,33 +63,34 @@ #endif ], "stdcells": { - "gf180mcu_fd_sc_mcu9t5v0": "FD_SC_MCU9T5V0_COMMIT", - "gf180mcu_fd_sc_mcu7t5v0": "FD_SC_MCU9T5V0_COMMIT" + "gf180mcu_fd_sc_mcu9t5v0": "FD_SC_MCU9T5V0_COMMIT", + "gf180mcu_fd_sc_mcu7t5v0": "FD_SC_MCU9T5V0_COMMIT" }, "iocells": { "gf180mcu_fd_io": "FD_IO_COMMIT" }, "primitive": { - "gf180mcu_fd_pr": "FD_PR_COMMIT" + "gf180mcu_fd_pr": "FD_PR_COMMIT" }, "memory": { - "gf180mcu_fd_ip_sram": "FD_IP_SRAM_COMMIT" + "gf180mcu_fd_ip_sram": "FD_IP_SRAM_COMMIT" }, "build": { - "open_pdks": "OPEN_PDKS_VERSION", - "magic": "MAGIC_VERSION" + "open_pdks": "OPEN_PDKS_VERSION", + "magic": "MAGIC_VERSION" }, "commit": { - "open_pdks": "OPEN_PDKS_COMMIT", - "magic": "MAGIC_COMMIT" - } + "open_pdks": "OPEN_PDKS_COMMIT", + "magic": "MAGIC_COMMIT" + }, "reference": { - "open_pdks": "a1cf1b7c41dfccf1d38815278c543dd2f1e402dc", - "magic": "1c20abad5b9cd57da167297e27ccfc92f3321cf5", - "gf180mcu_fd_pr": "e1b4e187900370103bf9b8a22bb8625f883368ef", - "gf180mcu_fd_io": "bcaa40aaf6cf04d6e9cb143d0e5b0de9429e53ab", - "gf180mcu_fd_sc_mcu7t5v0": "493461195536004d46c8cbaac9605095c8280983", - "gf180mcu_fd_sc_mcu9t5v0": "493461195536004d46c8cbaac9605095c8280983", - "gf180mcu_fd_ip_sram": "9c411928870ce15226228fa52ddb6ecc0ea4ffbe" + "open_pdks": "cc0029b45c68137aa21323912f50d2fc17eeea13", + "magic": "f7df5e7c86fb47c5fd445c846afddc6fbabad6ae", + "gf180mcu_pdk": "08c628b77c4683cad8441d7d0c2df1c8ab58cbc2", + "gf180mcu_fd_pr": "92ec4b2e5eb193a0c5c2754413d44981c8e17e16", + "gf180mcu_fd_io": "5cc533968c9d03972f92a461af0edc80118b1e9c", + "gf180mcu_fd_sc_mcu7t5v0": "1f37f62c329b62710f4331d68272beeae20140e5", + "gf180mcu_fd_sc_mcu9t5v0": "1f37f62c329b62710f4331d68272beeae20140e5", + "gf180mcu_fd_ip_sram": "343ab45497682f3f3f808ee4c79a8f92c5010636" } }
diff --git a/gf180mcu/openlane/config.tcl b/gf180mcu/openlane/config.tcl index 65ccbb0..3fd391e 100644 --- a/gf180mcu/openlane/config.tcl +++ b/gf180mcu/openlane/config.tcl
@@ -7,9 +7,23 @@ set ::env(STD_CELL_POWER_PINS) "VDD" set ::env(STD_CELL_GROUND_PINS) "VSS" +if { ![info exist ::env(STD_CELL_LIBRARY)] } { + set ::env(STD_CELL_LIBRARY) gf180mcu_fd_sc_mcu7t5v0 +} +if { ![info exist ::env(STD_CELL_LIBRARY_OPT)] } { + set ::env(STD_CELL_LIBRARY_OPT) gf180mcu_fd_sc_mcu7t5v0 +} + +# Lib Files +set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/$::env(STD_CELL_LIBRARY)__tt_025C_3v30.lib" +set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/$::env(STD_CELL_LIBRARY)__ff_n40C_5v50.lib" +set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/$::env(STD_CELL_LIBRARY)__ss_125C_1v62.lib" + +set ::env(LIB_TYPICAL) $::env(LIB_SYNTH) + # Technology LEF -set ::env(TECH_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*_tech.lef"] -set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*_mw.lef"] +set ::env(TECH_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*.tlef"] +set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"] set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"] set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" set ::env(GPIO_PADS_LEF) "\ @@ -90,7 +104,7 @@ set ::env(METAL_LAYER_NAMES) "Metal1 Metal2 Metal3 Metal4 Metal5" set ::env(RT_MIN_LAYER) "Metal1" set ::env(RT_MAX_LAYER) "Metal5" -set ::env(GLB_RT_LAYER_ADJUSTMENTS) "0,0,0,0,0" +set ::env(GRT_LAYER_ADJUSTMENTS) "0,0,0,0,0" ## Tracks info set ::env(TRACKS_INFO_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/tracks.info"
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl index b02fa05..09ffd1f 100644 --- a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl +++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl
@@ -1,75 +1,47 @@ set current_folder [file dirname [file normalize [info script]]] -# Technology lib -set TRACK_POSTFIX "7T5P0" -set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_mcu_sc7_TT_1P8V_25C.lib" -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_mcu_sc7_FF_1P98V_M40C.lib" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_mcu_sc7_SS_1P62V_125C.lib" - -set ::env(LIB_TYPICAL) $::env(LIB_SYNTH) - -# to be removed as ABC scripts were updated to handle the mapping - -# MUX4 mapping -# set ::env(SYNTH_MUX4_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux4_map.v" - -# MUX2 mapping -# set ::env(SYNTH_MUX_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux2_map.v" # Placement site for core cells # This can be found in the technology lef -set ::env(PLACE_SITE) "GF018hv5v_mcu_sc7" +set ::env(PLACE_SITE) "$::env(STD_CELL_LIBRARY)" set ::env(PLACE_SITE_WIDTH) 0.56 set ::env(PLACE_SITE_HEIGHT) 3.92 # welltap and endcap cell -set ::env(FP_WELLTAP_CELL) "FILLTIE_$TRACK_POSTFIX" -set ::env(FP_ENDCAP_CELL) "ENDCAP_$TRACK_POSTFIX" +set ::env(FP_WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__filltie" +set ::env(FP_ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__endcap" # defaults (can be overridden by designs): -set ::env(SYNTH_DRIVING_CELL) "INV_X1_$TRACK_POSTFIX" +set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1" set ::env(SYNTH_DRIVING_CELL_PIN) "ZN" -set ::env(SYNTH_CLK_DRIVING_CELL) "INV_X4_$TRACK_POSTFIX" +set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_4" set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "ZN" # update these set ::env(SYNTH_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file -set ::env(SYNTH_MIN_BUF_PORT) "BUF_X1_$TRACK_POSTFIX I Z" -set ::env(SYNTH_TIEHI_PORT) "TIEH_$TRACK_POSTFIX Z" -set ::env(SYNTH_TIELO_PORT) "TIEL_$TRACK_POSTFIX ZN" +set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 I Z" +set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Z" +set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel ZN" # Placement defaults set ::env(PL_LIB) $::env(LIB_TYPICAL) # Fillcell insertion -set ::env(FILL_CELL) "FILL_*" -set ::env(DECAP_CELL) "FILLCAP_*" ; # There is also ENDCAP, which one should be used? - -# To be removed -# set ::env(RE_BUFFER_CELL) "BUF_X4_$TRACK_POSTFIX" ; # which buf should be used? +set ::env(FILL_CELL) "$::env(STD_CELL_LIBRARY)__fill_*" +set ::env(DECAP_CELL) "$::env(STD_CELL_LIBRARY)__fillcap_*" # Diode Insertion # A fake diode has to be created, for now don't use any strategy that uses fake diode # set ::env(FAKEDIODE_CELL) "" -set ::env(DIODE_CELL) "ANTENNA_$TRACK_POSTFIX" +set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__antenna" set ::env(DIODE_CELL_PIN) "I" set ::env(DIODE_INSERTION_STRATEGY) {4} -# What should be put here? -# Are we still using it? to be reviewed set ::env(CELL_PAD) 2 -set ::env(CELL_PAD_EXCLUDE) "FILLTIE_* FILLDECAP_* FILL_* ENDCAP_*" - -# Clk Buffers info CTS data -# This is for simple_cts which is deprecated -# set ::env(CELL_CLK_PORT) CLK -# set ::env(ROOT_CLK_BUFFER) "CLKBUF_X20_$TRACK_POSTFIX" -# set ::env(CLK_BUFFER) "CLKBUF_X4_$TRACK_POSTFIX" ; # which size should be used? -# set ::env(CLK_BUFFER_INPUT) I -# set ::env(CLK_BUFFER_OUTPUT) Z +set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__filltie_* $::env(STD_CELL_LIBRARY)__filldecap_* $::env(STD_CELL_LIBRARY)__fill_* $::env(STD_CELL_LIBRARY)__endcap_*" # TritonCTS configurations -set ::env(CTS_ROOT_BUFFER) "CLKBUF_X16_$TRACK_POSTFIX" -set ::env(CTS_CLK_BUFFER_LIST) "CLKBUF_X2_$TRACK_POSTFIX CLKBUF_X4_$TRACK_POSTFIX CLKBUF_X8_$TRACK_POSTFIX" +set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16" +set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" set ::env(CTS_MAX_CAP) 0.5 set ::env(FP_PDN_RAIL_WIDTH) 0.6
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells index cd9c76f..4add638 100644 --- a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells +++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells
@@ -1,2 +1,2 @@ -MUX2_X1_7T5P0 -OAI33_X2_7T5P0 \ No newline at end of file +gf180mcu_fd_sc_mcu7t5v0__mux2_1 +gf180mcu_fd_sc_mcu7t5v0__oai33_2 \ No newline at end of file
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells index a919971..2526b87 100644 --- a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells +++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells
@@ -1,12 +1,12 @@ -SDFFSNQ_X4_7T5P0 -SDFFQ_X1_7T5P0 -SDFFQ_X2_7T5P0 -SDFFQ_X4_7T5P0 -SDFFRNQ_X1_7T5P0 -SDFFRNQ_X2_7T5P0 -SDFFRNQ_X4_7T5P0 -SDFFRSNQ_X1_7T5P0 -SDFFRSNQ_X2_7T5P0 -SDFFRSNQ_X4_7T5P0 -SDFFSNQ_X1_7T5P0 -SDFFSNQ_X2_7T5P0 \ No newline at end of file +gf180mcu_fd_sc_mcu7t5v0__sdffq_1 +gf180mcu_fd_sc_mcu7t5v0__sdffq_2 +gf180mcu_fd_sc_mcu7t5v0__sdffq_4 +gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1 +gf180mcu_fd_sc_mcu7t5v0__sdffrnq_2 +gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4 +gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1 +gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_2 +gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4 +gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1 +gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2 +gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl index 175335f..09ffd1f 100644 --- a/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl +++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl
@@ -1,71 +1,47 @@ set current_folder [file dirname [file normalize [info script]]] -# Technology lib -set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_green_sc9_TT_1P80V_25C.lib" -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_green_sc9_FF_1P98V_M40C.db" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_green_sc9_SS_1P62V_125C.db" - -set ::env(LIB_TYPICAL) $::env(LIB_SYNTH) - -# to be removed as ABC scripts were updated to handle the mapping - -# MUX4 mapping -# set ::env(SYNTH_MUX4_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux4_map.v" - -# MUX2 mapping -# set ::env(SYNTH_MUX_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux2_map.v" # Placement site for core cells # This can be found in the technology lef -set ::env(PLACE_SITE) "GF018hv5v_green_sc9" +set ::env(PLACE_SITE) "$::env(STD_CELL_LIBRARY)" set ::env(PLACE_SITE_WIDTH) 0.56 -set ::env(PLACE_SITE_HEIGHT) 5.04 +set ::env(PLACE_SITE_HEIGHT) 3.92 # welltap and endcap cell -set ::env(FP_WELLTAP_CELL) "FILLTIE" -set ::env(FP_ENDCAP_CELL) "ENDCAP" +set ::env(FP_WELLTAP_CELL) "$::env(STD_CELL_LIBRARY)__filltie" +set ::env(FP_ENDCAP_CELL) "$::env(STD_CELL_LIBRARY)__endcap" # defaults (can be overridden by designs): -set ::env(SYNTH_DRIVING_CELL) "INV_X1" -#capacitance : 0.017653; +set ::env(SYNTH_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_1" set ::env(SYNTH_DRIVING_CELL_PIN) "ZN" +set ::env(SYNTH_CLK_DRIVING_CELL) "$::env(STD_CELL_LIBRARY)__inv_4" +set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "ZN" # update these set ::env(SYNTH_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file -set ::env(SYNTH_MIN_BUF_PORT) "BUF_X1 I Z" -set ::env(SYNTH_TIEHI_PORT) "TIEH Z" -set ::env(SYNTH_TIELO_PORT) "TIEL ZN" +set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 I Z" +set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Z" +set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel ZN" # Placement defaults set ::env(PL_LIB) $::env(LIB_TYPICAL) # Fillcell insertion -set ::env(FILL_CELL) "FILL_*" -set ::env(DECAP_CELL) "FILLCAP_*" ; # There is also ENDCAP, which one should be used? +set ::env(FILL_CELL) "$::env(STD_CELL_LIBRARY)__fill_*" +set ::env(DECAP_CELL) "$::env(STD_CELL_LIBRARY)__fillcap_*" -# To be removed -# set ::env(RE_BUFFER_CELL) "BUF_X4" ; # which buf should be used? - -# Diode insertaion +# Diode Insertion # A fake diode has to be created, for now don't use any strategy that uses fake diode -set ::env(DIODE_CELL) "ANTENNA" -# set ::env(FAKEDIODE_CELL) "sky130_ef_sc_hd__fakediode_2" ; # What is this? +# set ::env(FAKEDIODE_CELL) "" +set ::env(DIODE_CELL) "$::env(STD_CELL_LIBRARY)__antenna" set ::env(DIODE_CELL_PIN) "I" +set ::env(DIODE_INSERTION_STRATEGY) {4} -# Are we still using it? to be reviewed set ::env(CELL_PAD) 2 -set ::env(CELL_PAD_EXCLUDE) "FILLTIE_* FILLDECAP_* FILL_* ENDCAP_*" - -# Clk Buffers info CTS data -# This is for simple_cts which is deprecated -# set ::env(CELL_CLK_PORT) CLK -# set ::env(ROOT_CLK_BUFFER) "CLKBUF_X20" -# set ::env(CLK_BUFFER) "CLKBUF_X4" ; # which size should be used? -# set ::env(CLK_BUFFER_INPUT) I -# set ::env(CLK_BUFFER_OUTPUT) Z +set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__filltie_* $::env(STD_CELL_LIBRARY)__filldecap_* $::env(STD_CELL_LIBRARY)__fill_* $::env(STD_CELL_LIBRARY)__endcap_*" # TritonCTS configurations -set ::env(CTS_ROOT_BUFFER) "CLKBUF_X16" -set ::env(CTS_CLK_BUFFER_LIST) "CLKBUF_X2 CLKBUF_X4 CLKBUF_X8" +set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16" +set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8" set ::env(CTS_MAX_CAP) 0.5 set ::env(FP_PDN_RAIL_WIDTH) 0.6
diff --git a/sky130/openlane/config.tcl b/sky130/openlane/config.tcl index 856d9c1..1cea6cd 100755 --- a/sky130/openlane/config.tcl +++ b/sky130/openlane/config.tcl
@@ -2,9 +2,15 @@ set ::env(PROCESS) 130 set ::env(DEF_UNITS_PER_MICRON) 1000 +if { ![info exist ::env(STD_CELL_LIBRARY)] } { + set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hd +} +if { ![info exist ::env(STD_CELL_LIBRARY_OPT)] } { + set ::env(STD_CELL_LIBRARY_OPT) sky130_fd_sc_hd +} + # Placement site for core cells # This can be found in the technology lef - set ::env(VDD_PIN) "VPWR" set ::env(GND_PIN) "VGND" @@ -163,7 +169,7 @@ set ::env(FP_IO_VLAYER) "met2" # Routing Layer Info -set ::env(GLB_RT_LAYER_ADJUSTMENTS) "0.99,0,0,0,0,0" +set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0,0,0,0,0" set ::env(RT_MIN_LAYER) "met1" set ::env(RT_MAX_LAYER) "met5"
diff --git a/sky130/sky130.json b/sky130/sky130.json index 081668e..8831a11 100644 --- a/sky130/sky130.json +++ b/sky130/sky130.json
@@ -93,7 +93,7 @@ }, "reference": { "open_pdks": "cc0029b45c68137aa21323912f50d2fc17eeea13", - "magic": "43d5cc280413b0fd947b555bf1e8d79ea8681450", + "magic": "f7df5e7c86fb47c5fd445c846afddc6fbabad6ae", "skywater_pdk": "f70d8ca46961ff92719d8870a18a076370b85f6c", "sky130_osu_sc_t12": "ac90ef0c622a9377a16b5218d9da3ac4169eeaaf", "sky130_osu_sc_t15": "95d1c19abb47e1b2945847acb4e817b1b8417c43", @@ -101,7 +101,7 @@ "sky130_sram_macros": "c2333394e0b0b9d9d71185678a8d8087715d5e3b", "sky130_ml_xx_hd": "6eb3b0718552b034f1bf1870285ff135e3fb2dcb", "xschem_sky130": "5949895a0214f3471f16850297ea15e34a564edd", - "klayout_sky130": "85165d907f6b68e73bb25b9982cca20a87c98686", - "precheck_sky130": "07ace967fbe88e33844bf046bd9d30e1679580b7" + "klayout_sky130": "85165d907f6b68e73bb25b9982cca20a87c98686", + "precheck_sky130": "07ace967fbe88e33844bf046bd9d30e1679580b7" } -} +} \ No newline at end of file