)]}'
{
  "commit": "750803b4493b0ccf90f3d3b77b84bda0fc093904",
  "tree": "62dd441d856377006ab3bf9e26585143a7583557",
  "parents": [
    "05fda41fac52b44772d1b8467b1c184fdc7aa7c4"
  ],
  "author": {
    "name": "mole99",
    "email": "leomoser99@gmail.com",
    "time": "Mon Jul 17 08:35:14 2023 +0200"
  },
  "committer": {
    "name": "mole99",
    "email": "leomoser99@gmail.com",
    "time": "Mon Jul 17 08:35:57 2023 +0200"
  },
  "message": "Include specify blocks in cell libraries\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "90162f042dee29a8ad6cd582430af916d30347bc",
      "old_mode": 33261,
      "old_path": "sky130/custom/scripts/fix_verilog.py",
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      "new_mode": 33261,
      "new_path": "sky130/custom/scripts/fix_verilog.py"
    },
    {
      "type": "modify",
      "old_id": "1dd663c8efddbdbdb2cafc37128fd88100dd6bc2",
      "old_mode": 33261,
      "old_path": "sky130/custom/scripts/inc_verilog.py",
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}