tree 9cafd5d646c7712a5db73ca172ea3a77844949da
parent e5d3206cc72b7afaed1e6972d59ea556511deba4
author R. Timothy Edwards <tim@opencircuitdesign.com> 1771465663 -0500
committer R. Timothy Edwards <tim@opencircuitdesign.com> 1771465663 -0500

Updated references after a major fix of verilog files in the
sky130_fd_sc_hs high-speed logic library.