)]}'
{
  "commit": "72e7163cd968fd5685201f388a936a1a4a3e679b",
  "tree": "9cafd5d646c7712a5db73ca172ea3a77844949da",
  "parents": [
    "e5d3206cc72b7afaed1e6972d59ea556511deba4"
  ],
  "author": {
    "name": "R. Timothy Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Feb 18 20:47:43 2026 -0500"
  },
  "committer": {
    "name": "R. Timothy Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Feb 18 20:47:43 2026 -0500"
  },
  "message": "Updated references after a major fix of verilog files in the\nsky130_fd_sc_hs high-speed logic library.\n",
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