tree dd4c05e8da6b8a3d17e16033331430029cc49608
parent b9795b7acefa1194d9bb429bbc4e8af1a088baf1
author Tim Edwards <tim@opencircuitdesign.com> 1670625579 -0500
committer Tim Edwards <tim@opencircuitdesign.com> 1670625579 -0500

Various corrections required for proper installation of GF180MCU.
Corrected the SPICE library generator (and verilog library
generator, which has the same issue, although the problem does
not get encountered that I'm aware of) to do a non-greedy match
to find the end of a subcircuit;  otherwise, the check for
redundant subcircuits in the multiple SPICE files can result in
deleting way too much from the library, resulting in missing
subcircuits.  Also:  Added to the script that creates the minimum
and maximum corner technology LEF files, to correct the values
for the wire capacitance per (square) unit length (the current
implementation is waiting on values to insert for the minimum
and maximum;  only the nominal case is corrected).