)]}'
{
  "commit": "715b5fe800e6b6a79e28e6e39652bdf749422d00",
  "tree": "dd4c05e8da6b8a3d17e16033331430029cc49608",
  "parents": [
    "b9795b7acefa1194d9bb429bbc4e8af1a088baf1"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Dec 09 17:39:39 2022 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Dec 09 17:39:39 2022 -0500"
  },
  "message": "Various corrections required for proper installation of GF180MCU.\nCorrected the SPICE library generator (and verilog library\ngenerator, which has the same issue, although the problem does\nnot get encountered that I\u0027m aware of) to do a non-greedy match\nto find the end of a subcircuit;  otherwise, the check for\nredundant subcircuits in the multiple SPICE files can result in\ndeleting way too much from the library, resulting in missing\nsubcircuits.  Also:  Added to the script that creates the minimum\nand maximum corner technology LEF files, to correct the values\nfor the wire capacitance per (square) unit length (the current\nimplementation is waiting on values to insert for the minimum\nand maximum;  only the nominal case is corrected).\n",
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