Various corrections required for proper installation of GF180MCU.
Corrected the SPICE library generator (and verilog library
generator, which has the same issue, although the problem does
not get encountered that I'm aware of) to do a non-greedy match
to find the end of a subcircuit; otherwise, the check for
redundant subcircuits in the multiple SPICE files can result in
deleting way too much from the library, resulting in missing
subcircuits. Also: Added to the script that creates the minimum
and maximum corner technology LEF files, to correct the values
for the wire capacitance per (square) unit length (the current
implementation is waiting on values to insert for the minimum
and maximum; only the nominal case is corrected).
diff --git a/VERSION b/VERSION
index aae5412..7e18090 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.370
+1.0.371
diff --git a/common/create_spice_library.py b/common/create_spice_library.py
index d26eddb..498ea1a 100755
--- a/common/create_spice_library.py
+++ b/common/create_spice_library.py
@@ -68,12 +68,13 @@
slist = glob.glob(destlibdir + '/*.cdl')
else:
# Sadly, there is no consensus on what a SPICE file extension should be.
- slist = glob.glob(destlibdir + '/*.spc')
- slist.extend(glob.glob(destlibdir + '/*.spice'))
- slist.extend(glob.glob(destlibdir + '/*.spi'))
- slist.extend(glob.glob(destlibdir + '/*.ckt'))
- slist.extend(glob.glob(destlibdir + '/*.cir'))
- slist.extend(glob.glob(destlibdir + '/*' + spiext))
+ spiexts = ['.spc', '.spice', '.spi', '.ckt', '.cir']
+ if spiext not in spiexts:
+ spiexts.append(spiext)
+ slist = []
+ for extension in spiexts:
+ slist.extend(glob.glob(destlibdir + '/*' + extension))
+
slist = natural_sort.natural_sort(slist)
if alllibname in slist:
@@ -105,7 +106,7 @@
subckts = re.findall(r'\.subckt[ \t]+([^ \t\n]+)', stext, flags=re.IGNORECASE)
sseen = list(item for item in subckts if item in allsubckts)
allsubckts.extend(list(item for item in subckts if item not in allsubckts))
- sfilter = remove_redundant_subckts(stext, allsubckts, sseen)
+ sfilter = remove_redundant_subckts(stext, subckts, sseen)
print(sfilter, file=ofile)
print('\n******* EOF\n', file=ofile)
@@ -137,17 +138,17 @@
for subckt in slist:
if subckt in sseen:
# Remove all occurrences of subckt
- updated = re.sub(r'\n\.subckt[ \t]+' + subckt + '[ \t\n]+.*\n\.ends[ \t\n]+', '\n', updated, flags=re.IGNORECASE | re.DOTALL)
+ updated = re.sub(r'\n\.subckt[ \t]+' + subckt + '[ \t\n]+.*?\n\.ends[ \t\n]+', '\n', updated, flags=re.IGNORECASE | re.DOTALL)
else:
# Determine the number of times the subcircuit appears in the text
- n = len(re.findall(r'\n\.subckt[ \t]+' + subckt + '[ \t\n]+.*\n\.ends[ \t\n]+', updated, flags=re.IGNORECASE | re.DOTALL))
+ n = len(re.findall(r'\n\.subckt[ \t]+' + subckt + '[ \t\n]+.*?\n\.ends[ \t\n]+', updated, flags=re.IGNORECASE | re.DOTALL))
# Optimization: Just keep original text if n < 2
if n < 2:
continue
# Remove all but one
- updated = re.sub(r'\n\.subckt[ \t]+' + subckt + '[ \t\n]+.*\n\.ends[ \t\n]+', '\n', n - 1, updated, flags=re.IGNORECASE | re.DOTALL)
+ updated = re.sub(r'\n\.subckt[ \t]+' + subckt + '[ \t\n]+.*?\n\.ends[ \t\n]+', '\n', n - 1, updated, flags=re.IGNORECASE | re.DOTALL)
return updated
#----------------------------------------------------------------------------
@@ -202,7 +203,7 @@
destlibdir = argumentlist[0]
destlib = argumentlist[1]
- startup_script = argumentlist[2]
+ spiext = argumentlist[2]
print('')
if spiext == '.cdl':
diff --git a/common/create_verilog_library.py b/common/create_verilog_library.py
index baa6624..d67c72b 100755
--- a/common/create_verilog_library.py
+++ b/common/create_verilog_library.py
@@ -121,18 +121,18 @@
# Determine the number of times the module appears in the text
if module in m2list:
# This module seen before outside of ntext, so remove all occurrances in ntext
- new = re.sub(r'[ \t\n]+module[ \t]+' + module + '[ \t\n\(]+.*[ \t\n]endmodule', '\n', updated, flags=re.DOTALL)
+ new = re.sub(r'[ \t\n]+module[ \t]+' + module + '[ \t\n\(]+.*?[ \t\n]endmodule', '\n', updated, flags=re.DOTALL)
updated = new
else:
- n = len(re.findall(r'[ \t\n]module[ \t]+' + module + '[ \t\n\(]+.*[ \t\n]endmodule', updated, flags=re.DOTALL))
+ n = len(re.findall(r'[ \t\n]module[ \t]+' + module + '[ \t\n\(]+.*?[ \t\n]endmodule', updated, flags=re.DOTALL))
# This module defined more than once inside ntext, so remove all but one
# Optimization: Just keep original text if n < 2
if n < 2:
continue
# Remove all but one
- updated = re.sub(r'[ \t\n]+module[ \t]+' + module + '[ \t\n]+.*[ \t\n]endmodule', '\n', n - 1, updated, flags=re.IGNORECASE | re.DOTALL)
+ updated = re.sub(r'[ \t\n]+module[ \t]+' + module + '[ \t\n]+.*?[ \t\n]endmodule', '\n', n - 1, updated, flags=re.IGNORECASE | re.DOTALL)
return updated
#----------------------------------------------------------------------------
diff --git a/common/foundry_install.py b/common/foundry_install.py
index 0b085e0..969908f 100755
--- a/common/foundry_install.py
+++ b/common/foundry_install.py
@@ -1701,11 +1701,14 @@
# write procedure, but we still need the pin use and class
# information from the LEF file, and maybe the bounding box.
-
# For annotation, the LEF file output will overwrite the
# original source LEF file.
lefdest = lefsrclibdir + '/' if have_lefanno else ''
+ # Delete the original files in case the naming is different
+ for leffile in leffiles:
+ print('file delete ' + lefsrclibdir + '/' + leffile, file=ofile)
+
for lefmacro in lefmacros:
print('if {[cellname list exists ' + lefmacro + '] != 0} {', file=ofile)
print(' load ' + lefmacro, file=ofile)
@@ -2259,7 +2262,7 @@
else:
gdslibroot = os.path.split(allgdslibname)[1]
print('load ' + os.path.splitext(gdslibroot)[0], file=ofile)
- # print('cellname delete \(UNNAMED\)', file=ofile)
+ print('catch {cellname delete \(UNNAMED\)}', file=ofile)
print('ext2spice lvs', file=ofile)
diff --git a/gf180mcu/Makefile.in b/gf180mcu/Makefile.in
index 620f997..44135eb 100644
--- a/gf180mcu/Makefile.in
+++ b/gf180mcu/Makefile.in
@@ -997,7 +997,7 @@
-gds cells/*/*_${$*_STACK}.gds compile-only \
options=custom/scripts/gds_import_io.tcl \
-lef cells/*/*_${$*_STACK}.lef \
- annotate untrusted lefopts=-hide compile-only \
+ annotate lefopts=-hide compile-only \
filter=custom/scripts/fix_io_lef.py \
-verilog cells/*/*.v compile-only \
-library general gf180mcu_fd_io 2>&1 | tee -a ${GF180MCU$*}_make.log
diff --git a/gf180mcu/custom/scripts/gds_import_io.tcl b/gf180mcu/custom/scripts/gds_import_io.tcl
index dd0395a..3a0147e 100644
--- a/gf180mcu/custom/scripts/gds_import_io.tcl
+++ b/gf180mcu/custom/scripts/gds_import_io.tcl
@@ -3,3 +3,4 @@
gds polygon subcells true
gds flatten true
gds flatglob *_CDNS_*
+# gds noduplicates true
diff --git a/gf180mcu/custom/scripts/make_minmax_techlef.py b/gf180mcu/custom/scripts/make_minmax_techlef.py
index e6446ab..de106e3 100755
--- a/gf180mcu/custom/scripts/make_minmax_techlef.py
+++ b/gf180mcu/custom/scripts/make_minmax_techlef.py
@@ -57,8 +57,11 @@
resrex1 = re.compile('^[ \t]*RESISTANCE RPERSQ')
resrex2 = re.compile('^[ \t]*ARRAYSPACING')
layerrex = re.compile('^[ \t]*LAYER ([^ \t\n]+)')
+caprex = re.compile('^[ \t]*CAPACITANCE CPERSQDIST')
+#--------------------------------------------------------------------
# Resistance values, by layer
+#--------------------------------------------------------------------
rnom = {}
rmin = {}
@@ -115,6 +118,19 @@
rmin['Metal5'] = '0.050'
#--------------------------------------------------------------------
+# Capacitance values, by layer
+#--------------------------------------------------------------------
+
+cnom = {}
+
+cnom['Metal1'] = '0.0004'
+cnom['Metal2'] = '0.0003'
+cnom['Metal3'] = '0.00028'
+cnom['Metal4'] = '0.000277'
+if variant == 'gf180mcuC':
+ cnom['Metal5'] = '0.000174'
+
+#--------------------------------------------------------------------
infile_name = tlefpath + '/' + tlefnom
print('Creating minimum and maximum corner variants of ' + infile_name)
@@ -133,9 +149,11 @@
else:
outfile = open(outfile_name, 'w')
curlayer = None
- value = None
+ rvalue = None
+ cvalue = None
for line in infile:
+ cmatch = caprex.match(line)
rmatch1 = resrex1.match(line)
rmatch2 = resrex2.match(line)
lmatch = layerrex.match(line)
@@ -143,20 +161,52 @@
curlayer = lmatch.group(1)
if curlayer in rnom:
if corner == 'min':
- value = rmin[curlayer]
+ try:
+ rvalue = rmin[curlayer]
+ except:
+ rvalue = None
elif corner == 'max':
- value = rmax[curlayer]
+ try:
+ rvalue = rmax[curlayer]
+ except:
+ rvalue = None
else:
- value = rnom[curlayer]
+ try:
+ rvalue = rnom[curlayer]
+ except:
+ rvalue = None
else:
- value = None
+ rvalue = None
+ if curlayer in cnom:
+ if corner == 'min':
+ try:
+ cvalue = cmin[curlayer]
+ except:
+ cvalue = None
+ elif corner == 'max':
+ try:
+ cvalue = cmax[curlayer]
+ except:
+ cvalue = None
+ else:
+ try:
+ cvalue = cnom[curlayer]
+ except:
+ cvalue = None
+ else:
+ cvalue = None
outfile.write(line)
- elif value and rmatch1:
- outfile.write(' RESISTANCE RPERSQ ' + value + ' ;\n')
- elif value and rmatch2:
+ elif rvalue and rmatch1:
+ print('Layer ' + curlayer + ': Rewriting resistance rpersq as value ' + rvalue)
+ outfile.write(' RESISTANCE RPERSQ ' + rvalue + ' ;\n')
+ elif rvalue and rmatch2:
outfile.write(line)
outfile.write('')
- outfile.write(' RESISTANCE ' + value + ' ;\n')
+ print('Layer ' + curlayer + ': Adding (via) resistance as value ' + rvalue)
+ outfile.write(' RESISTANCE ' + rvalue + ' ;\n')
+ elif cvalue and cmatch:
+ print('Layer ' + curlayer + ': Rewriting capacitance cpersqdist as value ' + cvalue)
+ outfile.write(' CAPACITANCE CPERSQDIST ' + cvalue + ' ;\n')
else:
outfile.write(line)
@@ -165,3 +215,5 @@
if infile_name == outfile_name:
os.rename(outfile_name + 'x', outfile_name)
+
+ print('Generated file ' + outfile_name + ' (Done)')
