openlane support for latch mapping in synthesis
diff --git a/sky130/openlane/config.tcl b/sky130/openlane/config.tcl
index cffa0e3..5c37eaa 100755
--- a/sky130/openlane/config.tcl
+++ b/sky130/openlane/config.tcl
@@ -40,6 +40,9 @@
# Tracks info
set ::env(TRACKS_INFO_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/tracks.info"
+# Latch mapping
+set ::env(SYNTH_LATCH_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/latch_map.v"
+
set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
# Extra PDN configs
diff --git a/sky130/openlane/sky130_fd_sc_hd/latch_map.v b/sky130/openlane/sky130_fd_sc_hd/latch_map.v
new file mode 100644
index 0000000..204ce88
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hd/latch_map.v
@@ -0,0 +1,21 @@
+module \$_DLATCH_P_ (input E, input D, output Q);
+ sky130_fd_sc_hd__dlxtp_1 _TECHMAP_DLATCH_P (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE(E)
+ );
+endmodule
+
+module \$_DLATCH_N_ (input E, input D, output Q);
+ sky130_fd_sc_hd__dlxtn_1 _TECHMAP_DLATCH_N (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE_N(E)
+ );
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hdll/latch_map.v b/sky130/openlane/sky130_fd_sc_hdll/latch_map.v
new file mode 100644
index 0000000..4a27aa7
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hdll/latch_map.v
@@ -0,0 +1,21 @@
+module \$_DLATCH_P_ (input E, input D, output Q);
+ sky130_fd_sc_hdll__dlxtp_1 _TECHMAP_DLATCH_P (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE(E)
+ );
+endmodule
+
+module \$_DLATCH_N_ (input E, input D, output Q);
+ sky130_fd_sc_hdll__dlxtn_1 _TECHMAP_DLATCH_N (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE_N(E)
+ );
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hs/latch_map.v b/sky130/openlane/sky130_fd_sc_hs/latch_map.v
new file mode 100644
index 0000000..9dd8167
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hs/latch_map.v
@@ -0,0 +1,21 @@
+module \$_DLATCH_P_ (input E, input D, output Q);
+ sky130_fd_sc_hs__dlxtp_1 _TECHMAP_DLATCH_P (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE(E)
+ );
+endmodule
+
+module \$_DLATCH_N_ (input E, input D, output Q);
+ sky130_fd_sc_hs__dlxtn_1 _TECHMAP_DLATCH_N (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE_N(E)
+ );
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hvl/latch_map.v b/sky130/openlane/sky130_fd_sc_hvl/latch_map.v
new file mode 100644
index 0000000..7cd80d4
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hvl/latch_map.v
@@ -0,0 +1,10 @@
+module \$_DLATCH_P_ (input E, input D, output Q);
+ sky130_fd_sc_hvl__dlxtp_1 _TECHMAP_DLATCH_P (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE(E)
+ );
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_ls/latch_map.v b/sky130/openlane/sky130_fd_sc_ls/latch_map.v
new file mode 100644
index 0000000..319ff5a
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_ls/latch_map.v
@@ -0,0 +1,21 @@
+module \$_DLATCH_P_ (input E, input D, output Q);
+ sky130_fd_sc_ls__dlxtp_1 _TECHMAP_DLATCH_P (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE(E)
+ );
+endmodule
+
+module \$_DLATCH_N_ (input E, input D, output Q);
+ sky130_fd_sc_ls__dlxtn_1 _TECHMAP_DLATCH_N (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE_N(E)
+ );
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_ms/latch_map.v b/sky130/openlane/sky130_fd_sc_ms/latch_map.v
new file mode 100644
index 0000000..3bb5946
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_ms/latch_map.v
@@ -0,0 +1,21 @@
+module \$_DLATCH_P_ (input E, input D, output Q);
+ sky130_fd_sc_ms__dlxtp_1 _TECHMAP_DLATCH_P (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE(E)
+ );
+endmodule
+
+module \$_DLATCH_N_ (input E, input D, output Q);
+ sky130_fd_sc_ms__dlxtn_1 _TECHMAP_DLATCH_N (
+ //# {{data|Data Signals}}
+ .D(D),
+ .Q(Q),
+
+ //# {{clocks|Clocking}}
+ .GATE_N(E)
+ );
+endmodule
