Merge branch 'master' of opencircuitdesign.com:/home/tim/gitsrc/open_pdks/ into HEAD
Pulling before merging pull request
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index 2e805da..d509361 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -72,6 +72,7 @@
#--------------------------------------------------------------------
# This Makefile contains bash-isms
SHELL = bash
+MV = mv
REVISION = 20200927
TECH = sky130
@@ -271,7 +272,7 @@
${QFLOW_STAGING_A}/${SKY130A}ls.sh
${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_ms qflow/${TECH}.sh > \
${QFLOW_STAGING_A}/${SKY130A}ms.sh
- ${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_osu_sc qflow/sky130osu.sh > \
+ ${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_osu_sc_t18 qflow/sky130osu.sh > \
${QFLOW_STAGING_A}/${SKY130A}osu.sh
${CPP} ${SKY130A_DEFS} qflow/${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}hd.par
${CPP} ${SKY130A_DEFS} qflow/${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}hdll.par
@@ -298,7 +299,7 @@
${CPP} ${SKY130A_DEFS} klayout/${TECH}.lyp > ${KLAYOUT_STAGING_A}/${SKY130A}.lyp
${CPP} ${SKY130A_DEFS} klayout/${TECH}.lyt > ${KLAYOUT_STAGING_A}/${SKY130A}.lyt
-openlane-a: openlane/common_pdn.tcl openlane/config.tcl openlane/sky130_fd_sc_hd/config.tcl openlane/sky130_fd_sc_hs/config.tcl openlane/sky130_fd_sc_ms/config.tcl openlane/sky130_fd_sc_ls/config.tcl openlane/sky130_fd_sc_hdll/config.tcl
+openlane-a: openlane/common_pdn.tcl openlane/config.tcl openlane/sky130_fd_sc_hd/config.tcl openlane/sky130_fd_sc_hs/config.tcl openlane/sky130_fd_sc_ms/config.tcl openlane/sky130_fd_sc_ls/config.tcl openlane/sky130_fd_sc_hdll/config.tcl openlane/sky130_osu_sc_t18/config.tcl
mkdir -p ${OPENLANETOP_STAGING_A}
mkdir -p ${OPENLANE_STAGING_A}
mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_hd
@@ -307,6 +308,7 @@
mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_ms
mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll
mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl
+ mkdir -p ${OPENLANE_STAGING_A}/sky130_osu_sc_t18
rm -f ${OPENLANE_STAGING_A}/common_pdn.info
rm -f ${OPENLANE_STAGING_A}/config.tcl
rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/config.tcl
@@ -328,6 +330,8 @@
rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/config.tcl
rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/tracks.info
rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/no_synth.cells
+ rm -f ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/config.tcl
+ rm -f ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/tracks.info
${CPP} ${SKY130A_DEFS} openlane/common_pdn.tcl > ${OPENLANE_STAGING_A}/common_pdn.tcl
${CPP} ${SKY130A_DEFS} openlane/config.tcl > ${OPENLANE_STAGING_A}/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/config.tcl
@@ -349,6 +353,8 @@
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/tracks.info
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/no_synth.cells
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_osu_sc_t18/config.tcl > ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/config.tcl
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_osu_sc_t18/tracks.info > ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/tracks.info
vendor-a:
# Install device subcircuits from vendor files
@@ -429,6 +435,16 @@
${RM} ${STAGING_PATH}/${SKY130A}/libs.ref/sky130_fd_sc_ms/verilog/*.*.v
${RM} ${STAGING_PATH}/${SKY130A}/libs.ref/sky130_fd_sc_ls/verilog/*.*.v
${RM} ${STAGING_PATH}/${SKY130A}/libs.ref/sky130_fd_sc_lp/verilog/*.*.v
+ # Install OSU digital standard cells.
+ ${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \
+ -techlef %l/latest/lef/sky130_osu_sc.tlef \
+ -cdl %l/latest/cdl/*.cdl ignore=topography compile-only \
+ -lef %l/latest/lef/*.lef compile-only \
+ -lib %l/latest/lib/*.lib \
+ -gds %l/latest/gds/*.gds compile-only \
+ -library digital sky130_osu_sc_t18 |& tee -a ${SKY130A}_install.log
+ # Renaming. Can it be avoided or simplified ?
+ ${MV} ${STAGING_PATH}/${SKY130A}/libs.ref/sky130_osu_sc_t18/techlef/sky130_osu_sc.tlef ${STAGING_PATH}/${SKY130A}/libs.ref/sky130_osu_sc_t18/techlef/sky130_osu_sc_t18.tlef
# Install OSU digital standard cells.
# ${STAGE} -source ${OSU_PATH} -target ${STAGING_PATH}/${SKY130A} \
# -techlef char/techfiles/scs8.lef rename sky130_osu_sc.tlef \
diff --git a/sky130/magic/sky130.magicrc b/sky130/magic/sky130.magicrc
index db999db..7fe3735 100644
--- a/sky130/magic/sky130.magicrc
+++ b/sky130/magic/sky130.magicrc
@@ -60,6 +60,7 @@
addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
} else {
addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
@@ -71,6 +72,7 @@
addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
}
# add path to GDS cells
@@ -86,6 +88,7 @@
path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_ls
path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_ms
path cell +${PDKPATH}/libs.ref/gds/sky130_osu130
+ path cell +${PDKPATH}/libs.ref/gds/sky130_osu130_t18
} else {
path cell ${PDKPATH}/libs.ref/sky130_fd_pr/gds
path cell +${PDKPATH}/libs.ref/sky130_fd_io/gds
@@ -97,6 +100,7 @@
path cell +${PDKPATH}/libs.ref/sky130_fd_sc_ls/gds
path cell +${PDKPATH}/libs.ref/sky130_fd_sc_ms/gds
path cell +${PDKPATH}/libs.ref/sky130_osu130/gds
+ path cell +${PDKPATH}/libs.ref/sky130_osu130_t18/gds
}
#endif (FULLTECH)
diff --git a/sky130/openlane/sky130_osu_sc_t18/config.tcl b/sky130/openlane/sky130_osu_sc_t18/config.tcl
new file mode 100755
index 0000000..1e5ac36
--- /dev/null
+++ b/sky130/openlane/sky130_osu_sc_t18/config.tcl
@@ -0,0 +1,73 @@
+set current_folder [file dirname [file normalize [info script]]]
+# Technology lib
+
+#ifdef EF_FORMAT
+set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(STD_CELL_LIBRARY)/sky130_osu_sc_TT_1P8_25C.lib"
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(STD_CELL_LIBRARY)/sky130_osu_sc_FF_1P8_25C.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(STD_CELL_LIBRARY)/sky130_osu_sc_SS_1p8_25C.lib"
+#else (!EF_FORMAT)
+set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_osu_sc_TT_1P8_25C.lib"
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_osu_sc_FF_1P8_25C.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_osu_sc_SS_1P8_25C.lib"
+#endif (!EF_FORMAT)
+
+set ::env(LIB_TYPICAL) $::env(LIB_SYNTH)
+
+# Placement site for core cells
+# This can be found in the technology lef (SITE)
+set ::env(PLACE_SITE) "s8_osu130"
+set ::env(PLACE_SITE_WIDTH) 0.11
+set ::env(PLACE_SITE_HEIGHT) 7.2
+
+# welltap and endcap cells
+# Does not exist in OSU cells. Taps are included in each cell.
+# set ::env(FP_WELLTAP_CELL) "sky130_osu_sc_t18__tapvpwrvgnd_1"
+# set ::env(FP_ENDCAP_CELL) "sky130_osu_sc_t18__decap_3"
+
+# defaults (can be overridden by designs):
+set ::env(SYNTH_DRIVING_CELL) "INVX8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+# capacitance : 0.037357;
+# update these
+set ::env(SYNTH_CAP_LOAD) "37.357" ; # femtofarad INVX8 pin A cap
+set ::env(SYNTH_MIN_BUF_PORT) "BUFX1 A Y"
+set ::env(SYNTH_TIEHI_PORT) "TIEHI Y"
+set ::env(SYNTH_TIELO_PORT) "TIELO Y"
+
+# Power pins
+set ::env(VDD_PIN) "vdd"
+set ::env(GND_PIN) "gnd"
+
+# cts defaults
+set ::env(CTS_ROOT_BUFFER) CLKBUFX1
+set ::env(CELL_CLK_PORT) CK
+
+# Placement defaults
+set ::env(PL_LIB) $::env(LIB_TYPICAL)
+
+# Fillcell insertion - do decap cell
+set ::env(FILL_CELL) "FILLX"
+set ::env(DECAP_CELL) ""
+set ::env(RE_BUFFER_CELL) "BUFX4"
+
+
+# Diode insertion
+set ::env(DIODE_CELL) "ANTFILL"
+#set ::env(FAKEDIODE_CELL) "sky130_osu_sc_t18__fakediode_2"
+set ::env(DIODE_CELL_PIN) "A"
+
+set ::env(CELL_PAD) 8
+set ::env(CELL_PAD_EXECLUDE) "FILLX*"
+
+# Clk Buffers info CTS data
+set ::env(ROOT_CLK_BUFFER) CLKBUFX1
+set ::env(CLK_BUFFER) CLKBUFX1
+set ::env(CLK_BUFFER_INPUT) A
+set ::env(CLK_BUFFER_OUTPUT) Y
+set ::env(CTS_CLK_BUFFER_LIST) "CLKBUFX1"
+# TODO...
+set ::env(CTS_SQR_CAP) 0.258e-3
+set ::env(CTS_SQR_RES) 0.125
+set ::env(CTS_MAX_CAP) 1.53169
+
+set ::env(FP_PDN_RAIL_WIDTH) 0.48
diff --git a/sky130/openlane/sky130_osu_sc_t18/tracks.info b/sky130/openlane/sky130_osu_sc_t18/tracks.info
new file mode 100644
index 0000000..48f6426
--- /dev/null
+++ b/sky130/openlane/sky130_osu_sc_t18/tracks.info
@@ -0,0 +1,12 @@
+li1 X 0 0.40
+li1 Y 0 0.40
+met1 X 0 0.40
+met1 Y 0 0.40
+met2 Y 0.24 0.48
+met2 X 0.24 0.48
+met3 X 0.37 0.74
+met3 Y 0.37 0.74
+met4 X 0.48 0.96
+met4 Y 0.48 0.96
+met5 X 1.85 3.7
+met5 Y 1.85 3.7
diff --git a/sky130/qflow/sky130osu.sh b/sky130/qflow/sky130osu.sh
index 4afd9bd..168bb64 100644
--- a/sky130/qflow/sky130osu.sh
+++ b/sky130/qflow/sky130osu.sh
@@ -9,21 +9,21 @@
#ifdef EF_FORMAT
set leffile=STAGING_PATH/TECHNAME/libs.ref/lef/sky130_osu130/sky130_osu130.lef
#else (!EF_FORMAT)
-set leffile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/lef/sky130_osu130.lef
+set leffile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/lef/sky130_osu130.lef
#endif (!EF_FORMAT)
# The SPICE netlist containing subcell definitions for all the standard cells
#ifdef EF_FORMAT
set spicefile=STAGING_PATH/TECHNAME/libs.ref/spice/sky130_osu130/sky130_osu130.spice
#else (!EF_FORMAT)
-set spicefile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/spice/sky130_osu130.spice
+set spicefile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/spice/sky130_osu130.spice
#endif (!EF_FORMAT)
# The liberty format file containing standard cell timing and function information
#ifdef EF_FORMAT
set libertyfile=STAGING_PATH/TECHNAME/libs.ref/lib/sky130_osu130/sky130_osu130.lib
#else (!EF_FORMAT)
-set libertyfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/lib/sky130_osu130.lib
+set libertyfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/lib/sky130_osu130.lib
#endif (!EF_FORMAT)
# If there is another LEF file containing technology information
@@ -34,7 +34,7 @@
#ifdef EF_FORMAT
set techleffile=STAGING_PATH/TECHNAME/libs.ref/techLEF/sky130_osu130/sky130_osu130_tech.lef
#else (!EF_FORMAT)
-set techleffile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/techLEF/sky130_osu130_tech.lef
+set techleffile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/techLEF/sky130_osu130_tech.lef
#endif (!EF_FORMAT)
#else
# NOTE: There is no technology LEF file for the 3-metal stack!
@@ -52,16 +52,16 @@
set clkbufpin_out=Y ;# Name of output port to buffer cell
set fillcell=FILL ;# Spacer (filler) cell (prefix, if more than one)
-set decapcell="" ;# Decap (filler) cell (prefix, if more than one)
-set antennacell="" ;# Antenna (filler) cell (prefix, if more than one)
-set antennapin_in="" ;# Antenna cell input connection
+set decapcell="DECAP" ;# Decap (filler) cell (prefix, if more than one)
+set antennacell="ANT" ;# Antenna (filler) cell (prefix, if more than one)
+set antennapin_in="A" ;# Antenna cell input connection
set bodytiecell="" ;# Body tie (filler) cell (prefix, if more than one)
# yosys tries to eliminate use of these; depends on source .v
-set tiehi="" ;# Cell to connect to power, if one exists
-set tiehipin_out="" ;# Output pin name of tiehi cell, if it exists
-set tielo="" ;# Cell to connect to ground, if one exists
-set tielopin_out="" ;# Output pin name of tielo cell, if it exists
+set tiehi="TIEHI" ;# Cell to connect to power, if one exists
+set tiehipin_out="Y" ;# Output pin name of tiehi cell, if it exists
+set tielo="TIELO" ;# Cell to connect to ground, if one exists
+set tielopin_out="Y" ;# Output pin name of tielo cell, if it exists
set gndnet="vdd" ;# Name used for ground pins in standard cells
set vddnet="vss" ;# Name used for power pins in standard cells
@@ -72,11 +72,11 @@
set magic_display="XR" ;# magic display, defeat display query and OGL preference
set netgen_setup=STAGING_PATH/TECHNAME/libs.tech/netgen/TECHNAME_setup.tcl ;# netgen setup file for LVS
#ifdef EF_FORMAT
-set gdsfile=STAGING_PATH/TECHNAME/libs.ref/gds/sky130_osu130/sky130_osu130.gds ;# GDS database of standard cells
-set verilogfile=STAGING_PATH/TECHNAME/libs.ref/verilog/sky130_osu130/sky130_osu130.v ;# Verilog models of standard cells
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/gds/LIBRARY/sky130_osu130.gds ;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/verilog/LIBRARY/sky130_osu130.v ;# Verilog models of standard cells
#else (!EF_FORMAT)
-set gdsfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/gds/sky130_osu130.gds ;# GDS database of standard cells
-set verilogfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/verilog/sky130_osu130.v ;# Verilog models of standard cells
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/gds/sky130_osu130.gds ;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/verilog/sky130_osu130.v ;# Verilog models of standard cells
#endif (!EF_FORMAT)
# Set a conditional default in the project_vars.sh file for this process
