)]}'
{
  "commit": "6a8bf1c6467ac346b9948478c0af686a1dcc0550",
  "tree": "b1908576cd5c2da960e3a699fe303d52593fbf89",
  "parents": [
    "929c8a22b5b19b53ae5333979aae725064957501"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Nov 30 21:36:11 2022 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Nov 30 21:36:11 2022 -0500"
  },
  "message": "Modified the liberty and verilog filters for gf180mcu to prevent\nthe filltie and endcap cells from being given the well and substrate\npins.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5576eb1b3c8b85bfaba2638bd8b27228fac8afb3",
      "old_mode": 33261,
      "old_path": "gf180mcu/custom/scripts/fix_related_bias_pins.py",
      "new_id": "19b4c05c4fb68b02b53b5ed126997cdc0186ce5e",
      "new_mode": 33261,
      "new_path": "gf180mcu/custom/scripts/fix_related_bias_pins.py"
    },
    {
      "type": "modify",
      "old_id": "2472a02b7c0a60ea84096e16d0c123ac76d2939d",
      "old_mode": 33261,
      "old_path": "gf180mcu/custom/scripts/inc_verilog.py",
      "new_id": "b13eda42caa55b540e73cab84b4c8fcf8ff7edb2",
      "new_mode": 33261,
      "new_path": "gf180mcu/custom/scripts/inc_verilog.py"
    }
  ]
}