Install fakediode properly - rename it to sky130_ef_sc_hd__fakediode_2 - install along with the sky130_fd_sc_hd library
diff --git a/sky130/Makefile.in b/sky130/Makefile.in index c78bdcb..2b6d895 100644 --- a/sky130/Makefile.in +++ b/sky130/Makefile.in
@@ -302,6 +302,7 @@ openlane-a: openlane/common_pdn.tcl openlane/config.tcl openlane/sky130_fd_sc_hd/config.tcl openlane/sky130_fd_sc_hs/config.tcl openlane/sky130_fd_sc_ms/config.tcl openlane/sky130_fd_sc_ls/config.tcl openlane/sky130_fd_sc_hdll/config.tcl openlane/sky130_osu_sc_t18/config.tcl mkdir -p ${OPENLANETOP_STAGING_A} mkdir -p ${OPENLANE_STAGING_A} + rm -f ${OPENLANE_STAGING_A}/custom_cells mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_hd mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_hs mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_ls @@ -314,7 +315,6 @@ rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/config.tcl rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/tracks.info rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/no_synth.cells - rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/sky130_fd_sc_hd__fakediode_2.gds rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/config.tcl rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/tracks.info rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/no_synth.cells @@ -332,12 +332,12 @@ rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/no_synth.cells rm -f ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/config.tcl rm -f ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/tracks.info + cp -r openlane/custom_cells ${OPENLANE_STAGING_A} ${CPP} ${SKY130A_DEFS} openlane/common_pdn.tcl > ${OPENLANE_STAGING_A}/common_pdn.tcl ${CPP} ${SKY130A_DEFS} openlane/config.tcl > ${OPENLANE_STAGING_A}/config.tcl ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/config.tcl ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/tracks.info ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/no_synth.cells - cp openlane/sky130_fd_sc_hd/sky130_fd_sc_hd__fakediode_2.gds ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/sky130_fd_sc_hd__fakediode_2.gds ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/config.tcl ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/tracks.info ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/no_synth.cells @@ -404,6 +404,11 @@ # Remove the base verilog files which have already been included into # the libraries ${RM} ${STAGING_PATH}/${SKY130A}/libs.ref/sky130_fd_io/verilog/*.*.v + # Install custom additions to standard cell libraries + ${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \ + -gds %l/gds/*.gds \ + -lef %l/lef/*.lef \ + -library digital sky130_fd_sc_hd |& tee -a ${SKY130A}_install.log # Install all SkyWater digital standard cells. ${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \ -techlef %l/latest/tech/*.tlef \
diff --git a/sky130/openlane/sky130_fd_sc_hd/sky130_fd_sc_hd__fakediode_2.gds b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fakediode_2.gds similarity index 88% rename from sky130/openlane/sky130_fd_sc_hd/sky130_fd_sc_hd__fakediode_2.gds rename to sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fakediode_2.gds index d98d9a4..ff35a72 100644 --- a/sky130/openlane/sky130_fd_sc_hd/sky130_fd_sc_hd__fakediode_2.gds +++ b/sky130/custom/sky130_fd_sc_hd/gds/sky130_ef_sc_hd__fakediode_2.gds Binary files differ
diff --git a/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fakediode_2.lef b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fakediode_2.lef new file mode 100644 index 0000000..8eb1ae6 --- /dev/null +++ b/sky130/custom/sky130_fd_sc_hd/lef/sky130_ef_sc_hd__fakediode_2.lef
@@ -0,0 +1,54 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO sky130_ef_sc_hd__fakediode_2 + CLASS CORE SPACER ; + FOREIGN sky130_ef_sc_hd__fakediode_2 ; + ORIGIN 0.000 0.000 ; + SIZE 0.920 BY 2.720 ; + PIN DIODE + PORT + LAYER li1 ; + RECT 0.085 0.255 0.835 2.465 ; + END + END DIODE + PIN VGND + USE GROUND ; + PORT + LAYER li1 ; + RECT 0.000 -0.085 0.920 0.085 ; + LAYER mcon ; + RECT 0.145 -0.085 0.315 0.085 ; + RECT 0.605 -0.085 0.775 0.085 ; + LAYER met1 ; + RECT 0.000 -0.240 0.920 0.240 ; + END + END VGND + PIN VPWR + USE POWER ; + PORT + LAYER li1 ; + RECT 0.000 2.635 0.920 2.805 ; + LAYER mcon ; + RECT 0.145 2.635 0.315 2.805 ; + RECT 0.605 2.635 0.775 2.805 ; + LAYER met1 ; + RECT 0.000 2.480 0.920 2.960 ; + END + END VPWR + PIN VPB + PORT + LAYER nwell ; + RECT -0.190 1.305 1.110 2.910 ; + END + END VPB + PIN VNB + PORT + LAYER pwell ; + RECT 0.145 -0.085 0.315 0.085 ; + END + END VNB +END sky130_ef_sc_hd__fakediode_2 +END LIBRARY +
diff --git a/sky130/openlane/sky130_fd_sc_hd/config.tcl b/sky130/openlane/sky130_fd_sc_hd/config.tcl index 000ce19..25c5b9c 100755 --- a/sky130/openlane/sky130_fd_sc_hd/config.tcl +++ b/sky130/openlane/sky130_fd_sc_hd/config.tcl
@@ -47,7 +47,7 @@ # Diode insertaion set ::env(DIODE_CELL) "sky130_fd_sc_hd__diode_2" -set ::env(FAKEDIODE_CELL) "sky130_fd_sc_hd__fakediode_2" +set ::env(FAKEDIODE_CELL) "sky130_ef_sc_hd__fakediode_2" set ::env(DIODE_CELL_PIN) "DIODE" set ::env(CELL_PAD) 8