tree 4d5db7b5524d2741a4ce71ec6585c5d1e0ab0c7a
parent 6c05bc48dc88784f9d98b89d6791cdfd91526676
author Tim Edwards <tim@opencircuitdesign.com> 1632170432 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1632170432 -0400

Added some (disabled) code to the inc_verilog.py script which
inserts the "specify ... endspecify" block into each of the standard
cells in the verilog library.