)]}'
{
  "commit": "5d7229ee1ae02b0001bce7d7b81239a593b48682",
  "tree": "4d5db7b5524d2741a4ce71ec6585c5d1e0ab0c7a",
  "parents": [
    "6c05bc48dc88784f9d98b89d6791cdfd91526676"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Sep 20 16:40:32 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Sep 20 16:40:32 2021 -0400"
  },
  "message": "Added some (disabled) code to the inc_verilog.py script which\ninserts the \"specify ... endspecify\" block into each of the standard\ncells in the verilog library.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7e126a4f6fc93947736e04e7682c08d2850227d2",
      "old_mode": 33188,
      "old_path": "VERSION",
      "new_id": "e5a4b3e5b72747bc716a06b010f6c1a08180beeb",
      "new_mode": 33188,
      "new_path": "VERSION"
    },
    {
      "type": "modify",
      "old_id": "a090b677211fbbda3d5da3c18bccf42744b178f7",
      "old_mode": 33261,
      "old_path": "sky130/custom/scripts/inc_verilog.py",
      "new_id": "63f4595445488937793b5d03c78b3a9ec56e6a18",
      "new_mode": 33261,
      "new_path": "sky130/custom/scripts/inc_verilog.py"
    }
  ]
}