diff --git a/sky130/Makefile b/sky130/Makefile
new file mode 100644
index 0000000..2673519
--- /dev/null
+++ b/sky130/Makefile
@@ -0,0 +1,397 @@
+# Makefile for efabless design kits for SkyWater Sky130:
+#
+#  sky130A      =  5-metal backend stack with dual MiM
+#
+# Written by Tim Edwards March 2019
+# efabless corporation
+# updated October 2019
+# updated December 2019 (divide installation sections for individual tools)
+# updated March 2020 (refactored the install process)
+# updated May 2020 (changed to new process name Sky130)
+#
+# Instructions:
+#
+# Modify values below as needed:
+#
+#	VENDOR_PATH: points to vendor sources
+#	EF_STYLE: 1 for efabless style, 0 otherwise
+#	LINK_TARGETS: link back to source or link to 1st PDK when possible
+#	DIST_PATH: install location for distributed install
+#	LOCAL_PATH: install location for local install or runtime location
+#		    for distributed install
+#
+# Run "make" to stage the PDK for tool setup and vendor libraries
+
+# If installing into the final destination (local install):
+#
+#   Run "make install-local" to install all staged files
+#   ("make install" is equivalent to "make install-local")
+#
+# If installing into a repository to be distributed to the final destination:
+#
+#   Run "make install-dist" to install all staged files
+#
+# Run "make clean" to remove all staging files.
+#
+# Run "make veryclean" to remove all staging and install log files.
+#
+# For the sake of simplicity, the "standard" local install can be done
+# with the usual
+#
+#   make
+#   make install
+#   make clean
+#
+#--------------------------------------------------------------------
+# This Makefile contains bash-isms
+SHELL = bash
+
+REVISION    = 20200508
+TECH        = sky130
+
+# If EF_STYLE is set to 1, then efabless naming conventions are
+# used, otherwise the generic naming conventions are used.
+# Mainly, the hierarchy of library names and file types is reversed
+# (e.g., sky130_fd_sc_hd/lef vs. lef/sky130_fd_sc_hd).
+
+EF_STYLE = 0
+# EF_STYLE = 1
+
+# Normally it's fine to keep the staging path in a local directory,
+# although /tmp or a dedicated staging area are also fine, as long
+# as the install process can write to the path.
+
+STAGING_PATH = `pwd`
+
+# If LINK_TARGETS is set to "none", then files are copied
+# from the SkyWater sources to the target.  If set to "source",
+# symbolic links are made in the target directories pointing
+# back to the SkyWater sources.  If set to the name of another
+# PDK (e.g, "sky130A"), then symbolic links are made to the
+# same files in that PDK, where they exist, and are copied
+# from source, where they don't.
+
+# LINK_TARGETS = source
+# LINK_TARGETS = none
+# LINK_TARGETS = sky130A
+LINK_TARGETS = source
+
+# Paths:
+
+# Path to skywater_pdk (to be changed to public repo;  work in progress)
+# Version below comes from foss-eda-tools.googlesource.com
+# SKYWATER_PATH = ~/gits/skywater-pdk-scratch/skywater-pdk/libraries
+# Version below is also from foss-eda-tools and is more recent than
+# the scratch repo above.
+SKYWATER_PATH = ~/gits/skywater-pdk/libraries
+
+# NOTE:  Install destination is the git repository of the technology platform.
+# Once updated in git, the git project can be distributed to all hosts.
+#
+ifeq (${EF_STYLE}, 1)
+    LOCAL_PATH = /ef/tech/SW
+    CONFIG_DIR = .ef-config
+    REV_DIR = ${REVISION}
+else
+    # LOCAL_PATH = /usr/local/share/vlsi/SkyWater
+    LOCAL_PATH = ~/projects/efabless/tech/SW
+    CONFIG_DIR = .config
+    REV_DIR = .
+endif
+
+DIST_PATH = ~/gits/ef-skywater-${TECH}
+
+# EF process nodes created from the master sources
+SKY130A = sky130A
+
+ifeq (${LINK_TARGETS}, ${SKY130A})
+    DIST_LINK_TARGETS = ${LOCAL_PATH}/${LINK_TARGETS}
+else
+    DIST_LINK_TARGETS = ${LINK_TARGETS}
+endif
+
+# Basic definitions for each EF process node
+SKY130A_DEFS = -DTECHNAME=sky130A -DREVISION=${REVISION}
+
+# Module definitions for each process node
+# (Note that MOS is default and therefore not used anywhere)
+# SKY130A_DEFS += -DMETAL5 -DMIM -DREDISTRIBUTION
+SKY130A_DEFS += -DMETAL5 -DMIM
+
+# Add staging path
+SKY130A_DEFS += -DSTAGING_PATH=${STAGING_PATH}
+
+ifeq (${EF_STYLE}, 1)
+    EF_FORMAT = -ef_format
+    SKY130A_DEFS += -DEF_FORMAT
+else
+    EF_FORMAT = -std_format
+endif
+
+MAGICTOP = libs.tech/magic
+NETGENTOP = libs.tech/netgen
+QFLOWTOP = libs.tech/qflow
+KLAYOUTTOP = libs.tech/klayout
+OPENLANETOP = libs.tech/openlane
+
+ifeq (${EF_STYLE}, 1)
+    MAGICPATH = ${MAGICTOP}/${REVISION}
+else
+    MAGICPATH = ${MAGICTOP}
+endif
+
+# Currently, netgen, qflow, and klayout do not use revisioning (needs to change!)
+NETGENPATH = ${NETGENTOP}
+QFLOWPATH = ${QFLOWTOP}
+KLAYOUTPATH = ${KLAYOUTTOP}
+OPENLANEPATH = ${OPENLANETOP}
+
+MAGICTOP_STAGING_A = ${STAGING_PATH}/${SKY130A}/${MAGICTOP}
+NETGENTOP_STAGING_A = ${STAGING_PATH}/${SKY130A}/${NETGENTOP}
+QFLOWTOP_STAGING_A = ${STAGING_PATH}/${SKY130A}/${QFLOWTOP}
+KLAYOUTTOP_STAGING_A = ${STAGING_PATH}/${SKY130A}/${KLAYOUTTOP}
+OPENLANETOP_STAGING_A = ${STAGING_PATH}/${SKY130A}/${OPENLANETOP}
+
+MAGIC_STAGING_A = ${STAGING_PATH}/${SKY130A}/${MAGICPATH}
+NETGEN_STAGING_A = ${STAGING_PATH}/${SKY130A}/${NETGENPATH}
+QFLOW_STAGING_A = ${STAGING_PATH}/${SKY130A}/${QFLOWPATH}
+KLAYOUT_STAGING_A = ${STAGING_PATH}/${SKY130A}/${KLAYOUTPATH}
+OPENLANE_STAGING_A = ${STAGING_PATH}/${SKY130A}/${OPENLANEPATH}
+
+SKY130A_DEFS += -DMAGIC_CURRENT=${MAGICTOP}/current
+
+# Where cpp syntax is followed, this is equivalent to cpp, but it does not
+# mangle non-C source files under the belief that they are actually C code.
+CPP   = ../common/preproc.py
+
+# The following script in the ../common directory does most of the work of
+# copying or linking the foundry vendor files to the target directory.
+STAGE = set -f ; ../common/foundry_install.py ${EF_FORMAT}
+INSTALL = ../common/staging_install.py ${EF_FORMAT}
+
+# The script(s) below are used for custom changes to the vendor PDK files
+ADDPROP = ../common/insert_property.py ${EF_FORMAT} 
+
+# List the EDA tools to install local setup files for
+TOOLS = magic qflow netgen klayout openlane
+
+all: all-a
+
+all-a:
+	echo "Starting sky130A PDK staging on "`date` > ${SKY130A}_install.log
+	${MAKE} tools-a
+	${MAKE} vendor-a
+	echo "Ended sky130A PDK staging on "`date` >> ${SKY130A}_install.log
+
+tools-a: general-a magic-a qflow-a netgen-a klayout-a openlane-a
+
+general-a: ${TECH}.json
+	mkdir -p ${STAGING_PATH}/${SKY130A}/${CONFIG_DIR}
+	rm -f ${STAGING_PATH}/${SKY130A}/${CONFIG_DIR}/nodeinfo.json
+	${CPP} ${SKY130A_DEFS} ${TECH}.json > \
+		${STAGING_PATH}/${SKY130A}/${CONFIG_DIR}/nodeinfo.json
+
+magic-a: ${TECH}.tech ${TECH}gds.tech ${TECH}.magicrc ${TECH}.tcl
+	mkdir -p ${MAGICTOP_STAGING_A}
+	mkdir -p ${MAGIC_STAGING_A}
+	rm -f ${MAGICTOP_STAGING_A}/current
+	rm -f ${MAGIC_STAGING_A}/${SKY130A}.tech
+	rm -f ${MAGIC_STAGING_A}/${SKY130A}-GDS.tech
+	rm -f ${MAGIC_STAGING_A}/${SKY130A}.tcl
+	rm -f ${MAGIC_STAGING_A}/${SKY130A}-BindKeys
+	rm -f ${MAGIC_STAGING_A}/magicrc
+	(cd ${MAGICTOP_STAGING_A} ; ln -s ${REV_DIR} current)
+	cp -rp custom/scripts/seal_ring_generator ${MAGIC_STAGING_A}/.
+	${CPP} ${SKY130A_DEFS} ${TECH}.tech > ${MAGIC_STAGING_A}/${SKY130A}.tech
+	${CPP} ${SKY130A_DEFS} ${TECH}gds.tech > ${MAGIC_STAGING_A}/${SKY130A}-GDS.tech
+	${CPP} ${SKY130A_DEFS} ${TECH}.magicrc > ${MAGIC_STAGING_A}/${SKY130A}.magicrc
+	${CPP} ${SKY130A_DEFS} ../common/pdk.bindkeys > ${MAGIC_STAGING_A}/${SKY130A}-BindKeys
+	${CPP} ${SKY130A_DEFS} ${TECH}.tcl > ${MAGIC_STAGING_A}/${SKY130A}.tcl
+	${CPP} ${SKY130A_DEFS} ../common/pdk.tcl >> ${MAGIC_STAGING_A}/${SKY130A}.tcl
+
+qflow-a: ${TECH}.sh ${TECH}.par
+	mkdir -p ${QFLOWTOP_STAGING_A}
+	mkdir -p ${QFLOW_STAGING_A}
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hd.sh
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hd.par
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hdll.sh
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hdll.par
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hs.sh
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hs.par
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hvl.sh
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}hvl.par
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}ls.sh
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}ls.par
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}lp.sh
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}lp.par
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}ms.sh
+	rm -f ${QFLOW_STAGING_A}/${SKY130A}ms.par
+	${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_hd ${TECH}.sh > \
+		${QFLOW_STAGING_A}/${SKY130A}hd.sh
+	${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_hdll ${TECH}.sh > \
+		${QFLOW_STAGING_A}/${SKY130A}hdll.sh
+	${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_hvl ${TECH}.sh > \
+		${QFLOW_STAGING_A}/${SKY130A}hvl.sh
+	${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_hs ${TECH}.sh > \
+		${QFLOW_STAGING_A}/${SKY130A}hs.sh
+	${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_lp ${TECH}.sh > \
+		${QFLOW_STAGING_A}/${SKY130A}lp.sh
+	${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_ls ${TECH}.sh > \
+		${QFLOW_STAGING_A}/${SKY130A}ls.sh
+	${CPP} ${SKY130A_DEFS} -DLIBRARY=sky130_fd_sc_ms ${TECH}.sh > \
+		${QFLOW_STAGING_A}/${SKY130A}ms.sh
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}hd.par
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}hdll.par
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}hvl.par
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}hs.par
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}ms.par
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}lp.par
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}ls.par
+	${CPP} ${SKY130A_DEFS} ${TECH}.par > ${QFLOW_STAGING_A}/${SKY130A}osu.par
+
+netgen-a: ${TECH}_setup.tcl
+	mkdir -p ${NETGENTOP_STAGING_A}
+	mkdir -p ${NETGEN_STAGING_A}
+	rm -f ${NETGEN_STAGING_A}/${SKY130A}_setup.tcl
+	rm -f ${NETGEN_STAGING_A}/setup.tcl
+	${CPP} ${SKY130A_DEFS} ${TECH}_setup.tcl > ${NETGEN_STAGING_A}/${SKY130A}_setup.tcl
+	(cd ${NETGEN_STAGING_A} ; ln -s ${SKY130A}_setup.tcl setup.tcl)
+
+klayout-a: ${TECH}.lyp ${TECH}.lyt
+	mkdir -p ${KLAYOUTTOP_STAGING_A}
+	mkdir -p ${KLAYOUT_STAGING_A}
+	rm -f ${KLAYOUT_STAGING_A}/${SKY130A}.lyp
+	rm -f ${KLAYOUT_STAGING_A}/${SKY130A}.lyt
+	${CPP} ${SKY130A_DEFS} ${TECH}.lyp > ${KLAYOUT_STAGING_A}/${SKY130A}.lyp
+	${CPP} ${SKY130A_DEFS} ${TECH}.lyt > ${KLAYOUT_STAGING_A}/${SKY130A}.lyt
+
+openlane-a: common_pdn.tcl common_tracks.info config.tcl sky130_fd_sc_hd_config.tcl
+	mkdir -p ${OPENLANETOP_STAGING_A}
+	mkdir -p ${OPENLANE_STAGING_A}
+	mkdir -p ${OPENLANE_STAGING_A}/sky130_fd_sc_hd
+	rm -f ${OPENLANE_STAGING_A}/common_pdn.info
+	rm -f ${OPENLANE_STAGING_A}/common_tracks.info
+	rm -f ${OPENLANE_STAGING_A}/config.tcl
+	rm -f ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/config.tcl
+	${CPP} ${SKY130A_DEFS} common_pdn.tcl > ${OPENLANE_STAGING_A}/common_pdn.tcl
+	${CPP} ${SKY130A_DEFS} common_tracks.info > ${OPENLANE_STAGING_A}/common_tracks.info
+	${CPP} ${SKY130A_DEFS} config.tcl > ${OPENLANE_STAGING_A}/config.tcl
+	${CPP} ${SKY130A_DEFS} sky130_fd_sc_hd_config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/config.tcl
+
+vendor-a:
+	# Install base device models from vendor files
+	# (NOTE: .mod and .pm3 files should not be in /cells/?)
+	${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \
+		-ngspice sky130_fd_pr_base/v%v/models/* filter=custom/scripts/fixspice.py \
+		-ngspice sky130_fd_pr_base/v%v/cells/*.mod filter=custom/scripts/fixspice.py \
+		-ngspice sky130_fd_pr_base/v%v/cells/*.pm3 filter=custom/scripts/fixspice.py \
+		|& tee -a ${SKY130A}_install.log
+	# Install RF device models from vendor files
+	${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \
+		-ngspice sky130_fd_pr_rf/v%v/models/* filter=custom/scripts/fixspice.py \
+		|& tee -a ${SKY130A}_install.log
+	# Install additional RF device models from vendor files
+	${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \
+		-ngspice sky130_fd_pr_rf2/v%v/models/* filter=custom/scripts/fixspice.py \
+		|& tee -a ${SKY130A}_install.log
+	# Install base device library from vendor files
+	${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \
+		-gds %l/v%v/cells/*/*.gds \
+		-spice %l/v%v/cells/*/*.spice ignore=topography \
+		-spice %l/v%v/cells/*/*.sp \
+		-library primitive sky130_fd_pr_base \
+		-library primitive sky130_fd_pr_rf \
+		-library primitive sky130_fd_pr_rf2 |& tee -a ${SKY130A}_install.log
+	# Install SkyWater I/O pad library
+	# Purposely ignoring "-lef sky130_fd_io/v%v/lef/*.lef" and making our own LEF views
+	${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \
+		-gds %l/v%v/cells/*/*.gds \
+		-verilog %l/v%v/cells/*/*.v \
+		-lib %l/v%v/cells/*/*.lib \
+		-doc %l/v%v/cells/*/*.doc \
+		-cdl %l/v%v/cells/*/*.cdl ignore=topography \
+		-spice %l/v%v/cells/*/*.spice  \
+		-library general sky130_fd_io |& tee -a ${SKY130A}_install.log
+        # Install all SkyWater digital standard cells.
+	${STAGE} -source ${SKYWATER_PATH} -target ${STAGING_PATH}/${SKY130A} \
+		-spice %l/v%v/cells/*/*.spice compile-only \
+		-cdl %l/v%v/cells/*/*.cdl ignore=topography compile-only \
+		-lef %l/v%v/cells/*/*.lef compile-only \
+		-doc %l/v%v/cells/*/*.pdf \
+		-lib %l/v%v/timing/*.lib \
+		-gds %l/v%v/cells/*/*.gds compile-only \
+		-verilog %l/v%v/cells/*/*.v exclude=*.*.v compile-only \
+		-library digital sky130_fd_sc_hd \
+		-library digital sky130_fd_sc_hdll \
+		-library digital sky130_fd_sc_hvl \
+		-library digital sky130_fd_sc_hs \
+		-library digital sky130_fd_sc_ls \
+		-library digital sky130_fd_sc_ms \
+		-library digital sky130_fd_sc_lp |& tee -a ${SKY130A}_install.log
+	# Install additional model file (efabless)
+	${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
+		-ngspice models/*.lib rename ${SKY130A}.lib \
+		|& tee -a ${SKY130A}_install.log
+	# Install custom additions to digital libraries
+	${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
+		-techlef techLEF/sky130_fd_sc_hd_tech.lef \
+		-library digital sky130_fd_sc_hd |& tee -a ${SKY130A}_install.log
+	${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
+		-techlef techLEF/sky130_fd_sc_hd_tech.lef \
+			rename sky130_fd_sc_hdll_tech.lef \
+		-library digital sky130_fd_sc_hdll |& tee -a ${SKY130A}_install.log
+	${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
+		-techlef techLEF/sky130_fd_sc_hs_tech.lef \
+		-library digital sky130_fd_sc_hs |& tee -a ${SKY130A}_install.log
+	${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
+		-techlef techLEF/sky130_fd_sc_hs_tech.lef \
+			rename sky130_fd_sc_ms_tech.lef \
+		-library digital sky130_fd_sc_ms |& tee -a ${SKY130A}_install.log
+	${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
+		-techlef techLEF/sky130_fd_sc_hs_tech.lef \
+			rename sky130_fd_sc_ls_tech.lef \
+		-library digital sky130_fd_sc_ls |& tee -a ${SKY130A}_install.log
+	# Install custom additions to I/O pad library
+	${STAGE} -source ./custom -target ${STAGING_PATH}/${SKY130A} \
+		-gds %l/gds/*.gds \
+		-verilog %l/verilog/*.v \
+		-lef %l/lef/*.lef \
+		-spice %l/spice/*.spice \
+		-library general sky130_fd_io |& tee -a ${SKY130A}_install.log
+	# Add correct bounding boxes on Magic layouts
+	${ADDPROP} ${STAGING_PATH}/${SKY130A} sky130_fd_io sky130_fd_io_top_gpio_ovtv2 \
+		"FIXED_BBOX 0 407 28000 40000"
+	${ADDPROP} ${STAGING_PATH}/${SKY130A} sky130_fd_io sky130_fd_io_top_xres4v2 \
+		"FIXED_BBOX 0 407 15000 40000"
+
+install: install-local
+
+install-local: install-local-a
+
+install-local-a:
+	echo "Starting SKY130 PDK migration on "`date` > ${SKY130A}_migrate.log
+	${INSTALL} -source ${STAGING_PATH}/${SKY130A} \
+		-target ${LOCAL_PATH}/${SKY130A} \
+		-link_from ${LINK_TARGETS} |& tee -a ${SKY130A}_migrate.log
+	echo "Ended SKY130 PDK migration on "`date` >> ${SKY130A}_migrate.log
+
+install-dist: install-dist-a
+
+install-dist-a:
+	echo "Starting SKY130 PDK migration on "`date` > ${SKY130A}_migrate.log
+	${INSTALL} -source ${STAGING_PATH}/${SKY130A} \
+		-target ${DIST_PATH}/${SKY130A} \
+		-local ${LOCAL_PATH}/${SKY130A} \
+		-link_from ${DIST_LINK_TARGETS} |& tee -a ${SKY130A}_migrate.log
+	echo "Ended SKY130 PDK migration on "`date` >> ${SKY130A}_migrate.log
+
+clean: clean-a
+
+clean-a:
+	${STAGE} -target ${STAGING_PATH}/${SKY130A} -clean
+
+veryclean: veryclean-a
+
+veryclean-a: clean-a
+	${RM} ${SKY130A}_install.log
+	${RM} ${SKY130A}_migrate.log
diff --git a/sky130/README b/sky130/README
new file mode 100644
index 0000000..00b9851
--- /dev/null
+++ b/sky130/README
@@ -0,0 +1,180 @@
+------------------------------------
+open_pdks
+----------------------------------------
+Master PDK generator for SkyWater Sky130
+Hybrid 180nm / 130nm foundry process
+for open source EDA tools
+----------------------------------------
+
+-------------------------------------------------------------------------------
+Prerequisites:
+
+1. Foundry source files:
+
+    Obtain sources for the SkyWater sky130 130nm process from the git repository at
+    the following location:
+
+	 https://github.com/google/skywater-pdk
+
+    This repository may go in any convenient location.  The Makefile suggests
+    the target location ~/projects/foundry/skywater-pdk but any location will
+    do as long as the definition for CYPRESS_PATH in the Makefile is set
+    appropriately.
+
+    So cd to the target location parent directory (e.g., "cd ~/projects/foundry")
+    and run the following command:
+
+	 git clone https://github.com/google/skywater-pdk
+
+    Then follow the instructions below.
+
+2. EDA tools:
+
+    For installing files to use with the Magic layout tool, Magic must be installed.
+    Obtain Magic from:
+
+	https://github.com/RTimothyEdwards/magic
+
+-------------------------------------------------------------------------------
+Installation:
+
+    There are two methods for installation:  Local and Distribution.  Use Local
+    installation if you are installing on a single host computer.  Use Distribution
+    installation if you are installing into a respository (such as git) that will
+    be distributed to multiple hosts.
+
+Step 1:
+
+    Edit the Makefile to set the following definitions for your host system:
+
+	EF_STYLE = Select "1" for an efabless-style file structure, "0"
+			otherwise.  There are only minor differences in
+			these two styles, namely for version tracking of
+			the Magic setup files, and the location of the
+			technology LEF file.
+
+	LINK_TARGETS = "none" or "source".  "none" copies files from the source
+			directories to the target.  "source" makes symbolic links
+			to the source directories.  Use "source" only if doing
+			a local install, and the source foundry data will not
+			be deleted.  For distribution installations, LINK_TARGETS
+			must be set to "none".
+
+	LOCAL_PATH = The path to the target install directory.  This is used
+			in both the local and distribution installations.  For
+			a distribution installation, this is the local name of
+			the path to the PDK after it has been distributed to
+			the host computers.
+
+	DIST_PATH = The path to the location of the installed files prior to
+			distribution.  This will most likely be a git or similar
+			repo.
+
+Step 2:
+	Run:
+
+	    make
+
+	This will pre-process the setup files to create the PDK-specific files
+	for the SKY130A PDK, and process all vendor files, and place everything
+	in a local staging area.
+
+Step 3:
+	For a local install, do:
+
+	    make install-local
+
+	This copies all files from the staging area into the destination
+	as specified by the variable LOCAL_PATH in the Makefile.  All
+	pointers to absolute paths in the files are changed to match
+	LOCAL_PATH.
+
+	For a distribution install, do:
+
+	    make install-dist
+
+	This copies all files from the staging area into the destination
+	as specified by the variable DIST_PATH in the Makefile.  All
+	pointers to absolute paths in the files are changed to match
+	LOCAL_PATH.  The assumption is that DIST_PATH is a repository
+	(such as a git repo) that is cloned to multiple hosts, and
+	the destination on the hosts where it is distributed is
+	LOCAL_PATH.
+
+-------------------------------------------------------------------------------
+Summary:
+
+    The Makefile script takes the source files and generates files for local
+    PDK names "SKY130A", "SKY130B", etc.  (Note there is currently only one
+    PDK variant "A".)
+
+    The definition of each PDK is made in the Makefile using defines; e.g.,
+	-DMETAL5, etc.
+
+    The make script makes use of the python script "preproc.py" (in the ../common
+    directory) to parse each source file for "#ifdef ..."-type macros.  The syntax
+    is similar to that used by the C preprocessor (cpp) but does not assume C
+    language syntax in the input file, so is generally better to use than cpp
+    (has less unexpected/unintentional behavior).  See comments in the preproc.py
+    script for a full list of macros that it accepts (short list: #ifdef, #ifndef,
+    #define, #include, and boolean operators ||, &&, and !). 
+
+    Files generated:
+	.tech		techfile for magic (full DRC, extract, GDS)
+	-GDS.tech	techfile for magic, vendor mask layers
+	.tcl		PDK script for magic
+	-BindKeys	key binding script for magic partly matching Cadence defaults
+	.magicrc	magic startup script (copy to local directory as .magicrc)
+	_setup.tcl	netgen setup script for LVS
+	.sh		qflow master setup script, standard 1.8V digital
+	.par		graywolf setup file, standard 1.8V digital
+
+    The installation directory below LOCAL_PATH is the name of the PDK;  e.g.,
+
+	    sky130A/		5-metal stack with MiM cap and redistribution layer
+
+    The installation directory hierarchy below the PDK name looks like the following:
+
+		libs.tech/		technology and setup files
+
+		    magic/		magic techfiles, startup file, PDK script,
+					and key binding script.
+		    netgen/		netgen setup file
+		    qflow/		qflow scripts and graywolf setup files.
+		    klayout/		setup files for klayout
+		    openlane/		setup files for openlane
+
+		libs.ref/		foundry data
+
+		    cdl/		CDL netlists
+		    doc/		Foundry documentation
+		    gds/		GDS files
+		    lef/		LEF macro files
+		    lib/		Timing files
+		    mag/		Magic files derived from GDS
+		    maglef/		Magic files derived from LEF macros
+		    spice/		SPICE netlists (ngspice compatible)
+		    techlef/		LEF technology files
+		    verilog/		verilog modules
+
+    Each subdirectory of libs.ref is further divided into sections based on the
+    IP type.  The section names are largely foundry-dependent.  For SkyWater Sky130,
+    these sections include one or more of:
+
+			sky130_fd_sc_hd/		1.8V digital logic (high density)
+			sky130_fd_sc_hdll/		1.8V digital logic (high density low leakage)
+			sky130_fd_sc_hs/		1.8V digital logic (low power)
+			sky130_fd_sc_hvl/		1.8V digital logic (low speed)
+			sky130_fd_sc_lp/		1.8V digital logic (medium speed)
+			sky130_fd_sc_ls/		1.8V digital logic (high speed)
+			sky130_fd_sc_ms/		3.3V digital logic
+
+			sky130_fd_io/			Standard I/O
+
+			sky130_fd_pr_base/		Primitive devices w/fixed layout
+			sky130_fd_pr_rf/		RF primitive devices w/fixed layout
+			sky130_fd_pr_rf2/		Additional RF primitive devices w/fixed layout
+
+    The target installation destinations assume the directory structure above.  Changing
+    this requires editing the source files.
+
diff --git a/sky130/common_pdn.tcl b/sky130/common_pdn.tcl
new file mode 100644
index 0000000..9ad2264
--- /dev/null
+++ b/sky130/common_pdn.tcl
@@ -0,0 +1,44 @@
+# Power nets
+set ::power_nets "VDD"
+set ::ground_nets "VSS"
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_WIDTH) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
+    power_pins "VDDE"
+    ground_pins "VSSE"
+    blockages "li1 met1 met2 met3 met4 met5" 
+    straps { 
+    } 
+    connect { }
+}
+
+set ::halo 0
+
+# Metal layer for rails on every row
+set ::rails_mlayer "met1" ;
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+
+proc generate_viarules {} {
+}
+
+cd $::env(TMP_DIR)/floorplan
+
diff --git a/sky130/common_tracks.info b/sky130/common_tracks.info
new file mode 100644
index 0000000..948dbd2
--- /dev/null
+++ b/sky130/common_tracks.info
@@ -0,0 +1,12 @@
+li1 X 0.23 0.46
+li1 Y 0.17 0.34
+met1 X 0.17 0.34
+met1 Y 0.17 0.34
+met2 X 0.23 0.46
+met2 Y 0.23 0.46
+met3 X 0.34 0.68
+met3 Y 0.34 0.68
+met4 X 0.46 0.92
+met4 Y 0.46 0.92
+met5 X 1.70 3.40
+met5 Y 1.70 3.40
diff --git a/sky130/config.tcl b/sky130/config.tcl
new file mode 100644
index 0000000..d34b05f
--- /dev/null
+++ b/sky130/config.tcl
@@ -0,0 +1,31 @@
+# Process node
+set ::env(PROCESS) 130
+set ::env(DEF_UNITS_PER_MICRON) 1000
+
+
+# Placement site for core cells
+# This can be found in the technology lef
+set ::env(PLACE_SITE) "unithd"
+set ::env(PLACE_SITE_WIDTH) 0.460
+set ::env(PLACE_SITE_HEIGHT) 2.720
+
+set ::env(VDD_PIN) "vpwr"
+set ::env(GND_PIN) "vgnd"
+
+# Track information for generating DEF tracks
+set ::env(TRACKS_INFO_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/common_tracks.info"
+
+
+# Technology LEF
+set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/techLEF/$::env(PDK_VARIANT)/$::env(PDK_VARIANT)_tech.lef"
+set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lef/$::env(PDK_VARIANT)/*.lef"]
+set ::env(MAGIC_TECH_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/current/EFS8A.tech"
+set ::env(MAGIC_MAGICRC) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/current/EFS8A.magicrc"
+set ::env(GPIO_PADS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lef/s8iom0s8/routing_abstract/*.lef"]
+
+# netgen setup
+set ::env(NETGEN_SETUP_FILE) $::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/$::env(PDK)_setup.tcl 
+# CTS luts
+set ::env(CTS_TECH_DIR) "N/A"
+
+set ::env(FP_TAPCELL_DIST) 20
diff --git a/sky130/custom/models/sky130.lib b/sky130/custom/models/sky130.lib
new file mode 100644
index 0000000..04c51ed
--- /dev/null
+++ b/sky130/custom/models/sky130.lib
@@ -0,0 +1,170 @@
+******* SkyWater s8 model library *********
+* Typical corner (tt)
+.lib tt
+* MOSFET
+.inc "./sky130_fd_pr_base__nshort_tt.cor"
+.inc "./sky130_fd_pr_base__nlowvt_tt.cor"
+.inc "./sky130_fd_pr_base__pshort_tt.cor"
+.inc "./sky130_fd_pr_base__ntvnative_tt.cor"
+.inc "./sky130_fd_pr_base__nhvnative_tt.cor"
+.inc "./sky130_fd_pr_base__nshortesd_tt.cor"
+.inc "./sky130_fd_pr_base__plowvt_tt.cor"
+.inc "./sky130_fd_pr_base__phighvt_tt.cor"
+.inc "./sky130_fd_pr_base__phvesd_tt.cor"
+.inc "./sky130_fd_pr_base__phv_tt.cor"
+.inc "./sky130_fd_pr_base__pvhv_tt.cor"
+.inc "./sky130_fd_pr_base__nhv_tt.cor"
+.inc "./sky130_fd_pr_base__nvhv_tt_discrete.cor"
+.inc "./sky130_fd_pr_base__nhvesd_tt.cor"
+.inc "./sky130_fd_pr_base__tt_nonfet.cor"
+* Mismatch parameters
+.inc "./sky130_fd_pr_base__nshort_mm.cor"
+.inc "./sky130_fd_pr_base__pshort_mm.cor"
+.inc "./sky130_fd_pr_base__nlowvt_mm.cor"
+.inc "./sky130_fd_pr_base__plowvt_mm.cor"
+.inc "./sky130_fd_pr_base__phighvt_mm.cor"
+.inc "./sky130_fd_pr_base__nhv_mm.cor"
+.inc "./sky130_fd_pr_base__phv_mm.cor"
+.inc "./sky130_fd_pr_base__nhvnative_mm.cor"
+.inc "./sky130_fd_pr_base__ntvnative_mm.cor"
+* All models
+.inc "models.all"
+* Corner
+.include "ttrf.cor"
+.endl
+
+* Slow-Fast corner (sf)
+.lib sf
+* MOSFET
+.inc "./sky130_fd_pr_base__nshort_sf.cor"
+.inc "./sky130_fd_pr_base__nlowvt_sf.cor"
+.inc "./sky130_fd_pr_base__pshort_sf.cor"
+.inc "./sky130_fd_pr_base__ntvnative_sf.cor"
+.inc "./sky130_fd_pr_base__nhvnative_sf.cor"
+.inc "./sky130_fd_pr_base__nshortesd_sf.cor"
+.inc "./sky130_fd_pr_base__plowvt_sf.cor"
+.inc "./sky130_fd_pr_base__phighvt_sf.cor"
+.inc "./sky130_fd_pr_base__phvesd_sf.cor"
+.inc "./sky130_fd_pr_base__phv_sf.cor"
+.inc "./sky130_fd_pr_base__pvhv_sf.cor"
+.inc "./sky130_fd_pr_base__nhv_sf.cor"
+.inc "./sky130_fd_pr_base__nvhv_sf_discrete.cor"
+.inc "./sky130_fd_pr_base__nhvesd_sf.cor"
+.inc "./sky130_fd_pr_base__sf_nonfet.cor"
+* Mismatch parameters
+.inc "./sky130_fd_pr_base__nshort_mm.cor"
+.inc "./sky130_fd_pr_base__pshort_mm.cor"
+.inc "./sky130_fd_pr_base__nlowvt_mm.cor"
+.inc "./sky130_fd_pr_base__plowvt_mm.cor"
+.inc "./sky130_fd_pr_base__phighvt_mm.cor"
+.inc "./sky130_fd_pr_base__nhv_mm.cor"
+.inc "./sky130_fd_pr_base__phv_mm.cor"
+.inc "./sky130_fd_pr_base__nhvnative_mm.cor"
+.inc "./sky130_fd_pr_base__ntvnative_mm.cor"
+* All models
+.inc "models.all"
+* Corner
+.include "sfrf.cor"
+.endl
+
+* Fast-Fast corner (ff)
+.lib ff
+* MOSFET
+.inc "./sky130_fd_pr_base__nshort_ff.cor"
+.inc "./sky130_fd_pr_base__nlowvt_ff.cor"
+.inc "./sky130_fd_pr_base__pshort_ff.cor"
+.inc "./sky130_fd_pr_base__ntvnative_ff.cor"
+.inc "./sky130_fd_pr_base__nhvnative_ff.cor"
+.inc "./sky130_fd_pr_base__nshortesd_ff.cor"
+.inc "./sky130_fd_pr_base__plowvt_ff.cor"
+.inc "./sky130_fd_pr_base__phighvt_ff.cor"
+.inc "./sky130_fd_pr_base__phvesd_ff.cor"
+.inc "./sky130_fd_pr_base__phv_ff.cor"
+.inc "./sky130_fd_pr_base__pvhv_ff.cor"
+.inc "./sky130_fd_pr_base__nhv_ff.cor"
+.inc "./sky130_fd_pr_base__nvhv_ff_discrete.cor"
+.inc "./sky130_fd_pr_base__nhvesd_ff.cor"
+.inc "./sky130_fd_pr_base__ff_nonfet.cor"
+* Mismatch parameters
+.inc "./sky130_fd_pr_base__nshort_mm.cor"
+.inc "./sky130_fd_pr_base__pshort_mm.cor"
+.inc "./sky130_fd_pr_base__nlowvt_mm.cor"
+.inc "./sky130_fd_pr_base__plowvt_mm.cor"
+.inc "./sky130_fd_pr_base__phighvt_mm.cor"
+.inc "./sky130_fd_pr_base__nhv_mm.cor"
+.inc "./sky130_fd_pr_base__phv_mm.cor"
+.inc "./sky130_fd_pr_base__nhvnative_mm.cor"
+.inc "./sky130_fd_pr_base__ntvnative_mm.cor"
+* All models
+.inc "models.all"
+* Corner
+.include "ffrf.cor"
+.endl
+
+* Slow-Slow corner (ss)
+.lib ss
+* MOSFET
+.inc "./sky130_fd_pr_base__nshort_ss.cor"
+.inc "./sky130_fd_pr_base__nlowvt_ss.cor"
+.inc "./sky130_fd_pr_base__pshort_ss.cor"
+.inc "./sky130_fd_pr_base__ntvnative_ss.cor"
+.inc "./sky130_fd_pr_base__nhvnative_ss.cor"
+.inc "./sky130_fd_pr_base__nshortesd_ss.cor"
+.inc "./sky130_fd_pr_base__plowvt_ss.cor"
+.inc "./sky130_fd_pr_base__phighvt_ss.cor"
+.inc "./sky130_fd_pr_base__phvesd_ss.cor"
+.inc "./sky130_fd_pr_base__phv_ss.cor"
+.inc "./sky130_fd_pr_base__pvhv_ss.cor"
+.inc "./sky130_fd_pr_base__nhv_ss.cor"
+.inc "./sky130_fd_pr_base__nvhv_ss_discrete.cor"
+.inc "./sky130_fd_pr_base__nhvesd_ss.cor"
+.inc "./sky130_fd_pr_base__ss_nonfet.cor"
+* Mismatch parameters
+.inc "./sky130_fd_pr_base__nshort_mm.cor"
+.inc "./sky130_fd_pr_base__pshort_mm.cor"
+.inc "./sky130_fd_pr_base__nlowvt_mm.cor"
+.inc "./sky130_fd_pr_base__plowvt_mm.cor"
+.inc "./sky130_fd_pr_base__phighvt_mm.cor"
+.inc "./sky130_fd_pr_base__nhv_mm.cor"
+.inc "./sky130_fd_pr_base__phv_mm.cor"
+.inc "./sky130_fd_pr_base__nhvnative_mm.cor"
+.inc "./sky130_fd_pr_base__ntvnative_mm.cor"
+* All models
+.inc "models.all"
+* Corner
+.include "ssrf.cor"
+.endl
+
+* Fast-Slow corner (fs)
+.lib fs
+* MOSFET
+.inc "./sky130_fd_pr_base__nshort_fs.cor"
+.inc "./sky130_fd_pr_base__nlowvt_fs.cor"
+.inc "./sky130_fd_pr_base__pshort_fs.cor"
+.inc "./sky130_fd_pr_base__ntvnative_fs.cor"
+.inc "./sky130_fd_pr_base__nhvnative_fs.cor"
+.inc "./sky130_fd_pr_base__nshortesd_fs.cor"
+.inc "./sky130_fd_pr_base__plowvt_fs.cor"
+.inc "./sky130_fd_pr_base__phighvt_fs.cor"
+.inc "./sky130_fd_pr_base__phvesd_fs.cor"
+.inc "./sky130_fd_pr_base__phv_fs.cor"
+.inc "./sky130_fd_pr_base__pvhv_fs.cor"
+.inc "./sky130_fd_pr_base__nhv_fs.cor"
+.inc "./sky130_fd_pr_base__nvhv_fs_discrete.cor"
+.inc "./sky130_fd_pr_base__nhvesd_fs.cor"
+.inc "./sky130_fd_pr_base__fs_nonfet.cor"
+* Mismatch parameters
+.inc "./sky130_fd_pr_base__nshort_mm.cor"
+.inc "./sky130_fd_pr_base__pshort_mm.cor"
+.inc "./sky130_fd_pr_base__nlowvt_mm.cor"
+.inc "./sky130_fd_pr_base__plowvt_mm.cor"
+.inc "./sky130_fd_pr_base__phighvt_mm.cor"
+.inc "./sky130_fd_pr_base__nhv_mm.cor"
+.inc "./sky130_fd_pr_base__phv_mm.cor"
+.inc "./sky130_fd_pr_base__nhvnative_mm.cor"
+.inc "./sky130_fd_pr_base__ntvnative_mm.cor"
+* All models
+.inc "models.all"
+* Corner
+.include "fsrf.cor"
+.endl
diff --git a/sky130/custom/scripts/fixspice.py b/sky130/custom/scripts/fixspice.py
new file mode 100755
index 0000000..92cca88
--- /dev/null
+++ b/sky130/custom/scripts/fixspice.py
@@ -0,0 +1,96 @@
+#!/bin/env python3
+#
+# fixspice ---
+#
+# This script fixes problems in the SkyWater SPICE models.  This should be
+# made obsolete by the forthcoming set of models from the foundry, but the
+# script will get the original set working with ngspice.
+#
+# This script is a filter to be run by setting the name of this script as
+# the value to "filter=" for the model install in the s8 Makefile.
+
+import re
+import os
+import sys
+
+def filter(inname, outname):
+
+    # Read input
+    try:
+        with open(inname, 'r') as inFile:
+            spitext = inFile.read()
+            # (Don't) unwrap continuation lines
+            # spilines = spitext.replace('\n+', ' ').splitlines()
+            spilines = spitext.splitlines()
+    except:
+        print('fixspice.py: failed to open ' + fnmIn + ' for reading.', file=sys.stderr)
+        return 1
+
+    # Process input with regexp
+
+    fixedlines = []
+    modified = False
+
+    for line in spilines:
+
+        # Fix 1:  ngspice does not understand the syntax used for the dev/gauss lines,
+        #  so remove them.
+        fixedline = re.sub('dev/gauss[ \t]*=.*$', '', line)
+
+        # Fix 2: Remove references to *_dlc_rotweak
+        # fixedline = re.sub('\+[ \t]*[^ \t_]+_dlc_rotweak', '', fixedline)
+
+        # Fix 2: Remove references to *_[a,p]junction_mult
+        # fixedline = re.sub('\*[ \t]*[^ \t_]+_[ap]junction_mult', '', fixedline)
+
+        fixedlines.append(fixedline)
+        if fixedline != line:
+            modified = True
+
+    # Write output
+    if outname == None:
+        for i in fixedlines:
+            print(i)
+    else:
+        # If the output is a symbolic link but no modifications have been made,
+        # then leave it alone.  If it was modified, then remove the symbolic
+        # link before writing.
+        if os.path.islink(outname):
+            if not modified:
+                return 0
+            else:
+                os.unlink(outname)
+        try:
+            with open(outname, 'w') as outFile:
+                for i in fixedlines:
+                    print(i, file=outFile)
+        except:
+            print('fixspice.py: failed to open ' + outname + ' for writing.', file=sys.stderr)
+            return 1
+
+
+if __name__ == '__main__':
+
+    # This script expects to get one or two arguments.  One argument is
+    # mandatory and is the input file.  The other argument is optional and
+    # is the output file.  The output file and input file may be the same
+    # name, in which case the original input is overwritten.
+
+    options = []
+    arguments = []
+    for item in sys.argv[1:]:
+        if item.find('-', 0) == 0:
+            options.append(item[1:])
+        else:
+            arguments.append(item)
+
+    if len(arguments) > 0:
+        infilename = arguments[0]
+
+    if len(arguments) > 1:
+        outfilename = arguments[1]
+    else:
+        outfilename = None
+
+    result = filter(infilename, outfilename)
+    sys.exit(result)
diff --git a/sky130/custom/scripts/seal_ring_generator/.magicrc b/sky130/custom/scripts/seal_ring_generator/.magicrc
new file mode 100644
index 0000000..2a18665
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/.magicrc
@@ -0,0 +1,3 @@
+scalegrid 1 10
+tech load s8seal_ring.tech
+drc off
diff --git a/sky130/custom/scripts/seal_ring_generator/README b/sky130/custom/scripts/seal_ring_generator/README
new file mode 100644
index 0000000..af48894
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/README
@@ -0,0 +1,37 @@
+# This directory contains a seal ring generator for SkyWater s8 using magic.
+# Because the seal ring contains many layers that do not appear in standard
+# layout editing, they are all specially implemented in the s8seal_ring.tech
+# file in this directory.
+#
+# An example seal ring was generated by SkyWater and imported using magic's
+# gdsquery.sh script.  It was then hand-edited to contain only the bottom
+# quarter.  Then it was saved in .mag databases.
+#
+# The generator script s8_gen_sealring.py calls magic using the s8seal_ring.tech
+# file, and automatically modifies the geometry to stretch to the half width
+# and height of the specified dimensions.  Then the lower-left cells are
+# copied and folded over the centerline to make the complete seal ring.
+# The seal ring is then written out in GDS format.  Then a simplified magic
+# view is generated in the usual user-facing s8 technology file, with the
+# GDS_FILE property pointing to the seal ring GDS.  This layout and GDS can
+# then be imported into a layout.
+#
+# Usage:
+#
+#   s8_gen_sealring.py width height target_dir [-force] [-outer]
+#
+# Where:
+#   width = the full-chip layout width
+#   height = the full-chip layout height
+#   target_dir = location of the full-chip layout
+#
+#   -force = overwrite existing files in the target directory
+#   -outer = width and height represent the seal ring outer edge, not the chip area
+#
+# Results:
+#   Files advSeal_6u_gen.mag and advSeal_6um_gen.gds are generated and placed in
+#   target_dir.  advSeal_6u_gen.mag is an "abstract" view that represents the
+#   seal ring in diffusion and the nikon cross in metal1, and references
+#   the advSeal_6um_gen.gds file in the same directory as a GDS_FILE property.
+#
+
diff --git a/sky130/custom/scripts/seal_ring_generator/generate_gds.tcl b/sky130/custom/scripts/seal_ring_generator/generate_gds.tcl
new file mode 100644
index 0000000..9aedf7b
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/generate_gds.tcl
@@ -0,0 +1,10 @@
+# Tcl script input to magic to generate seal ring GDS
+tech load s8seal_ring -noprompt
+drc off
+load advSeal_6um_gen
+select top cell
+expand
+cif *hier write disable
+cif *array write disable
+gds write advSeal_6um_gen
+quit
diff --git a/sky130/custom/scripts/seal_ring_generator/nikon_sealring_shape.mag b/sky130/custom/scripts/seal_ring_generator/nikon_sealring_shape.mag
new file mode 100644
index 0000000..caf7cc9
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/nikon_sealring_shape.mag
@@ -0,0 +1,130 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< checkpaint >>
+rect 0 0 400 400
+<< type21 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type22 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type23 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type27 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type28 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type30 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type32 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type34 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type35 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type36 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type40 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type41 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type43 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type44 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type46 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type50 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type51 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type56 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type58 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type59 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type88 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type96 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type97 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+<< type98 >>
+rect 175 225 225 320
+rect 80 175 320 225
+rect 175 80 225 175
+use sr_polygon00006  sr_polygon00006_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 400 400
+use sr_polygon00005  sr_polygon00005_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 400 400
+use sr_polygon00004  sr_polygon00004_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 400 400
+use sr_polygon00003  sr_polygon00003_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 400 400
+use sr_polygon00002  sr_polygon00002_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 400 400
+use sr_polygon00001  sr_polygon00001_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 400 400
+use sr_polygon00007  sr_polygon00007_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 400 400
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/s8_gen_sealring.py b/sky130/custom/scripts/seal_ring_generator/s8_gen_sealring.py
new file mode 100755
index 0000000..d1c3761
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/s8_gen_sealring.py
@@ -0,0 +1,349 @@
+#!/bin/env python3
+#-------------------------------------------------------------------------
+# s8_gen_sealring.py ---  a seal ring generator for SkyWater s8 using magic.
+#
+# Because the seal ring contains many layers that do not appear in standard
+# layout editing, they are all specially implemented in the s8seal_ring.tech
+# file in this directory.
+#
+# An example seal ring was generated by SkyWater and imported using magic's
+# gdsquery.sh script.  It was then hand-edited to contain only the bottom
+# quarter.  Then it was saved in .mag databases.
+#
+# The generator script s8_gen_sealring.py calls magic using the s8seal_ring.tech
+# file, and automatically modifies the geometry to stretch to the half width
+# and height of the specified dimensions.  Then the lower-left cells are
+# copied and folded over the centerline to make the complete seal ring.
+# The seal ring is then written out in GDS format.  Then a simplified magic
+# view is generated in the usual user-facing s8 technology file, with the
+# GDS_FILE property pointing to the seal ring GDS.  This layout and GDS can
+# then be imported into a layout.
+#
+# Usage:
+#
+#   s8_gen_sealring.py width height target_dir [-force] [-outer] [-keep]
+#
+# Where:
+#   width = the full-chip layout width
+#   height = the full-chip layout height
+#   target_dir = location of the full-chip layout
+#
+#   -force = overwrite any existing files at the target
+#   -outer = width and height are the seal ring outer edge, not the chip area
+#   -keep = keep local working directory of results
+#
+# Results:
+#   Files advSeal_6um_gen.mag and advSeal_6um_gen.gds are generated and placed in
+#   target_dir.  advSeal_6um_gen.mag is an "abstract" view that represents the
+#   seal ring in diffusion and the nikon cross in metal1, and references
+#   the advSeal_6um_gen.gds file in the same directory as a GDS_FILE property.
+#-------------------------------------------------------------------------
+
+import subprocess
+import shutil
+import sys
+import os
+import re
+
+def generate_sealring(width, height, target_dir, force, keep):
+
+    # All files of interest are listed below.
+
+    script = 'generate_gds.tcl'
+    tech = 's8seal_ring.tech'
+    corner = 'seal_ring_corner.mag'
+    abstract = 'seal_ring_corner_abstract.mag'
+    slots = 'sealring_slots.mag'
+    array = 'seal_ring_slots_array.mag'
+    nikon = 'nikon_sealring_shape.mag'
+    polygons = ['sr_polygon00007.mag',
+	    'sr_polygon00027.mag', 'sr_polygon00011.mag', 'sr_polygon00028.mag',
+	    'sr_polygon00001.mag', 'sr_polygon00015.mag', 'sr_polygon00031.mag',
+	    'sr_polygon00002.mag', 'sr_polygon00016.mag', 'sr_polygon00032.mag',
+	    'sr_polygon00003.mag', 'sr_polygon00019.mag', 'sr_polygon00035.mag',
+	    'sr_polygon00004.mag', 'sr_polygon00020.mag', 'sr_polygon00036.mag',
+	    'sr_polygon00005.mag', 'sr_polygon00023.mag', 'sr_polygon00039.mag',
+	    'sr_polygon00006.mag', 'sr_polygon00024.mag']
+
+
+    # Create temporary directory
+    if os.path.exists('temp'):
+        print('temp/ directory exists.  Please remove it before running.')
+        sys.exit(0)
+
+    os.makedirs('temp')
+    os.chdir('temp')
+
+    # Copy all .mag files, .magicrc file, and s8seal_ring.tech file to temp/
+    files_to_copy = polygons[:]
+    files_to_copy.append(nikon)
+    files_to_copy.append(slots)
+    files_to_copy.append(array)
+    files_to_copy.append(corner)
+    files_to_copy.append(abstract)
+    files_to_copy.append(tech)
+    files_to_copy.append(script)
+
+    for file in files_to_copy:
+        shutil.copy('../' + file, '.')
+
+    # Seal ring is placed 6um outside of the chip, so add 12um to width and height
+    fwidth = float(width) + 12
+    fheight = float(height) + 12
+
+    dbhwidth = int(fwidth * 100)
+    dbhheight = int(fheight * 100)
+
+    swidth = str(dbhwidth)
+    sheight = str(dbhheight)
+
+    swidthx5 = str(dbhwidth * 5)
+
+    dwidth = str(int(fwidth * 200))
+    dheight = str(int(fheight * 200))
+
+    # Modify every polygon to half width and height
+
+    for file in polygons:
+        with open(file, 'r') as ifile:
+            maglines = ifile.read().splitlines()
+
+        with open(file, 'w') as ofile:
+            for line in maglines:
+                newline = re.sub('51200', swidth, line)
+                newline = re.sub('51210', sheight, newline)
+                # NOTE: polygon 39 is at scale 10, not 2, due to
+                # corner positions of 45 degree angled geometry.
+                newline = re.sub('256000', swidthx5, newline)
+                print(newline, file=ofile)
+
+    # Abstract corner view gets the same treatment
+
+    qwidth = str(int(fwidth * 50))
+    qheight = str(int(fheight * 50))
+
+    with open(abstract, 'r') as ifile:
+        maglines = ifile.read().splitlines()
+
+    with open(abstract, 'w') as ofile:
+        for line in maglines:
+            newline = re.sub('25600', qwidth, line)
+            newline = re.sub('25605', qheight, newline)
+            print(newline, file=ofile)
+
+    # Slots arrays are recalculated to span the width and height
+
+    with open(array, 'r') as ifile:
+        maglines = ifile.read().splitlines()
+
+    slotsX = False
+    with open(array, 'w') as ofile:
+        for line in maglines:
+            newline = line
+            if 'slots_X' in line:
+                slotsX = True
+            elif 'array 0' in line:
+                if slotsX:
+                    nslots = int((fwidth - 25.0) / 25.0) - 1
+                    newline = 'array 0 ' + str(nslots) + ' 5000 0 0 430'
+                else:
+                    nslots = int((fheight - 25.0) / 25.0) - 1
+                    newline = 'array 0 ' + str(nslots) + ' 5000 0 0 430'
+
+            print(newline, file=ofile)
+
+    # Corner cell changes bounding boxes to half width and height.
+
+    with open(corner, 'r') as ifile:
+        maglines = ifile.read().splitlines()
+
+    slotsX = False
+    with open(corner, 'w') as ofile:
+        for line in maglines:
+            newline = re.sub('51200', swidth, line)
+            newline = re.sub('51210', sheight, newline)
+            print(newline, file=ofile)
+
+    # Create a new top-level layout called 'advSeal_6um_gen.mag'
+    # Mirrors uses in X and Y, and adds slots arrays at lower left
+    # and upper right
+
+    with open('advSeal_6um_gen.mag', 'w') as ofile:
+        print('magic', file=ofile)
+        print('tech s8seal_ring', file=ofile)
+        print('magscale 1 2', file=ofile)
+        print('timestamp 1584630000', file=ofile)
+
+        # Lower left original
+        print('use seal_ring_corner seal_ring_corner_0', file=ofile)
+        print('timestamp 1584562315', file=ofile)
+        print('transform 1 0 0 0 1 0', file=ofile)
+        print('box -30480 -30480 ' + swidth + ' ' + sheight, file=ofile)
+
+        # Mirrored in X
+        print('use seal_ring_corner seal_ring_corner_3', file=ofile)
+        print('timestamp 1584562315', file=ofile)
+        print('transform -1 0 ' + dwidth + ' 0 1 0', file=ofile)
+        print('box -30480 -30480 ' + swidth + ' ' + sheight, file=ofile)
+	
+        # Mirrored in Y
+        print('use seal_ring_corner seal_ring_corner_1', file=ofile)
+        print('timestamp 1584562315', file=ofile)
+        print('transform 1 0 0 0 -1 ' + dheight, file=ofile)
+        print('box -30480 -30480 ' + swidth + ' ' + sheight, file=ofile)
+
+        # Mirrored in both X and Y 
+        print('use seal_ring_corner seal_ring_corner_2', file=ofile)
+        print('timestamp 1584562315', file=ofile)
+        print('transform -1 0 ' + dwidth + ' 0 -1 ' + dheight, file=ofile)
+        print('box -30480 -30480 ' + swidth + ' ' + sheight, file=ofile)
+
+        # Lower left slot arrays (bottom and left sides slots)
+        print('use seal_ring_slots_array seal_ring_slots_array_0', file=ofile)
+        print('timestamp 1584629764', file=ofile)
+        print('transform 1 0 0 0 1 0', file=ofile)
+        print('box 285 285 ' + swidth + ' ' + sheight, file=ofile)
+
+        # Upper right slot arrays (top and right sides slots)
+        print('use seal_ring_slots_array seal_ring_slots_array_1', file=ofile)
+        print('timestamp 1584629764', file=ofile)
+        print('transform -1 0 ' + dwidth + ' 0 -1 ' + dheight, file=ofile)
+        print('box 285 285 ' + swidth + ' ' + sheight, file=ofile)
+
+        print('<< end >>', file=ofile)
+    
+    # Create a new abstract layout TO BE called 'advSeal_6um_gen.mag'
+    # This is the view in technology EFS8A.  Since there is already
+    # a cell with this name that is used to generate GDS, the cell
+    # will be called "seal_ring.mag" and copied to "advSeal_6um_gen.mag"
+    # in the target directory.
+
+    xwidth = str(dbhwidth)
+    xheight = str(dbhheight)
+
+    with open('seal_ring.mag', 'w') as ofile:
+        print('magic', file=ofile)
+        print('tech EFS8A', file=ofile)
+        print('timestamp 1584566829', file=ofile)
+
+        # Lower left original
+        print('use seal_ring_corner_abstract seal_ring_corner_abstract_0', file=ofile)
+        print('timestamp 1584566221', file=ofile)
+        print('transform 1 0 0 0 1 0', file=ofile)
+        print('box 0 0 ' + qwidth + ' ' + qheight, file=ofile)
+
+        # Mirrored in X
+        print('use seal_ring_corner_abstract seal_ring_corner_abstract_3', file=ofile)
+        print('timestamp 1584566221', file=ofile)
+        print('transform -1 0 ' + xwidth + ' 0 1 0', file=ofile)
+        print('box 0 0 ' + qwidth + ' ' + qheight, file=ofile)
+	
+        # Mirrored in Y
+        print('use seal_ring_corner_abstract seal_ring_corner_abstract_1', file=ofile)
+        print('timestamp 1584566221', file=ofile)
+        print('transform 1 0 0 0 -1 ' + xheight, file=ofile)
+        print('box 0 0 ' + qwidth + ' ' + qheight, file=ofile)
+
+        # Mirrored in both X and Y 
+        print('use seal_ring_corner_abstract seal_ring_corner_abstract_2', file=ofile)
+        print('timestamp 1584566221', file=ofile)
+        print('transform -1 0 ' + xwidth + ' 0 -1 ' + xheight, file=ofile)
+        print('box 0 0 ' + qwidth + ' ' + qheight, file=ofile)
+
+        print('<< properties >>', file=ofile)
+        print('string LEFview no_prefix', file=ofile)
+        print('string GDS_FILE advSeal_6um_gen.gds', file=ofile)
+        print('string GDS_START 0', file=ofile)
+        print('string FIXED_BBOX 0 0 ' + swidth + ' ' + sheight, file=ofile)
+
+        print('<< end >>', file=ofile)
+
+    # Create the GDS of the seal ring
+
+    mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+	    'generate_gds.tcl'],
+	    stdin = subprocess.DEVNULL, stdout = subprocess.PIPE,
+	    stderr = subprocess.PIPE, universal_newlines = True)
+    if mproc.stdout:
+        for line in mproc.stdout.splitlines():
+            print(line)
+    if mproc.stderr:
+        print('Error message output from magic:')
+        for line in mproc.stderr.splitlines():
+            print(line)
+    if mproc.returncode != 0:
+        print('ERROR:  Magic exited with status ' + str(mproc.returncode))
+
+    # Copy the GDS file and the abstract view to the target directory
+
+    os.chdir('..')
+
+    if not os.path.exists(target_dir):
+        os.makedirs(target_dir)
+
+    print('Installing files to ' + target_dir)
+    if force or not os.path.exists(target_dir + '/advSeal_6um_gen.gds'):
+        shutil.copy('temp/advSeal_6um_gen.gds', target_dir)
+    else:
+        print('ERROR: advSeal_6um_gen.gds already exists at target!  Use -force to overwrite.')
+    if force or not os.path.exists(target_dir + '/advSeal_6um_gen.mag'):
+        shutil.copy('temp/seal_ring.mag', target_dir + '/advSeal_6um_gen.mag')
+    else:
+        print('ERROR: advSeal_6um_gen.mag already exists at target!  Use -force to overwrite.')
+    if force or not os.path.exists(target_dir + '/seal_ring_corner_abstract.mag'):
+        shutil.copy('temp/seal_ring_corner_abstract.mag', target_dir)
+    else:
+        print('ERROR: seal_ring_corner_abstract.mag already exists at target!  Use -force to overwrite.')
+    
+    # Remove the temporary directory and its contents
+
+    if not keep:
+        shutil.rmtree('temp')
+    else:
+        print('Retaining generated files in temp/ directory')
+
+    # Done!
+    print('Done generating files advSeal_6um_gen.gds and advSeal_6um_gen.mag in ' + target_dir)
+    print('Place the seal ring cell in the final layout at (0um, 0um) before generating GDS.')
+    print('The top level layout minus seal ring must have a lower left corner of (6um, 6um)')
+
+# If called as main, run generate_sealring()
+
+if __name__ == '__main__':
+
+    # Divide up command line into options and arguments
+    options = []
+    arguments = []
+    for item in sys.argv[1:]:
+        if item.find('-', 0) == 0:
+            options.append(item)
+        else:
+            arguments.append(item)
+
+    force = True if '-force' in options else False
+    keep = True if '-keep' in options else False
+    outer = True if '-outer' in options else False
+
+    # Need one argument:  path to verilog netlist
+    # If two arguments, then 2nd argument is the output file.
+
+    if len(arguments) == 3:
+        width = arguments[0]
+        height = arguments[1]
+        target_dir = arguments[2]
+
+        # Seal ring is 12um thick, so if "outer" option is used, subtract 12um
+        # from both width and height.
+        if outer:
+            width = str(float(width) - 12.0)
+            height = str(float(height) - 12.0)
+
+        generate_sealring(width, height, target_dir, force, keep)
+    else:
+        print("Usage:  s8_gen_sealring.py <width> <height> <target_dir> [options]")
+        print("Options:")
+        print("   -outer : Width and height are seal ring outer edge, not chip area")
+        print("   -force : Overwrite any existing files at <target_dir>")
+        print("   -keep :  Keep generated files in temp/ directory")
+    
+
diff --git a/sky130/custom/scripts/seal_ring_generator/s8seal_ring.tech b/sky130/custom/scripts/seal_ring_generator/s8seal_ring.tech
new file mode 100644
index 0000000..e5d37f3
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/s8seal_ring.tech
@@ -0,0 +1,506 @@
+tech
+   30
+   s8seal_ring
+end
+
+version
+   version 0.0
+   description "Auto-generated techfile for unknown GDS read-in"
+end
+
+planes
+   plane11
+   plane20
+   plane21
+   plane22
+   plane23
+   plane25
+   plane27
+   plane28
+   plane30
+   plane32
+   plane34
+   plane35
+   plane36
+   plane37
+   plane39
+   plane40
+   plane41
+   plane43
+   plane44
+   plane46
+   plane48
+   plane49
+   plane50
+   plane51
+   plane56
+   plane58
+   plane59
+   plane61
+   plane65
+   plane81
+   plane88
+   plane96
+   plane97
+   plane98
+end
+
+types
+   plane11 type11
+   plane20 type20
+   plane21 type21
+   plane22 type22
+   plane22 type22_22
+   plane23 type23
+   plane25 type25
+   plane27 type27
+   plane28 type28
+   plane30 type30
+   plane32 type32
+   plane34 type34
+   plane35 type35
+   plane36 type36
+   plane37 type37
+   plane39 type39
+   plane40 type40
+   plane41 type41
+   plane43 type43
+   plane44 type44
+   plane46 type46
+   plane48 type48
+   plane49 type49
+   plane50 type50
+   plane51 type51
+   plane56 type56
+   plane58 type58
+   plane59 type59
+   plane61 type61_20
+   plane65 type65_20
+   plane81 type81_1
+   plane81 type81_51
+   plane81 type81_52
+   plane88 type88
+   plane96 type96
+   plane97 type97
+   plane98 type98
+end 
+
+contact
+end
+
+styles
+   styletype mos
+   type11 polysilicon
+   type20 ndiffusion
+   type21 pdiffusion
+   type22 capacitor
+   type22_22 metal1
+   type23 metal2
+   type25 metal3
+   type27 metal4
+   type28 metal5
+   type30 metal6
+   type32 metal7
+   type34 metal8
+   type35 metal9
+   type36 implant1
+   type37 implant2
+   type39 implant3
+   type40 implant4
+   type41 ntransistor
+   type43 ptransistor
+   type44 electrode
+   type46 poly_light
+   type48 mvndiff
+   type49 hvndiff
+   type50 ncontact
+   type51 mvpdiff
+   type56 hvpdiff
+   type58 pcontact
+   type59 poly_resist
+   type61_20 metal10
+   type65_20 mems
+   type81_1 cwell
+   type81_51 cwellnsc
+   type81_52 highvolt_nwell
+   type88 highvolt_pwell
+   type96 nwell
+   type97 pwell
+   type98 poly_light
+end
+
+compose
+end
+
+connect
+end
+
+cifoutput
+style generic
+   scalefactor 1
+
+   layer GDS11 type11
+   labels type11
+   calma 11 0
+
+   layer GDS20 type20
+   labels type20
+   calma 20 0
+
+   layer GDS21 type21
+   labels type21
+   calma 21 0
+
+   layer GDS22 type22
+   labels type22
+   calma 22 0
+
+   layer GDS22_22 type22_22
+   labels type22_22
+   calma 22 22
+
+   layer GDS23 type23
+   labels type23
+   calma 23 0
+
+   layer GDS25 type25
+   labels type25
+   calma 25 0
+
+   layer GDS27 type27
+   labels type27
+   calma 27 0
+
+   layer GDS28 type28
+   labels type28
+   calma 28 0
+
+   layer GDS30 type30
+   labels type30
+   calma 30 0
+
+   layer GDS32 type32
+   labels type32
+   calma 32 0
+
+   layer GDS34 type34
+   labels type34
+   calma 34 0
+
+   layer GDS35 type35
+   labels type35
+   calma 35 0
+
+   layer GDS36 type36
+   labels type36
+   calma 36 0
+
+   layer GDS37 type37
+   labels type37
+   calma 37 0
+
+   layer GDS39 type39
+   labels type39
+   calma 39 0
+
+   layer GDS40 type40
+   labels type40
+   calma 40 0
+
+   layer GDS41 type41
+   labels type41
+   calma 41 0
+
+   layer GDS43 type43
+   labels type43
+   calma 43 0
+
+   layer GDS44 type44
+   labels type44
+   calma 44 0
+
+   layer GDS46 type46
+   labels type46
+   calma 46 0
+
+   layer GDS48 type48
+   labels type48
+   calma 48 0
+
+   layer GDS49 type49
+   labels type49
+   calma 49 0
+
+   layer GDS50 type50
+   labels type50
+   calma 50 0
+
+   layer GDS51 type51
+   labels type51
+   calma 51 0
+
+   layer GDS56 type56
+   labels type56
+   calma 56 0
+
+   layer GDS58 type58
+   labels type58
+   calma 58 0
+
+   layer GDS59 type59
+   labels type59
+   calma 59 0
+
+   layer GDS61_20 type61_20
+   labels type61_20
+   calma 61 20
+
+   layer GDS65_20 type65_20
+   labels type65_20
+   calma 65 20
+
+   layer GDS81_1 type81_1
+   labels type81_1
+   calma 81 1
+
+   layer GDS81_51 type81_51
+   labels type81_51
+   calma 81 51
+
+   layer GDS81_52 type81_52
+   labels type81_52
+   calma 81 52
+
+   layer GDS88 type88
+   labels type88
+   calma 88 0
+
+   layer GDS96 type96
+   labels type96
+   calma 96 0
+
+   layer GDS97 type97
+   labels type97
+   calma 97 0
+
+   layer GDS98 type98
+   labels type98
+   calma 98 0
+
+end
+
+cifinput
+style generic
+   scalefactor 1
+
+   layer type11 GDS11
+   labels GDS11
+
+   layer type20 GDS20
+   labels GDS20
+
+   layer type21 GDS21
+   labels GDS21
+
+   layer type22 GDS22
+   labels GDS22
+
+   layer type22_22 GDS22_22
+   labels GDS22_22
+
+   layer type23 GDS23
+   labels GDS23
+
+   layer type25 GDS25
+   labels GDS25
+
+   layer type27 GDS27
+   labels GDS27
+
+   layer type28 GDS28
+   labels GDS28
+
+   layer type30 GDS30
+   labels GDS30
+
+   layer type32 GDS32
+   labels GDS32
+
+   layer type34 GDS34
+   labels GDS34
+
+   layer type35 GDS35
+   labels GDS35
+
+   layer type36 GDS36
+   labels GDS36
+
+   layer type37 GDS37
+   labels GDS37
+
+   layer type39 GDS39
+   labels GDS39
+
+   layer type40 GDS40
+   labels GDS40
+
+   layer type41 GDS41
+   labels GDS41
+
+   layer type43 GDS43
+   labels GDS43
+
+   layer type44 GDS44
+   labels GDS44
+
+   layer type46 GDS46
+   labels GDS46
+
+   layer type48 GDS48
+   labels GDS48
+
+   layer type49 GDS49
+   labels GDS49
+
+   layer type50 GDS50
+   labels GDS50
+
+   layer type51 GDS51
+   labels GDS51
+
+   layer type56 GDS56
+   labels GDS56
+
+   layer type58 GDS58
+   labels GDS58
+
+   layer type59 GDS59
+   labels GDS59
+
+   layer type61_20 GDS61_20
+   labels GDS61_20
+
+   layer type65_20 GDS65_20
+   labels GDS65_20
+
+   layer type81_1 GDS81_1
+   labels GDS81_1
+
+   layer type81_51 GDS81_51
+   labels GDS81_51
+
+   layer type81_52 GDS81_52
+   labels GDS81_52
+
+   layer type88 GDS88
+   labels GDS88
+
+   layer type96 GDS96
+   labels GDS96
+
+   layer type97 GDS97
+   labels GDS97
+
+   layer type98 GDS98
+   labels GDS98
+
+   calma GDS11 11 0
+   calma GDS20 20 0
+   calma GDS21 21 0
+   calma GDS22 22 0
+   calma GDS22_22 22 22
+   calma GDS23 23 0
+   calma GDS25 25 0
+   calma GDS27 27 0
+   calma GDS28 28 0
+   calma GDS30 30 0
+   calma GDS32 32 0
+   calma GDS34 34 0
+   calma GDS35 35 0
+   calma GDS36 36 0
+   calma GDS37 37 0
+   calma GDS39 39 0
+   calma GDS40 40 0
+   calma GDS41 41 0
+   calma GDS43 43 0
+   calma GDS44 44 0
+   calma GDS46 46 0
+   calma GDS48 48 0
+   calma GDS49 49 0
+   calma GDS50 50 0
+   calma GDS51 51 0
+   calma GDS56 56 0
+   calma GDS58 58 0
+   calma GDS59 59 0
+   calma GDS61_20 61 20
+   calma GDS65_20 65 20
+   calma GDS81_1 81 1
+   calma GDS81_51 81 51
+   calma GDS81_52 81 52
+   calma GDS88 88 0
+   calma GDS96 96 0
+   calma GDS97 97 0
+   calma GDS98 98 0
+end
+
+# mzrouter
+# end
+
+drc
+end
+
+extract
+style generic
+   cscale 1
+   lambda 1
+   step 10
+   sidehalo 0
+
+  planeorder plane11 0
+  planeorder plane20 1
+  planeorder plane21 2
+  planeorder plane22 3
+  planeorder plane23 4
+  planeorder plane25 5
+  planeorder plane27 6
+  planeorder plane28 7
+  planeorder plane30 8
+  planeorder plane32 9
+  planeorder plane34 10
+  planeorder plane35 11
+  planeorder plane36 12
+  planeorder plane37 13
+  planeorder plane39 14
+  planeorder plane40 15
+  planeorder plane41 16
+  planeorder plane43 17
+  planeorder plane44 18
+  planeorder plane46 19
+  planeorder plane48 20
+  planeorder plane49 21
+  planeorder plane50 22
+  planeorder plane51 23
+  planeorder plane56 24
+  planeorder plane58 25
+  planeorder plane59 26
+  planeorder plane61 27
+  planeorder plane65 28
+  planeorder plane81 29
+  planeorder plane88 30
+  planeorder plane96 31
+  planeorder plane97 32
+  planeorder plane98 33
+end
+
+# wiring
+# end
+
+# router
+# end
+
+# plowing
+# end
+
+plot
+  style pnm
+end
diff --git a/sky130/custom/scripts/seal_ring_generator/seal_ring_corner.mag b/sky130/custom/scripts/seal_ring_generator/seal_ring_corner.mag
new file mode 100644
index 0000000..e15ffc8
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/seal_ring_corner.mag
@@ -0,0 +1,68 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584562315
+<< type81_52 >>
+rect 0 20320 20320 51210
+rect 0 0 51200 20320
+use sr_polygon00028  sr_polygon00028_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 650 2369 710 51210
+use sr_polygon00024  sr_polygon00024_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 530 2319 590 51210
+use sr_polygon00020  sr_polygon00020_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 410 2269 470 51210
+use sr_polygon00016  sr_polygon00016_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 290 2219 350 51210
+use sr_polygon00032  sr_polygon00032_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 0 2099 1000 51210
+use sr_polygon00031  sr_polygon00031_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 650 650 51200 2394
+use sr_polygon00027  sr_polygon00027_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 530 530 51200 2344
+use sr_polygon00023  sr_polygon00023_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 410 410 51200 2294
+use sr_polygon00019  sr_polygon00019_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 290 290 51200 2244
+use nikon_sealring_shape  nikon_sealring_shape_0
+timestamp 1584558468
+transform 1 0 200 0 1 200
+box 0 0 800 800
+use sr_polygon00036  sr_polygon00036_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 0 0 1200 51210
+use sr_polygon00015  sr_polygon00015_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box 0 0 2099 2099
+use sr_polygon00035  sr_polygon00035_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 0 0 51200 2514
+use sr_polygon00039  sr_polygon00039_0
+timestamp 1584558827
+transform 1 0 0 0 1 0
+box 0 0 51200 2597
+use sr_polygon00011  sr_polygon00011_0
+timestamp 1584558468
+transform 1 0 0 0 1 0
+box -30480 -30480 30480 30480
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/seal_ring_corner_abstract.mag b/sky130/custom/scripts/seal_ring_generator/seal_ring_corner_abstract.mag
new file mode 100644
index 0000000..1477b9c
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/seal_ring_corner_abstract.mag
@@ -0,0 +1,27 @@
+magic
+tech EFS8A
+timestamp 1584566221
+<< psubstratepdiff >>
+rect 145 1110 355 25605
+tri 145 900 355 1110 ne
+tri 355 900 652 1197 sw
+tri 355 652 603 900 ne
+rect 603 652 652 900
+tri 652 652 900 900 sw
+tri 603 355 900 652 ne
+tri 900 355 1197 652 sw
+tri 900 145 1110 355 ne
+rect 1110 145 25600 355
+<< locali >>
+tri 100 383 217 500 se
+rect 217 383 383 500
+tri 383 383 500 500 sw
+rect 100 217 500 383
+tri 100 100 217 217 ne
+rect 217 100 383 217
+tri 383 100 500 217 nw
+<< metal1 >>
+rect 275 325 325 420
+rect 180 275 420 325
+rect 275 180 325 275
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/seal_ring_slots_array.mag b/sky130/custom/scripts/seal_ring_generator/seal_ring_slots_array.mag
new file mode 100644
index 0000000..f38f77c
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/seal_ring_slots_array.mag
@@ -0,0 +1,15 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584629764
+use sealring_slots  sealring_slots_Y
+array 0 7 5000 0 0 430
+timestamp 1584628639
+transform 0 -1 1000 1 0 -7000
+box 9500 285 12200 715
+use sealring_slots  sealring_slots_X
+array 0 7 5000 0 0 430
+timestamp 1584628639
+transform 1 0 -7000 0 1 0
+box 9500 285 12200 715
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sealring_slots.mag b/sky130/custom/scripts/seal_ring_generator/sealring_slots.mag
new file mode 100644
index 0000000..c3ee669
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sealring_slots.mag
@@ -0,0 +1,13 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584628639
+<< checkpaint >>
+rect 6900 285 7100 355
+rect 9500 285 9700 355
+<< type22_22 >>
+rect 12000 645 12200 715
+rect 9500 525 9700 595
+rect 12000 405 12200 475
+rect 9500 285 9700 355
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00001.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00001.mag
new file mode 100644
index 0000000..e7c32b8
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00001.mag
@@ -0,0 +1,21 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< type48 >>
+tri 0 283 117 400 se
+rect 117 320 283 400
+rect 117 283 175 320
+rect 0 225 175 283
+rect 225 283 283 320
+tri 283 283 400 400 sw
+rect 225 225 400 283
+rect 0 175 80 225
+rect 320 175 400 225
+rect 0 117 175 175
+tri 0 0 117 117 ne
+rect 117 80 175 117
+rect 225 117 400 175
+rect 225 80 283 117
+rect 117 0 283 80
+tri 283 0 400 117 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00002.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00002.mag
new file mode 100644
index 0000000..51355fa
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00002.mag
@@ -0,0 +1,21 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< type25 >>
+tri 0 283 117 400 se
+rect 117 320 283 400
+rect 117 283 175 320
+rect 0 225 175 283
+rect 225 283 283 320
+tri 283 283 400 400 sw
+rect 225 225 400 283
+rect 0 175 80 225
+rect 320 175 400 225
+rect 0 117 175 175
+tri 0 0 117 117 ne
+rect 117 80 175 117
+rect 225 117 400 175
+rect 225 80 283 117
+rect 117 0 283 80
+tri 283 0 400 117 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00003.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00003.mag
new file mode 100644
index 0000000..7c2dd29
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00003.mag
@@ -0,0 +1,21 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< type20 >>
+tri 0 283 117 400 se
+rect 117 320 283 400
+rect 117 283 175 320
+rect 0 225 175 283
+rect 225 283 283 320
+tri 283 283 400 400 sw
+rect 225 225 400 283
+rect 0 175 80 225
+rect 320 175 400 225
+rect 0 117 175 175
+tri 0 0 117 117 ne
+rect 117 80 175 117
+rect 225 117 400 175
+rect 225 80 283 117
+rect 117 0 283 80
+tri 283 0 400 117 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00004.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00004.mag
new file mode 100644
index 0000000..7721108
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00004.mag
@@ -0,0 +1,21 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< type39 >>
+tri 0 283 117 400 se
+rect 117 320 283 400
+rect 117 283 175 320
+rect 0 225 175 283
+rect 225 283 283 320
+tri 283 283 400 400 sw
+rect 225 225 400 283
+rect 0 175 80 225
+rect 320 175 400 225
+rect 0 117 175 175
+tri 0 0 117 117 ne
+rect 117 80 175 117
+rect 225 117 400 175
+rect 225 80 283 117
+rect 117 0 283 80
+tri 283 0 400 117 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00005.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00005.mag
new file mode 100644
index 0000000..27e8081
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00005.mag
@@ -0,0 +1,21 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< type11 >>
+tri 0 283 117 400 se
+rect 117 320 283 400
+rect 117 283 175 320
+rect 0 225 175 283
+rect 225 283 283 320
+tri 283 283 400 400 sw
+rect 225 225 400 283
+rect 0 175 80 225
+rect 320 175 400 225
+rect 0 117 175 175
+tri 0 0 117 117 ne
+rect 117 80 175 117
+rect 225 117 400 175
+rect 225 80 283 117
+rect 117 0 283 80
+tri 283 0 400 117 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00006.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00006.mag
new file mode 100644
index 0000000..8b44cb9
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00006.mag
@@ -0,0 +1,21 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< type49 >>
+tri 0 283 117 400 se
+rect 117 320 283 400
+rect 117 283 175 320
+rect 0 225 175 283
+rect 225 283 283 320
+tri 283 283 400 400 sw
+rect 225 225 400 283
+rect 0 175 80 225
+rect 320 175 400 225
+rect 0 117 175 175
+tri 0 0 117 117 ne
+rect 117 80 175 117
+rect 225 117 400 175
+rect 225 80 283 117
+rect 117 0 283 80
+tri 283 0 400 117 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00007.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00007.mag
new file mode 100644
index 0000000..89547c6
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00007.mag
@@ -0,0 +1,21 @@
+magic
+tech s8seal_ring
+timestamp 1584558468
+<< type37 >>
+tri 0 283 117 400 se
+rect 117 320 283 400
+rect 117 283 175 320
+rect 0 225 175 283
+rect 225 283 283 320
+tri 283 283 400 400 sw
+rect 225 225 400 283
+rect 0 175 80 225
+rect 320 175 400 225
+rect 0 117 175 175
+tri 0 0 117 117 ne
+rect 117 80 175 117
+rect 225 117 400 175
+rect 225 80 283 117
+rect 117 0 283 80
+tri 283 0 400 117 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00011.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00011.mag
new file mode 100644
index 0000000..47854ae
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00011.mag
@@ -0,0 +1,99 @@
+magic
+tech s8seal_ring
+magscale 1 10
+timestamp 1584558468
+<< type81_51 >>
+tri -14938 151666 0 152400 se
+tri 0 151666 14938 152400 sw
+tri -29732 149472 -14938 151666 se
+rect -14938 149472 14938 151666
+tri 14938 149472 29732 151666 sw
+tri -44239 145838 -29732 149472 se
+rect -29732 145838 29732 149472
+tri 29732 145838 44239 149472 sw
+tri -58321 140799 -44239 145838 se
+rect -44239 140799 44239 145838
+tri 44239 140799 58321 145838 sw
+tri -71841 134405 -58321 140799 se
+rect -58321 134405 58321 140799
+tri 58321 134405 71841 140799 sw
+tri -84669 126716 -71841 134405 se
+rect -71841 126716 71841 134405
+tri 71841 126716 84669 134405 sw
+tri -96682 117807 -84669 126716 se
+rect -84669 117807 84669 126716
+tri 84669 117807 96682 126716 sw
+tri -107763 107763 -96682 117807 se
+rect -96682 107763 96682 117807
+tri 96682 107763 107763 117807 sw
+tri -117807 96682 -107763 107763 se
+rect -107763 96682 107763 107763
+tri 107763 96682 117807 107763 sw
+tri -126716 84669 -117807 96682 se
+rect -117807 84669 117807 96682
+tri 117807 84669 126716 96682 sw
+tri -134405 71841 -126716 84669 se
+rect -126716 71841 126716 84669
+tri 126716 71841 134405 84669 sw
+tri -140799 58321 -134405 71841 se
+rect -134405 58321 134405 71841
+tri 134405 58321 140799 71841 sw
+tri -145838 44239 -140799 58321 se
+rect -140799 44239 140799 58321
+tri 140799 44239 145838 58321 sw
+tri -149472 29732 -145838 44239 se
+rect -145838 29732 145838 44239
+tri 145838 29732 149472 44239 sw
+tri -151666 14938 -149472 29732 se
+rect -149472 14938 149472 29732
+tri 149472 14938 151666 29732 sw
+tri -152400 0 -151666 14938 se
+tri -152400 -14938 -151666 0 ne
+rect -151666 -14938 151666 14938
+tri 151666 0 152400 14938 sw
+tri 151666 -14938 152400 0 nw
+tri -151666 -29732 -149472 -14938 ne
+rect -149472 -29732 149472 -14938
+tri 149472 -29732 151666 -14938 nw
+tri -149472 -44239 -145838 -29732 ne
+rect -145838 -44239 145838 -29732
+tri 145838 -44239 149472 -29732 nw
+tri -145838 -58321 -140799 -44239 ne
+rect -140799 -58321 140799 -44239
+tri 140799 -58321 145838 -44239 nw
+tri -140799 -71841 -134405 -58321 ne
+rect -134405 -71841 134405 -58321
+tri 134405 -71841 140799 -58321 nw
+tri -134405 -84669 -126716 -71841 ne
+rect -126716 -84669 126716 -71841
+tri 126716 -84669 134405 -71841 nw
+tri -126716 -96682 -117807 -84669 ne
+rect -117807 -96682 117807 -84669
+tri 117807 -96682 126716 -84669 nw
+tri -117807 -107763 -107763 -96682 ne
+rect -107763 -107763 107763 -96682
+tri 107763 -107763 117807 -96682 nw
+tri -107763 -117807 -96682 -107763 ne
+rect -96682 -117807 96682 -107763
+tri 96682 -117807 107763 -107763 nw
+tri -96682 -126716 -84669 -117807 ne
+rect -84669 -126716 84669 -117807
+tri 84669 -126716 96682 -117807 nw
+tri -84669 -134405 -71841 -126716 ne
+rect -71841 -134405 71841 -126716
+tri 71841 -134405 84669 -126716 nw
+tri -71841 -140799 -58321 -134405 ne
+rect -58321 -140799 58321 -134405
+tri 58321 -140799 71841 -134405 nw
+tri -58321 -145838 -44239 -140799 ne
+rect -44239 -145838 44239 -140799
+tri 44239 -145838 58321 -140799 nw
+tri -44239 -149472 -29732 -145838 ne
+rect -29732 -149472 29732 -145838
+tri 29732 -149472 44239 -145838 nw
+tri -29732 -151666 -14938 -149472 ne
+rect -14938 -151666 14938 -149472
+tri 14938 -151666 29732 -149472 nw
+tri -14938 -152400 0 -151666 ne
+tri 0 -152400 14938 -151666 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00015.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00015.mag
new file mode 100644
index 0000000..d91c7fb
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00015.mag
@@ -0,0 +1,15 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558468
+<< type37 >>
+tri 0 1000 1099 2099 sw
+rect 0 200 200 1000
+tri 200 766 434 1000 nw
+tri 766 766 1000 1000 ne
+tri 200 200 434 434 sw
+tri 766 200 1000 434 se
+rect 1000 200 1099 1000
+rect 0 0 1099 200
+tri 1099 0 2099 1000 sw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00016.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00016.mag
new file mode 100644
index 0000000..7aa89fc
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00016.mag
@@ -0,0 +1,8 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+rect 290 2244 350 51210
+tri 290 2219 350 2244 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00019.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00019.mag
new file mode 100644
index 0000000..b316735
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00019.mag
@@ -0,0 +1,55 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+tri 290 2219 350 2244 se
+tri 350 2219 375 2244 sw
+tri 290 2134 375 2219 ne
+tri 375 2134 460 2219 sw
+tri 375 2049 460 2134 ne
+tri 460 2049 545 2134 sw
+tri 460 1964 545 2049 ne
+tri 545 1964 630 2049 sw
+tri 545 1879 630 1964 ne
+tri 630 1879 715 1964 sw
+tri 630 1794 715 1879 ne
+tri 715 1794 800 1879 sw
+tri 715 1709 800 1794 ne
+tri 800 1709 885 1794 sw
+tri 800 1624 885 1709 ne
+tri 885 1624 970 1709 sw
+tri 885 1539 970 1624 ne
+tri 970 1539 1055 1624 sw
+tri 970 1454 1055 1539 ne
+tri 1055 1454 1140 1539 sw
+tri 1055 1369 1140 1454 ne
+tri 1140 1369 1225 1454 sw
+tri 1140 1284 1225 1369 ne
+tri 1225 1284 1310 1369 sw
+tri 1225 1199 1310 1284 ne
+tri 1310 1199 1395 1284 sw
+tri 1310 1114 1395 1199 ne
+tri 1395 1114 1480 1199 sw
+tri 1395 1029 1480 1114 ne
+tri 1480 1029 1565 1114 sw
+tri 1480 944 1565 1029 ne
+tri 1565 944 1650 1029 sw
+tri 1565 859 1650 944 ne
+tri 1650 859 1735 944 sw
+tri 1650 774 1735 859 ne
+tri 1735 774 1820 859 sw
+tri 1735 689 1820 774 ne
+tri 1820 689 1905 774 sw
+tri 1820 604 1905 689 ne
+tri 1905 604 1990 689 sw
+tri 1905 519 1990 604 ne
+tri 1990 519 2075 604 sw
+tri 1990 434 2075 519 ne
+tri 2075 434 2160 519 sw
+tri 2075 349 2160 434 ne
+tri 2160 350 2244 434 sw
+rect 2160 349 51200 350
+tri 2160 290 2219 349 ne
+rect 2219 290 51200 349
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00020.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00020.mag
new file mode 100644
index 0000000..9e328f8
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00020.mag
@@ -0,0 +1,8 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+rect 410 2294 470 51210
+tri 410 2269 470 2294 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00023.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00023.mag
new file mode 100644
index 0000000..fe8335d
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00023.mag
@@ -0,0 +1,54 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+tri 410 2269 470 2294 se
+tri 470 2269 495 2294 sw
+tri 410 2184 495 2269 ne
+tri 495 2184 580 2269 sw
+tri 495 2099 580 2184 ne
+tri 580 2099 665 2184 sw
+tri 580 2014 665 2099 ne
+tri 665 2014 750 2099 sw
+tri 665 1929 750 2014 ne
+tri 750 1929 835 2014 sw
+tri 750 1844 835 1929 ne
+tri 835 1844 920 1929 sw
+tri 835 1759 920 1844 ne
+tri 920 1759 1005 1844 sw
+tri 920 1674 1005 1759 ne
+tri 1005 1674 1090 1759 sw
+tri 1005 1589 1090 1674 ne
+tri 1090 1589 1175 1674 sw
+tri 1090 1504 1175 1589 ne
+tri 1175 1504 1260 1589 sw
+tri 1175 1419 1260 1504 ne
+tri 1260 1419 1345 1504 sw
+tri 1260 1334 1345 1419 ne
+tri 1345 1334 1430 1419 sw
+tri 1345 1249 1430 1334 ne
+tri 1430 1249 1515 1334 sw
+tri 1430 1164 1515 1249 ne
+tri 1515 1164 1600 1249 sw
+tri 1515 1079 1600 1164 ne
+tri 1600 1079 1685 1164 sw
+tri 1600 994 1685 1079 ne
+tri 1685 994 1770 1079 sw
+tri 1685 909 1770 994 ne
+tri 1770 909 1855 994 sw
+tri 1770 824 1855 909 ne
+tri 1855 824 1940 909 sw
+tri 1855 739 1940 824 ne
+tri 1940 739 2025 824 sw
+tri 1940 654 2025 739 ne
+tri 2025 654 2110 739 sw
+tri 2025 569 2110 654 ne
+tri 2110 569 2195 654 sw
+tri 2110 484 2195 569 ne
+tri 2195 484 2280 569 sw
+tri 2195 410 2269 484 ne
+rect 2269 470 2280 484
+tri 2280 470 2294 484 sw
+rect 2269 410 51200 470
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00024.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00024.mag
new file mode 100644
index 0000000..eb9f364
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00024.mag
@@ -0,0 +1,8 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+rect 530 2344 590 51210
+tri 530 2319 590 2344 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00027.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00027.mag
new file mode 100644
index 0000000..c6d2ad1
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00027.mag
@@ -0,0 +1,53 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+tri 530 2319 590 2344 se
+tri 590 2319 615 2344 sw
+tri 530 2234 615 2319 ne
+tri 615 2234 700 2319 sw
+tri 615 2149 700 2234 ne
+tri 700 2149 785 2234 sw
+tri 700 2064 785 2149 ne
+tri 785 2064 870 2149 sw
+tri 785 1979 870 2064 ne
+tri 870 1979 955 2064 sw
+tri 870 1894 955 1979 ne
+tri 955 1894 1040 1979 sw
+tri 955 1809 1040 1894 ne
+tri 1040 1809 1125 1894 sw
+tri 1040 1724 1125 1809 ne
+tri 1125 1724 1210 1809 sw
+tri 1125 1639 1210 1724 ne
+tri 1210 1639 1295 1724 sw
+tri 1210 1554 1295 1639 ne
+tri 1295 1554 1380 1639 sw
+tri 1295 1469 1380 1554 ne
+tri 1380 1469 1465 1554 sw
+tri 1380 1384 1465 1469 ne
+tri 1465 1384 1550 1469 sw
+tri 1465 1299 1550 1384 ne
+tri 1550 1299 1635 1384 sw
+tri 1550 1214 1635 1299 ne
+tri 1635 1214 1720 1299 sw
+tri 1635 1129 1720 1214 ne
+tri 1720 1129 1805 1214 sw
+tri 1720 1044 1805 1129 ne
+tri 1805 1044 1890 1129 sw
+tri 1805 959 1890 1044 ne
+tri 1890 959 1975 1044 sw
+tri 1890 874 1975 959 ne
+tri 1975 874 2060 959 sw
+tri 1975 789 2060 874 ne
+tri 2060 789 2145 874 sw
+tri 2060 704 2145 789 ne
+tri 2145 704 2230 789 sw
+tri 2145 619 2230 704 ne
+tri 2230 619 2315 704 sw
+tri 2230 534 2315 619 ne
+tri 2315 590 2344 619 sw
+rect 2315 534 51200 590
+tri 2315 530 2319 534 ne
+rect 2319 530 51200 534
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00028.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00028.mag
new file mode 100644
index 0000000..3db918a
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00028.mag
@@ -0,0 +1,8 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+rect 650 2394 710 51210
+tri 650 2369 710 2394 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00031.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00031.mag
new file mode 100644
index 0000000..1eb8648
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00031.mag
@@ -0,0 +1,51 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type65_20 >>
+tri 650 2369 710 2394 se
+tri 710 2369 735 2394 sw
+tri 650 2284 735 2369 ne
+tri 735 2284 820 2369 sw
+tri 735 2199 820 2284 ne
+tri 820 2199 905 2284 sw
+tri 820 2114 905 2199 ne
+tri 905 2114 990 2199 sw
+tri 905 2029 990 2114 ne
+tri 990 2029 1075 2114 sw
+tri 990 1944 1075 2029 ne
+tri 1075 1944 1160 2029 sw
+tri 1075 1859 1160 1944 ne
+tri 1160 1859 1245 1944 sw
+tri 1160 1774 1245 1859 ne
+tri 1245 1774 1330 1859 sw
+tri 1245 1689 1330 1774 ne
+tri 1330 1689 1415 1774 sw
+tri 1330 1604 1415 1689 ne
+tri 1415 1604 1500 1689 sw
+tri 1415 1519 1500 1604 ne
+tri 1500 1519 1585 1604 sw
+tri 1500 1434 1585 1519 ne
+tri 1585 1434 1670 1519 sw
+tri 1585 1349 1670 1434 ne
+tri 1670 1349 1755 1434 sw
+tri 1670 1264 1755 1349 ne
+tri 1755 1264 1840 1349 sw
+tri 1755 1179 1840 1264 ne
+tri 1840 1179 1925 1264 sw
+tri 1840 1094 1925 1179 ne
+tri 1925 1094 2010 1179 sw
+tri 1925 1009 2010 1094 ne
+tri 2010 1009 2095 1094 sw
+tri 2010 924 2095 1009 ne
+tri 2095 924 2180 1009 sw
+tri 2095 839 2180 924 ne
+tri 2180 839 2265 924 sw
+tri 2180 754 2265 839 ne
+tri 2265 754 2350 839 sw
+tri 2265 669 2350 754 ne
+tri 2350 710 2394 754 sw
+rect 2350 669 51200 710
+tri 2350 650 2369 669 ne
+rect 2369 650 51200 669
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00032.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00032.mag
new file mode 100644
index 0000000..395db17
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00032.mag
@@ -0,0 +1,8 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type61_20 >>
+rect 0 2514 1000 51210
+tri 0 2099 1000 2514 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00035.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00035.mag
new file mode 100644
index 0000000..934e4e1
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00035.mag
@@ -0,0 +1,13 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type61_20 >>
+tri 0 2099 1000 2514 se
+tri 1000 2099 1415 2514 sw
+tri 0 684 1415 2099 ne
+tri 1415 1000 2514 2099 sw
+rect 1415 684 51200 1000
+tri 1415 0 2099 684 ne
+rect 2099 0 51200 684
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00036.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00036.mag
new file mode 100644
index 0000000..7e944a4
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00036.mag
@@ -0,0 +1,8 @@
+magic
+tech s8seal_ring
+magscale 1 2
+timestamp 1584558827
+<< type81_1 >>
+rect 0 2597 1200 51210
+tri 0 0 1200 2597 nw
+<< end >>
diff --git a/sky130/custom/scripts/seal_ring_generator/sr_polygon00039.mag b/sky130/custom/scripts/seal_ring_generator/sr_polygon00039.mag
new file mode 100644
index 0000000..24dfe83
--- /dev/null
+++ b/sky130/custom/scripts/seal_ring_generator/sr_polygon00039.mag
@@ -0,0 +1,10 @@
+magic
+tech s8seal_ring
+magscale 1 10
+timestamp 1584558827
+<< type81_1 >>
+tri 2772 6000 6000 12985 se
+tri 6000 6000 12985 12985 sw
+tri 0 0 2772 5999 se
+rect 2772 0 256000 6000
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/README b/sky130/custom/sky130_fd_io/README
new file mode 100644
index 0000000..edffb27
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/README
@@ -0,0 +1,20 @@
+This directory contains standard format files for "power_pads_lib",
+which is an efabless addendum to the SkyWater I/O library "s8iom0".
+
+power_pads_lib does the following:
+
+(1) Changes the orientation of the corner pad from upper-right to
+    lower-left with a wrapper cell called "s8iom0_corner_pad".  Also
+    extends the power buses to make the dimensions of the corner pad
+    multiples of 1um.
+
+(2) Adds a 1um-wide spacer cell to complement the existing 5um-wide
+    spacer cell.
+
+(3) Adds wrappers for all the combinations of power pad base cell +
+    power pad overlay, to create all 12 combinations, for pads with
+    either high- or low-voltage clamps, connecting to one of the six
+    power domains vddio, vdda, vccd, vssio, vssa, or vssd.
+
+"power_pads_lib" is open source copyright 2019 efabless, Inc.
+Released under Apache 2.0 license
diff --git a/sky130/custom/sky130_fd_io/cdl/power_pads_lib.cdl b/sky130/custom/sky130_fd_io/cdl/power_pads_lib.cdl
new file mode 100644
index 0000000..538405f
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/cdl/power_pads_lib.cdl
@@ -0,0 +1,92 @@
+* Power pads library (s8 power pads + overlays)
+* Includes corner and fill cell subcircuits
+
+.SUBCKT s8iom0_vdda_hvc_pad
++ amuxbus_a amuxbus_b drn_hvc src_bdy_hvc
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vdda_lvc_pad
++ amuxbus_a amuxbus_b drn_lvc1 drn_lvc2 src_bdy_lvc1 src_bdy_lvc2
++ bdy2_b2b vssi
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vddio_hvc_pad
++ amuxbus_a amuxbus_b drn_hvc src_bdy_hvc
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vddio_lvc_pad
++ amuxbus_a amuxbus_b drn_lvc1 drn_lvc2 src_bdy_lvc1 src_bdy_lvc2
++ bdy2_b2b vssi
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vccd_hvc_pad
++ amuxbus_a amuxbus_b drn_hvc src_bdy_hvc
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vccd_lvc_pad
++ amuxbus_a amuxbus_b drn_lvc1 drn_lvc2 src_bdy_lvc1 src_bdy_lvc2
++ bdy2_b2b vssi
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vssa_hvc_pad
++ amuxbus_a amuxbus_b drn_hvc src_bdy_hvc
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vssa_lvc_pad
++ amuxbus_a amuxbus_b drn_lvc1 drn_lvc2 src_bdy_lvc1 src_bdy_lvc2
++ bdy2_b2b vssi
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vssio_hvc_pad
++ amuxbus_a amuxbus_b drn_hvc src_bdy_hvc
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vssio_lvc_pad
++ amuxbus_a amuxbus_b drn_lvc1 drn_lvc2 src_bdy_lvc1 src_bdy_lvc2
++ bdy2_b2b vssi
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vssd_hvc_pad
++ amuxbus_a amuxbus_b drn_hvc src_bdy_hvc
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_vssd_lvc_pad
++ amuxbus_a amuxbus_b drn_lvc1 drn_lvc2 src_bdy_lvc1 src_bdy_lvc2
++ bdy2_b2b vssi
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_corner_pad
++ amuxbus_a amuxbus_b 
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0s8_com_bus_slice
++ amuxbus_a amuxbus_b
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0s8_com_bus_slice_1um
++ amuxbus_a amuxbus_b
++ vssa vdda vswitch vddio_q vcchib vddio vccd vssio vssd vssio_q
+.ENDS
+
+.SUBCKT s8iom0_gpiov2_pad
++ in_h pad_a_noesd_h pad_a_esd_0_h pad_a_esd_1_h
++ pad dm<2> dm<1> dm<0> hld_h_n in inp_dis ib_mode_sel enable_h enable_vdda_h
++ enable_inp_h oe_n tie_hi_esd tie_lo_esd slow vtrip_sel hld_ovr
++ analog_en analog_sel enable_vddio enable_vswitch_h analog_pol out
++ amuxbus_a amuxbus_b vssa vdda vswitch vddio_q vcchib vddio vccd vssio
++ vssd vssio_q
+.ENDS
diff --git a/sky130/custom/sky130_fd_io/gds/power_pads_lib.gds b/sky130/custom/sky130_fd_io/gds/power_pads_lib.gds
new file mode 100644
index 0000000..da0dc4d
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/gds/power_pads_lib.gds
Binary files differ
diff --git a/sky130/custom/sky130_fd_io/lef/power_pads_lib.lef b/sky130/custom/sky130_fd_io/lef/power_pads_lib.lef
new file mode 100644
index 0000000..1ff3c03
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/lef/power_pads_lib.lef
@@ -0,0 +1,5391 @@
+VERSION 5.3 ;
+   NAMESCASESENSITIVE ON ;
+   NOWIREEXTENSIONATPIN ON ;
+   DIVIDERCHAR "/" ;
+   BUSBITCHARS "[]" ;
+UNITS
+   DATABASE MICRONS 1000 ;
+END UNITS
+
+MACRO s8iom0_gpiov2_pad
+   CLASS PAD INOUT ;
+   FOREIGN s8iom0_gpiov2_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 80.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 36.4400 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 38.7600 51.0900 80.0000 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 52.1450 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 54.4650 46.3300 80.0000 49.3100 ;
+      END
+   END amuxbus_b
+   PIN analog_en
+      PORT
+         LAYER met1 ;
+	    RECT 62.4300 -2.0350 62.6900 -0.7300 ;
+      END
+   END analog_en
+   PIN analog_pol
+      PORT
+         LAYER met3 ;
+	    RECT 45.8650 -2.0350 46.1950 34.7700 ;
+      END
+   END analog_pol
+   PIN analog_sel
+      PORT
+         LAYER met2 ;
+	    RECT 30.7500 -2.0350 31.0100 0.2300 ;
+      END
+   END analog_sel
+   PIN dm<2>
+      PORT
+         LAYER met2 ;
+	    RECT 28.4900 -2.0350 28.7500 2.0350 ;
+      END
+   END dm<2>
+   PIN dm<1>
+      PORT
+         LAYER met2 ;
+	    RECT 66.8350 -2.0350 67.0950 -0.8400 ;
+      END
+   END dm<1>
+   PIN dm<0>
+      PORT
+         LAYER met2 ;
+	    RECT 49.8550 -2.0350 50.1150 -1.4900 ;
+      END
+   END dm<0>
+   PIN enable_h
+      PORT
+         LAYER met2 ;
+	    RECT 35.4600 -2.0350 35.7200 -0.4850 ;
+      END
+   END enable_h
+   PIN enable_inp_h
+      PORT
+         LAYER met2 ;
+	    RECT 38.3900 -2.0350 38.6500 1.0550 ;
+      END
+   END enable_inp_h
+   PIN enable_vdda_h
+      PORT
+         LAYER met2 ;
+	    RECT 12.7550 -2.0350 13.0150 3.3150 ;
+      END
+   END enable_vdda_h
+   PIN enable_vddio
+      PORT
+         LAYER met3 ;
+	    RECT 78.5800 -2.0350 78.9100 182.7400 ;
+      END
+   END enable_vddio
+   PIN enable_vswitch_h
+      PORT
+         LAYER met2 ;
+	    RECT 16.3100 -2.0350 16.5700 0.2850 ;
+      END
+   END enable_vswitch_h
+   PIN hld_h_n
+      PORT
+         LAYER met2 ;
+	    RECT 31.8150 -2.0350 32.0750 1.3050 ;
+      END
+   END hld_h_n
+   PIN hld_ovr
+      PORT
+         LAYER met2 ;
+	    RECT 26.6000 -2.0350 26.8600 0.6700 ;
+      END
+   END hld_ovr
+   PIN ib_mode_sel
+      PORT
+         LAYER met2 ;
+	    RECT 5.4200 -2.0350 5.6500 2.4400 ;
+      END
+   END ib_mode_sel
+   PIN in
+      PORT
+         LAYER met3 ;
+	    RECT 79.2400 -2.0350 79.5700 187.5250 ;
+      END
+   END in
+   PIN in_h
+      PORT
+         LAYER met3 ;
+	    RECT 0.4000 -2.0350 1.0200 176.4500 ;
+      END
+   END in_h
+   PIN inp_dis
+      PORT
+         LAYER met2 ;
+	    RECT 45.2450 -2.0350 45.5050 3.0550 ;
+      END
+   END inp_dis
+   PIN oe_n
+      PORT
+         LAYER met2 ;
+	    RECT 3.3750 -2.0350 3.6050 2.4400 ;
+      END
+   END oe_n
+   PIN out
+      PORT
+         LAYER met2 ;
+	    RECT 22.3550 -2.0350 22.6150 4.3900 ;
+      END
+   END out
+   PIN pad
+      PORT
+         LAYER met5 ;
+	    RECT 11.2000 102.5250 73.8000 164.9750 ;
+      END
+   END pad
+   PIN pad_a_esd_0_h
+      PORT
+         LAYER met2 ;
+	    RECT 76.2800 -2.0350 76.9200 0.0200 ;
+      END
+   END pad_a_esd_0_h
+   PIN pad_a_esd_1_h
+      PORT
+         LAYER met2 ;
+	    RECT 68.2750 -2.0350 68.9250 0.2350 ;
+      END
+   END pad_a_esd_1_h
+   PIN pad_a_noesd_h
+      PORT
+         LAYER met3 ;
+	    RECT 62.8200 -2.0350 63.8900 7.6700 ;
+      END
+   END pad_a_noesd_h
+   PIN slow
+      PORT
+         LAYER met2 ;
+	    RECT 77.6100 -2.0350 77.8700 -0.8500 ;
+      END
+   END slow
+   PIN tie_hi_esd
+      PORT
+         LAYER met2 ;
+	    RECT 78.7050 -2.0350 78.9050 -0.8200 ;
+      END
+   END tie_hi_esd
+   PIN tie_lo_esd
+      PORT
+         LAYER met2 ;
+	    RECT 79.7150 -2.0350 79.9150 175.8350 ;
+      END
+   END tie_lo_esd
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 6.9500 80.0000 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 6.8500 80.0000 11.5000 ;
+      END
+   END vccd
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 0.1000 80.0000 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 0.0000 80.0000 5.4500 ;
+      END
+   END vcchib
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.9700 13.0000 80.0000 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.9700 12.9000 80.0000 16.3500 ;
+      END
+   END vdda
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 68.0000 80.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 17.8500 80.0000 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 17.7500 80.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 68.0000 80.0000 92.9650 ;
+      END
+   END vddio
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 62.1500 80.0000 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 62.0500 80.0000 66.5000 ;
+      END
+   END vddio_q
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 2.6100 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 2.6100 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 45.7000 80.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 34.8050 80.0000 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 49.6100 80.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 47.0900 54.3700 80.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 47.0900 45.7000 80.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 34.7000 80.0000 38.1500 ;
+      END
+   END vssa
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 39.6500 80.0000 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 39.5500 80.0000 44.2000 ;
+      END
+   END vssd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 0.8100 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.9700 173.7500 80.0000 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 23.9000 80.0000 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 23.8000 80.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 173.7500 80.0000 197.9650 ;
+      END
+   END vssio
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 56.3000 80.0000 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 56.2000 80.0000 60.6500 ;
+      END
+   END vssio_q
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 78.7300 29.9500 80.0000 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 78.7300 29.8500 80.0000 33.3000 ;
+      END
+   END vswitch
+   PIN vtrip_sel
+      PORT
+         LAYER met2 ;
+	    RECT 6.1300 -2.0350 6.3900 -0.4850 ;
+      END
+   END vtrip_sel
+   OBS
+         LAYER li1 ;
+	    RECT -0.1600 -1.8050 80.1600 197.6700 ;
+         LAYER met1 ;
+	    RECT -0.1450 -0.4500 80.1450 197.9650 ;
+	    RECT -0.1450 -1.7750 62.1500 -0.4500 ;
+	    RECT 62.9700 -1.7750 80.1450 -0.4500 ;
+         LAYER met2 ;
+	    RECT 0.2100 176.1150 79.9150 197.9650 ;
+	    RECT 0.2100 4.6700 79.4350 176.1150 ;
+	    RECT 0.2100 3.5950 22.0750 4.6700 ;
+	    RECT 0.2100 2.7200 12.4750 3.5950 ;
+	    RECT 0.2100 -1.7850 3.0950 2.7200 ;
+	    RECT 3.8850 -1.7850 5.1400 2.7200 ;
+	    RECT 5.9300 -0.2050 12.4750 2.7200 ;
+	    RECT 6.6700 -1.7850 12.4750 -0.2050 ;
+	    RECT 13.2950 0.5650 22.0750 3.5950 ;
+	    RECT 13.2950 -1.7850 16.0300 0.5650 ;
+	    RECT 16.8500 -1.7850 22.0750 0.5650 ;
+	    RECT 22.8950 3.3350 79.4350 4.6700 ;
+	    RECT 22.8950 2.3150 44.9650 3.3350 ;
+	    RECT 22.8950 0.9500 28.2100 2.3150 ;
+	    RECT 22.8950 -1.7850 26.3200 0.9500 ;
+	    RECT 27.1400 -1.7850 28.2100 0.9500 ;
+	    RECT 29.0300 1.5850 44.9650 2.3150 ;
+	    RECT 29.0300 0.5100 31.5350 1.5850 ;
+	    RECT 29.0300 -1.7850 30.4700 0.5100 ;
+	    RECT 31.2900 -1.7850 31.5350 0.5100 ;
+	    RECT 32.3550 1.3350 44.9650 1.5850 ;
+	    RECT 32.3550 -0.2050 38.1100 1.3350 ;
+	    RECT 32.3550 -1.7850 35.1800 -0.2050 ;
+	    RECT 36.0000 -1.7850 38.1100 -0.2050 ;
+	    RECT 38.9300 -1.7850 44.9650 1.3350 ;
+	    RECT 45.7850 0.5150 79.4350 3.3350 ;
+	    RECT 45.7850 -0.5600 67.9950 0.5150 ;
+	    RECT 45.7850 -1.2100 66.5550 -0.5600 ;
+	    RECT 45.7850 -1.7850 49.5750 -1.2100 ;
+	    RECT 50.3950 -1.7850 66.5550 -1.2100 ;
+	    RECT 67.3750 -1.7850 67.9950 -0.5600 ;
+	    RECT 69.2050 0.3000 79.4350 0.5150 ;
+	    RECT 69.2050 -1.7850 76.0000 0.3000 ;
+	    RECT 77.2000 -0.5400 79.4350 0.3000 ;
+	    RECT 77.2000 -0.5700 78.4250 -0.5400 ;
+	    RECT 77.2000 -1.7850 77.3300 -0.5700 ;
+	    RECT 78.1500 -1.7850 78.4250 -0.5700 ;
+	    RECT 79.1850 -1.7850 79.4350 -0.5400 ;
+         LAYER met3 ;
+	    RECT 0.4000 187.9250 79.5700 197.9650 ;
+	    RECT 0.4000 183.1400 78.8400 187.9250 ;
+	    RECT 0.4000 176.8500 78.1800 183.1400 ;
+	    RECT 1.4200 35.1700 78.1800 176.8500 ;
+	    RECT 1.4200 -1.7900 45.4650 35.1700 ;
+	    RECT 46.5950 8.0700 78.1800 35.1700 ;
+	    RECT 46.5950 -1.7900 62.4200 8.0700 ;
+	    RECT 64.2900 -1.7900 78.1800 8.0700 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 78.3300 197.9650 ;
+	    RECT 0.9650 93.3650 78.9700 173.3500 ;
+	    RECT 1.6700 67.6000 78.3300 93.3650 ;
+	    RECT 0.9650 66.9000 78.9700 67.6000 ;
+	    RECT 1.6700 61.6500 78.3300 66.9000 ;
+	    RECT 0.9650 61.0500 78.9700 61.6500 ;
+	    RECT 1.6700 55.8000 78.3300 61.0500 ;
+	    RECT 0.9650 55.1000 78.9700 55.8000 ;
+	    RECT 3.0100 54.4700 46.6900 55.1000 ;
+	    RECT 36.8400 50.6900 38.3600 54.4700 ;
+	    RECT 1.6700 49.7100 78.3300 50.6900 ;
+	    RECT 52.5450 46.4300 54.0650 49.7100 ;
+	    RECT 3.0100 45.3000 46.6900 45.9300 ;
+	    RECT 0.9650 44.6000 78.9700 45.3000 ;
+	    RECT 1.6700 39.1500 78.3300 44.6000 ;
+	    RECT 0.9650 38.5500 78.9700 39.1500 ;
+	    RECT 1.6700 34.3000 78.3300 38.5500 ;
+	    RECT 0.9650 33.7000 78.9700 34.3000 ;
+	    RECT 1.6700 29.4500 78.3300 33.7000 ;
+	    RECT 0.9650 28.8500 78.9700 29.4500 ;
+	    RECT 1.6700 23.4000 78.3300 28.8500 ;
+	    RECT 0.9650 22.8000 78.9700 23.4000 ;
+	    RECT 1.6700 17.3500 78.3300 22.8000 ;
+	    RECT 0.9650 16.7500 78.9700 17.3500 ;
+	    RECT 1.3650 12.5000 78.5700 16.7500 ;
+	    RECT 0.9650 11.9000 78.9700 12.5000 ;
+	    RECT 1.6700 6.4500 78.3300 11.9000 ;
+	    RECT 0.9650 5.8500 78.9700 6.4500 ;
+	    RECT 1.6700 -0.4000 78.3300 5.8500 ;
+	    RECT 0.9650 -1.5000 78.9700 -0.4000 ;
+         LAYER met5 ;
+	    RECT 0.0000 166.5750 80.0000 197.9650 ;
+	    RECT 0.0000 100.9250 9.6000 166.5750 ;
+	    RECT 75.4000 100.9250 80.0000 166.5750 ;
+	    RECT 0.0000 94.5500 80.0000 100.9250 ;
+	    RECT 2.8700 16.2500 77.1300 94.5500 ;
+	    RECT 2.5650 13.0000 77.3700 16.2500 ;
+	    RECT 2.8700 0.1000 77.1300 13.0000 ;
+   END
+END s8iom0_gpiov2_pad
+MACRO s8iom0_vddio_lvc_pad
+   CLASS PAD POWER ;
+   FOREIGN s8iom0_vddio_lvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_lvc1
+      PORT
+         LAYER met3 ;
+	    RECT 26.0000 -0.0350 36.8800 20.1850 ;
+      END
+   END drn_lvc1
+   PIN drn_lvc2
+      PORT
+         LAYER met3 ;
+	    RECT 38.3800 -0.0350 49.2550 22.8650 ;
+      END
+   END drn_lvc2
+   PIN src_bdy_lvc1
+      PORT
+         LAYER met2 ;
+	    RECT 0.5000 -0.0350 20.4950 1.4500 ;
+      END
+   END src_bdy_lvc1
+   PIN src_bdy_lvc2
+      PORT
+         LAYER met2 ;
+	    RECT 54.7150 -0.0350 74.7000 3.6250 ;
+      END
+   END src_bdy_lvc2
+   PIN bdy2_b2b
+      PORT
+         LAYER met2 ;
+	    RECT 34.4400 -0.0350 44.4400 0.2900 ;
+      END
+   END bdy2_b2b
+   PIN vssi
+      PORT
+         LAYER met1 ;
+	    RECT 34.3350 0.4750 35.3350 0.9750 ;
+      END
+   END vssi
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 9.3150 100.1050 65.9550 167.5350 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.7550 -0.0350 74.7000 17.7650 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.5000 -0.0350 24.5000 17.7650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 0.2400 0.9850 74.7550 197.7450 ;
+         LAYER met1 ;
+	    RECT 0.1200 1.2550 74.7850 197.8050 ;
+	    RECT 0.1200 0.1950 34.0550 1.2550 ;
+	    RECT 35.6150 0.1950 74.7850 1.2550 ;
+	    RECT 0.1200 -0.0350 74.7850 0.1950 ;
+         LAYER met2 ;
+	    RECT 0.4900 3.9050 74.7000 194.3950 ;
+	    RECT 0.4900 1.7300 54.4350 3.9050 ;
+	    RECT 20.7750 0.5700 54.4350 1.7300 ;
+	    RECT 20.7750 -0.0350 34.1600 0.5700 ;
+	    RECT 44.7200 -0.0350 54.4350 0.5700 ;
+         LAYER met3 ;
+	    RECT 0.4900 23.2650 74.7000 189.4800 ;
+	    RECT 0.4900 20.5850 37.9800 23.2650 ;
+	    RECT 0.4900 18.1650 25.6000 20.5850 ;
+	    RECT 24.9000 0.0000 25.6000 18.1650 ;
+	    RECT 37.2800 0.0000 37.9800 20.5850 ;
+	    RECT 49.6550 18.1650 74.7000 23.2650 ;
+	    RECT 49.6550 0.0000 50.3550 18.1650 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 169.1350 75.0000 197.9650 ;
+	    RECT 0.0000 98.5050 7.7150 169.1350 ;
+	    RECT 67.5550 98.5050 75.0000 169.1350 ;
+	    RECT 0.0000 94.5500 75.0000 98.5050 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vddio_lvc_pad
+MACRO s8iom0_vddio_hvc_pad
+   CLASS PAD POWER ;
+   FOREIGN s8iom0_vddio_hvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 50.3900 -2.0350 74.2900 23.6250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 37.8900 -2.0350 48.8900 10.3450 ;
+      END
+   END drn_hvc
+   PIN src_bdy_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 0.4950 -2.0350 24.3950 0.0200 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 25.8950 -2.0350 36.8950 10.3900 ;
+      END
+   END src_bdy_hvc
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 6.1000 101.9750 68.8000 164.5900 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.3900 -2.0350 74.2900 88.1500 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.4950 -2.0350 24.3950 30.4800 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2050 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.2250 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 1.0700 -1.0350 72.7750 197.6600 ;
+         LAYER met1 ;
+	    RECT 0.1850 -1.0650 73.6200 197.6900 ;
+         LAYER met2 ;
+	    RECT 0.2650 23.9050 74.2900 193.0400 ;
+	    RECT 0.2650 0.3000 50.1100 23.9050 ;
+	    RECT 24.6750 -2.0350 50.1100 0.3000 ;
+         LAYER met3 ;
+	    RECT 0.2400 88.5500 74.2900 197.9650 ;
+	    RECT 0.2400 30.8800 49.9900 88.5500 ;
+	    RECT 24.7950 10.7900 49.9900 30.8800 ;
+	    RECT 24.7950 10.3450 25.4950 10.7900 ;
+	    RECT 37.2950 10.7450 49.9900 10.7900 ;
+	    RECT 37.2950 10.3450 37.4900 10.7450 ;
+	    RECT 49.2900 10.3450 49.9900 10.7450 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 166.1900 75.0000 197.9650 ;
+	    RECT 0.0000 100.3750 4.5000 166.1900 ;
+	    RECT 70.4000 100.3750 75.0000 166.1900 ;
+	    RECT 0.0000 94.5500 75.0000 100.3750 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vddio_hvc_pad
+MACRO s8iom0_vccd_hvc_pad
+   CLASS PAD POWER ;
+   FOREIGN s8iom0_vccd_hvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 50.3900 -2.0350 74.2900 23.6250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 37.8900 -2.0350 48.8900 10.3450 ;
+      END
+   END drn_hvc
+   PIN src_bdy_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 0.4950 -2.0350 24.3950 0.0200 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 25.8950 -2.0350 36.8950 10.3900 ;
+      END
+   END src_bdy_hvc
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 6.1000 101.9750 68.8000 164.5900 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.3900 -2.0350 74.2900 6.8650 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.4950 -2.0350 24.3950 6.8650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2050 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.2250 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 1.0700 -1.0350 72.7750 197.6600 ;
+         LAYER met1 ;
+	    RECT 0.1850 -1.0650 73.6200 197.6900 ;
+         LAYER met2 ;
+	    RECT 0.2650 23.9050 74.2900 193.0400 ;
+	    RECT 0.2650 0.3000 50.1100 23.9050 ;
+	    RECT 24.6750 -2.0350 50.1100 0.3000 ;
+         LAYER met3 ;
+	    RECT 0.2400 10.7900 74.2900 197.9650 ;
+	    RECT 0.2400 7.2650 25.4950 10.7900 ;
+	    RECT 24.7950 6.8650 25.4950 7.2650 ;
+	    RECT 37.2950 10.7450 74.2900 10.7900 ;
+	    RECT 37.2950 6.8650 37.4900 10.7450 ;
+	    RECT 49.2900 7.2650 74.2900 10.7450 ;
+	    RECT 49.2900 6.8650 49.9900 7.2650 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 166.1900 75.0000 197.9650 ;
+	    RECT 0.0000 100.3750 4.5000 166.1900 ;
+	    RECT 70.4000 100.3750 75.0000 166.1900 ;
+	    RECT 0.0000 94.5500 75.0000 100.3750 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vccd_hvc_pad
+MACRO s8iom0_vccd_lvc_pad
+   CLASS PAD POWER ;
+   FOREIGN s8iom0_vccd_lvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_lvc1
+      PORT
+         LAYER met3 ;
+	    RECT 26.0000 -0.0350 36.8800 20.1850 ;
+      END
+   END drn_lvc1
+   PIN drn_lvc2
+      PORT
+         LAYER met3 ;
+	    RECT 38.3800 -0.0350 49.2550 22.8650 ;
+      END
+   END drn_lvc2
+   PIN src_bdy_lvc1
+      PORT
+         LAYER met2 ;
+	    RECT 0.5000 -0.0350 20.4950 1.4500 ;
+      END
+   END src_bdy_lvc1
+   PIN src_bdy_lvc2
+      PORT
+         LAYER met2 ;
+	    RECT 54.7150 -0.0350 74.7000 3.6250 ;
+      END
+   END src_bdy_lvc2
+   PIN bdy2_b2b
+      PORT
+         LAYER met2 ;
+	    RECT 34.4400 -0.0350 44.4400 0.2900 ;
+      END
+   END bdy2_b2b
+   PIN vssi
+      PORT
+         LAYER met1 ;
+	    RECT 34.3350 0.4750 35.3350 0.9750 ;
+      END
+   END vssi
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 9.3150 100.1050 65.9550 167.5350 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.7550 -0.0350 74.7000 6.8650 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.5000 -0.0350 24.5000 6.8650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 74.2250 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2050 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 0.2400 0.9850 74.7550 197.7450 ;
+         LAYER met1 ;
+	    RECT 0.1200 1.2550 74.7850 197.8050 ;
+	    RECT 0.1200 0.1950 34.0550 1.2550 ;
+	    RECT 35.6150 0.1950 74.7850 1.2550 ;
+	    RECT 0.1200 -0.0350 74.7850 0.1950 ;
+         LAYER met2 ;
+	    RECT 0.4900 3.9050 74.7000 194.3950 ;
+	    RECT 0.4900 1.7300 54.4350 3.9050 ;
+	    RECT 20.7750 0.5700 54.4350 1.7300 ;
+	    RECT 20.7750 -0.0350 34.1600 0.5700 ;
+	    RECT 44.7200 -0.0350 54.4350 0.5700 ;
+         LAYER met3 ;
+	    RECT 0.4900 23.2650 74.7000 189.4800 ;
+	    RECT 0.4900 20.5850 37.9800 23.2650 ;
+	    RECT 0.4900 7.2650 25.6000 20.5850 ;
+	    RECT 24.9000 0.0000 25.6000 7.2650 ;
+	    RECT 37.2800 0.0000 37.9800 20.5850 ;
+	    RECT 49.6550 7.2650 74.7000 23.2650 ;
+	    RECT 49.6550 0.0000 50.3550 7.2650 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 169.1350 75.0000 197.9650 ;
+	    RECT 0.0000 98.5050 7.7150 169.1350 ;
+	    RECT 67.5550 98.5050 75.0000 169.1350 ;
+	    RECT 0.0000 94.5500 75.0000 98.5050 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vccd_lvc_pad
+MACRO s8iom0_vdda_hvc_pad
+   CLASS PAD POWER ;
+   FOREIGN s8iom0_vdda_hvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 50.3900 -2.0350 74.2900 23.6250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 37.8900 -2.0350 48.8900 10.3450 ;
+      END
+   END drn_hvc
+   PIN src_bdy_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 0.4950 -2.0350 24.3950 0.0200 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 25.8950 -2.0350 36.8950 10.3900 ;
+      END
+   END src_bdy_hvc
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 6.1000 101.9750 68.8000 164.5900 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.3900 -2.0350 74.2900 6.8650 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.4950 -2.0350 24.3950 6.8650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 74.2250 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2050 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.6300 189.5650 0.6400 189.5750 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.3600 189.5650 74.3700 189.5750 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 1.0700 -1.0350 72.7750 197.6600 ;
+         LAYER met1 ;
+	    RECT 0.1850 -1.0650 73.6200 197.6900 ;
+         LAYER met2 ;
+	    RECT 0.2650 23.9050 74.2900 193.0400 ;
+	    RECT 0.2650 0.3000 50.1100 23.9050 ;
+	    RECT 24.6750 -2.0350 50.1100 0.3000 ;
+         LAYER met3 ;
+	    RECT 0.2400 10.7900 74.6550 197.9650 ;
+	    RECT 0.2400 7.2650 25.4950 10.7900 ;
+	    RECT 24.7950 6.8550 25.4950 7.2650 ;
+	    RECT 37.2950 10.7450 74.6550 10.7900 ;
+	    RECT 37.2950 6.8550 37.4900 10.7450 ;
+	    RECT 49.2900 7.2650 74.6550 10.7450 ;
+	    RECT 49.2900 6.8550 49.9900 7.2650 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 166.1900 75.0000 197.9650 ;
+	    RECT 0.0000 100.3750 4.5000 166.1900 ;
+	    RECT 70.4000 100.3750 75.0000 166.1900 ;
+	    RECT 0.0000 94.5500 75.0000 100.3750 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vdda_hvc_pad
+MACRO s8iom0_vdda_lvc_pad
+   CLASS PAD POWER ;
+   FOREIGN s8iom0_vdda_lvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_lvc1
+      PORT
+         LAYER met3 ;
+	    RECT 26.0000 -0.0350 36.8800 20.1850 ;
+      END
+   END drn_lvc1
+   PIN drn_lvc2
+      PORT
+         LAYER met3 ;
+	    RECT 38.3800 -0.0350 49.2550 22.8650 ;
+      END
+   END drn_lvc2
+   PIN src_bdy_lvc1
+      PORT
+         LAYER met2 ;
+	    RECT 0.5000 -0.0350 20.4950 1.4500 ;
+      END
+   END src_bdy_lvc1
+   PIN src_bdy_lvc2
+      PORT
+         LAYER met2 ;
+	    RECT 54.7150 -0.0350 74.7000 3.6250 ;
+      END
+   END src_bdy_lvc2
+   PIN bdy2_b2b
+      PORT
+         LAYER met2 ;
+	    RECT 34.4400 -0.0350 44.4400 0.2900 ;
+      END
+   END bdy2_b2b
+   PIN vssi
+      PORT
+         LAYER met1 ;
+	    RECT 34.3350 0.4750 35.3350 0.9750 ;
+      END
+   END vssi
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met3 ;
+	    RECT 50.7550 -0.0350 74.7000 12.9250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.5000 -0.0350 24.5000 12.9250 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 9.3150 100.1050 65.9550 167.5350 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 0.2400 0.9850 74.7550 197.7450 ;
+         LAYER met1 ;
+	    RECT 0.1200 1.2550 74.7850 197.8050 ;
+	    RECT 0.1200 0.1950 34.0550 1.2550 ;
+	    RECT 35.6150 0.1950 74.7850 1.2550 ;
+	    RECT 0.1200 -0.0350 74.7850 0.1950 ;
+         LAYER met2 ;
+	    RECT 0.4900 3.9050 74.7000 194.3950 ;
+	    RECT 0.4900 1.7300 54.4350 3.9050 ;
+	    RECT 20.7750 0.5700 54.4350 1.7300 ;
+	    RECT 20.7750 -0.0350 34.1600 0.5700 ;
+	    RECT 44.7200 -0.0350 54.4350 0.5700 ;
+         LAYER met3 ;
+	    RECT 0.4900 23.2650 74.7000 189.4800 ;
+	    RECT 0.4900 20.5850 37.9800 23.2650 ;
+	    RECT 0.4900 13.3250 25.6000 20.5850 ;
+	    RECT 24.9000 0.0000 25.6000 13.3250 ;
+	    RECT 37.2800 0.0000 37.9800 20.5850 ;
+	    RECT 49.6550 13.3250 74.7000 23.2650 ;
+	    RECT 49.6550 0.0000 50.3550 13.3250 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 169.1350 75.0000 197.9650 ;
+	    RECT 0.0000 98.5050 7.7150 169.1350 ;
+	    RECT 67.5550 98.5050 75.0000 169.1350 ;
+	    RECT 0.0000 94.5500 75.0000 98.5050 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vdda_lvc_pad
+MACRO s8iom0s8_com_bus_slice_1um
+   CLASS PAD SPACER ;
+   FOREIGN s8iom0s8_com_bus_slice_1um ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 1.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.0000 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.0000 49.3100 ;
+      END
+   END amuxbus_b
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.0000 46.0300 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8000 1.0000 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.0000 50.7900 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 1.0000 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 1.0000 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.0000 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.0000 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.0000 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.0000 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.0000 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.0000 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.0000 92.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.0000 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.0000 22.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.0000 92.9500 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.0000 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.0000 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.0000 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.0000 28.4500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 173.7500 1.0000 197.9650 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.0000 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.0000 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.0000 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.0000 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.0000 197.9650 ;
+   END
+END s8iom0s8_com_bus_slice_1um
+MACRO s8iom0_vssio_hvc_pad
+   CLASS PAD GROUND ;
+   FOREIGN s8iom0_vssio_hvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 50.3900 -2.0350 74.2900 23.6250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 37.8900 -2.0350 48.8900 10.3450 ;
+      END
+   END drn_hvc
+   PIN src_bdy_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 0.4950 -2.0350 24.3950 0.0200 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 25.8950 -2.0350 36.8950 10.3900 ;
+      END
+   END src_bdy_hvc
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met5 ;
+	    RECT 6.1000 101.9750 68.8000 164.5900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.6300 189.5650 0.6400 189.5750 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.2500 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.4950 -2.0350 24.3950 23.8150 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.3900 -2.0350 74.2900 23.8150 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 1.0700 -1.0350 72.7750 197.6600 ;
+         LAYER met1 ;
+	    RECT 0.1850 -1.0650 73.6200 197.6900 ;
+         LAYER met2 ;
+	    RECT 0.2650 23.9050 74.2900 193.0400 ;
+	    RECT 0.2650 0.3000 50.1100 23.9050 ;
+	    RECT 24.6750 -2.0350 50.1100 0.3000 ;
+         LAYER met3 ;
+	    RECT 0.2400 24.2150 74.2900 197.9650 ;
+	    RECT 24.7950 10.7900 49.9900 24.2150 ;
+	    RECT 24.7950 10.3450 25.4950 10.7900 ;
+	    RECT 37.2950 10.7450 49.9900 10.7900 ;
+	    RECT 37.2950 10.3450 37.4900 10.7450 ;
+	    RECT 49.2900 10.3450 49.9900 10.7450 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 166.1900 75.0000 197.9650 ;
+	    RECT 0.0000 100.3750 4.5000 166.1900 ;
+	    RECT 70.4000 100.3750 75.0000 166.1900 ;
+	    RECT 0.0000 94.5500 75.0000 100.3750 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vssio_hvc_pad
+MACRO s8iom0_corner_pad
+   CLASS ENDCAP TOPRIGHT ;
+   FOREIGN s8iom0_corner_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 200.0000 BY 204.0000 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 57.1250 22.9100 60.1050 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 53.1250 0.0000 56.1050 26.9100 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 52.3650 20.9350 55.3450 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 48.3650 0.0000 51.3450 20.8750 ;
+      END
+   END amuxbus_b
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 51.7350 23.1550 60.7350 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.6300 56.0200 0.6400 56.0300 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 40.8350 1.3350 44.0850 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.7350 19.5750 52.0650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 40.7350 1.3350 44.1850 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 55.6450 21.5500 56.8250 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 60.4050 23.1750 60.7350 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 36.8400 0.0000 40.0850 1.2700 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 47.7350 0.0000 56.7350 27.1550 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 51.2850 0.6300 51.2950 0.6400 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 56.4050 0.0000 56.7350 27.1750 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 51.6450 0.0000 52.8250 21.5550 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 36.7350 0.0000 40.1850 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 47.7350 0.0000 48.0650 23.5750 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 19.0350 1.4700 22.2850 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 18.9350 1.4700 22.3850 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 15.0350 0.0000 18.2850 1.2550 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 14.9350 0.0000 18.3850 1.2550 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 35.9850 1.3850 39.2350 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 35.8850 1.3850 39.3350 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 31.9850 0.0000 35.2350 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 31.8850 0.0000 35.3350 1.2700 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.1850 1.4800 72.4350 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0850 1.4800 72.5350 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 64.1850 0.0000 68.4350 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 64.0850 0.0000 68.5350 1.2700 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.1350 2.3500 11.3850 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.0350 2.3500 11.4850 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 2.1350 0.0000 7.3850 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 2.0350 0.0000 7.4850 1.2700 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 74.0350 2.6450 98.9850 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.8850 1.5250 28.3350 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.7850 1.5250 28.4350 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 74.0350 2.6450 99.0000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 19.8850 0.0000 24.3350 1.2700 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 70.0350 0.0000 94.9850 1.8550 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 70.0350 0.0000 95.0000 1.8550 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 19.7850 0.0000 24.4350 1.2700 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 12.9850 3.7850 17.4350 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.8850 3.7850 17.5350 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 8.9850 0.0000 13.4350 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 8.8850 0.0000 13.5350 1.2700 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9350 1.6000 34.3850 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8350 1.6000 34.4850 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 179.7850 1.4350 204.0000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.6300 194.8650 0.6400 194.8750 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 25.9350 0.0000 30.3850 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 25.8350 0.0000 30.4850 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 175.7850 0.0000 200.0000 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 190.8650 0.6300 190.8750 0.6400 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.6850 1.4750 50.1350 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.5850 1.4750 50.2350 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 41.6850 0.0000 46.1350 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 41.5850 0.0000 46.2350 1.2700 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.3350 1.6250 66.5850 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.2350 1.6250 66.6850 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 58.3350 0.0000 62.5850 1.2700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 58.2350 0.0000 62.6850 1.2700 ;
+      END
+   END vssio_q
+   OBS
+         LAYER met4 ;
+	    RECT 1.8350 179.3850 200.0000 204.0000 ;
+	    RECT 0.0000 99.4000 200.0000 179.3850 ;
+	    RECT 3.0450 73.6350 200.0000 99.4000 ;
+	    RECT 0.0000 72.9350 200.0000 73.6350 ;
+	    RECT 1.8800 67.6850 200.0000 72.9350 ;
+	    RECT 0.0000 67.0850 200.0000 67.6850 ;
+	    RECT 2.0250 61.8350 200.0000 67.0850 ;
+	    RECT 0.0000 61.1350 200.0000 61.8350 ;
+	    RECT 23.5750 60.0050 200.0000 61.1350 ;
+	    RECT 23.3100 56.7250 200.0000 60.0050 ;
+	    RECT 21.9500 55.2450 200.0000 56.7250 ;
+	    RECT 21.3350 51.9650 200.0000 55.2450 ;
+	    RECT 19.9750 51.3350 200.0000 51.9650 ;
+	    RECT 0.0000 50.6350 200.0000 51.3350 ;
+	    RECT 1.8750 45.1850 200.0000 50.6350 ;
+	    RECT 0.0000 44.5850 200.0000 45.1850 ;
+	    RECT 1.7350 40.3350 200.0000 44.5850 ;
+	    RECT 0.0000 39.7350 200.0000 40.3350 ;
+	    RECT 1.7850 35.4850 200.0000 39.7350 ;
+	    RECT 0.0000 34.8850 200.0000 35.4850 ;
+	    RECT 2.0000 29.4350 200.0000 34.8850 ;
+	    RECT 0.0000 28.8350 200.0000 29.4350 ;
+	    RECT 1.9250 27.5750 200.0000 28.8350 ;
+	    RECT 1.9250 27.3100 56.0050 27.5750 ;
+	    RECT 1.9250 23.9750 52.7250 27.3100 ;
+	    RECT 1.9250 23.3850 47.3350 23.9750 ;
+	    RECT 0.0000 22.7850 47.3350 23.3850 ;
+	    RECT 1.8700 18.5350 47.3350 22.7850 ;
+	    RECT 48.4650 21.9550 52.7250 23.9750 ;
+	    RECT 48.4650 21.2750 51.2450 21.9550 ;
+	    RECT 0.0000 17.9350 47.3350 18.5350 ;
+	    RECT 4.1850 12.4850 47.3350 17.9350 ;
+	    RECT 0.0000 11.8850 47.3350 12.4850 ;
+	    RECT 2.7500 5.6350 47.3350 11.8850 ;
+	    RECT 0.0000 1.6700 47.3350 5.6350 ;
+	    RECT 0.0000 1.2550 1.6350 1.6700 ;
+	    RECT 7.8850 1.2550 8.4850 1.6700 ;
+	    RECT 13.9350 1.6550 19.3850 1.6700 ;
+	    RECT 13.9350 1.2550 14.5350 1.6550 ;
+	    RECT 18.7850 1.2550 19.3850 1.6550 ;
+	    RECT 24.8350 1.2550 25.4350 1.6700 ;
+	    RECT 30.8850 1.2550 31.4850 1.6700 ;
+	    RECT 35.7350 1.2550 36.3350 1.6700 ;
+	    RECT 40.5850 1.2550 41.1850 1.6700 ;
+	    RECT 46.6350 1.2550 47.3350 1.6700 ;
+	    RECT 57.1350 2.2550 200.0000 27.5750 ;
+	    RECT 57.1350 1.6700 69.6350 2.2550 ;
+	    RECT 57.1350 1.2550 57.8350 1.6700 ;
+	    RECT 63.0850 1.2550 63.6850 1.6700 ;
+	    RECT 68.9350 1.2550 69.6350 1.6700 ;
+	    RECT 95.4000 1.6700 200.0000 2.2550 ;
+	    RECT 95.4000 1.2550 175.3850 1.6700 ;
+         LAYER met5 ;
+	    RECT 0.0000 100.5850 200.0000 204.0000 ;
+	    RECT 4.2450 72.4350 200.0000 100.5850 ;
+	    RECT 3.0800 68.1850 200.0000 72.4350 ;
+	    RECT 3.2250 62.3350 200.0000 68.1850 ;
+	    RECT 24.7550 50.1350 200.0000 62.3350 ;
+	    RECT 3.0750 44.0850 200.0000 50.1350 ;
+	    RECT 2.9350 40.8350 200.0000 44.0850 ;
+	    RECT 2.9850 35.9850 200.0000 40.8350 ;
+	    RECT 3.2000 28.7550 200.0000 35.9850 ;
+	    RECT 3.2000 28.3350 46.1350 28.7550 ;
+	    RECT 3.1250 22.2850 46.1350 28.3350 ;
+	    RECT 3.0700 19.0350 46.1350 22.2850 ;
+	    RECT 5.3850 11.3850 46.1350 19.0350 ;
+	    RECT 3.9500 4.5350 46.1350 11.3850 ;
+	    RECT 0.0000 2.8700 46.1350 4.5350 ;
+	    RECT 58.3350 3.4550 200.0000 28.7550 ;
+	    RECT 58.3350 2.8700 68.4350 3.4550 ;
+	    RECT 0.0000 0.0000 0.5350 2.8700 ;
+	    RECT 15.0350 2.8550 18.2850 2.8700 ;
+	    RECT 96.5850 0.0000 200.0000 3.4550 ;
+   END
+END s8iom0_corner_pad
+MACRO s8iom0_vssio_lvc_pad
+   CLASS PAD GROUND ;
+   FOREIGN s8iom0_vssio_lvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_lvc1
+      PORT
+         LAYER met3 ;
+	    RECT 26.0000 -0.0350 36.8800 20.1850 ;
+      END
+   END drn_lvc1
+   PIN drn_lvc2
+      PORT
+         LAYER met3 ;
+	    RECT 38.3800 -0.0350 49.2550 22.8650 ;
+      END
+   END drn_lvc2
+   PIN src_bdy_lvc1
+      PORT
+         LAYER met2 ;
+	    RECT 0.5000 -0.0350 20.4950 1.4500 ;
+      END
+   END src_bdy_lvc1
+   PIN src_bdy_lvc2
+      PORT
+         LAYER met2 ;
+	    RECT 54.7150 -0.0350 74.7000 3.6250 ;
+      END
+   END src_bdy_lvc2
+   PIN bdy2_b2b
+      PORT
+         LAYER met2 ;
+	    RECT 34.4400 -0.0350 44.4400 0.2900 ;
+      END
+   END bdy2_b2b
+   PIN vssi
+      PORT
+         LAYER met1 ;
+	    RECT 34.3350 0.4750 35.3350 0.9750 ;
+      END
+   END vssi
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met5 ;
+	    RECT 9.3150 100.1050 65.9550 167.5350 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.7550 -0.0350 74.7000 23.8150 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.5000 -0.0350 24.5000 23.8150 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 0.2400 0.9850 74.7550 197.7450 ;
+         LAYER met1 ;
+	    RECT 0.1200 1.2550 74.7850 197.8050 ;
+	    RECT 0.1200 0.1950 34.0550 1.2550 ;
+	    RECT 35.6150 0.1950 74.7850 1.2550 ;
+	    RECT 0.1200 -0.0350 74.7850 0.1950 ;
+         LAYER met2 ;
+	    RECT 0.5000 3.9050 74.7000 194.3950 ;
+	    RECT 0.5000 1.7300 54.4350 3.9050 ;
+	    RECT 20.7750 0.5700 54.4350 1.7300 ;
+	    RECT 20.7750 -0.0350 34.1600 0.5700 ;
+	    RECT 44.7200 -0.0350 54.4350 0.5700 ;
+         LAYER met3 ;
+	    RECT 0.4900 24.2150 74.7000 197.9650 ;
+	    RECT 24.9000 23.2650 50.3550 24.2150 ;
+	    RECT 24.9000 20.5850 37.9800 23.2650 ;
+	    RECT 24.9000 1.6950 25.6000 20.5850 ;
+	    RECT 37.2800 1.6950 37.9800 20.5850 ;
+	    RECT 49.6550 1.6950 50.3550 23.2650 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 169.1350 75.0000 197.9650 ;
+	    RECT 0.0000 98.5050 7.7150 169.1350 ;
+	    RECT 67.5550 98.5050 75.0000 169.1350 ;
+	    RECT 0.0000 94.5500 75.0000 98.5050 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vssio_lvc_pad
+MACRO s8iom0_vssa_lvc_pad
+   CLASS PAD GROUND ;
+   FOREIGN s8iom0_vssa_lvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 51.0900 75.0000 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 46.3300 75.0000 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_lvc1
+      PORT
+         LAYER met3 ;
+	    RECT 26.0000 -0.0350 36.8800 20.1850 ;
+      END
+   END drn_lvc1
+   PIN drn_lvc2
+      PORT
+         LAYER met3 ;
+	    RECT 38.3800 -0.0350 49.2550 22.8650 ;
+      END
+   END drn_lvc2
+   PIN src_bdy_lvc1
+      PORT
+         LAYER met2 ;
+	    RECT 0.5000 -0.0350 20.4950 1.4500 ;
+      END
+   END src_bdy_lvc1
+   PIN src_bdy_lvc2
+      PORT
+         LAYER met2 ;
+	    RECT 54.7150 -0.0350 74.7000 3.6250 ;
+      END
+   END src_bdy_lvc2
+   PIN bdy2_b2b
+      PORT
+         LAYER met2 ;
+	    RECT 34.4400 -0.0350 44.4400 0.2900 ;
+      END
+   END bdy2_b2b
+   PIN vssi
+      PORT
+         LAYER met1 ;
+	    RECT 34.3350 0.4750 35.3350 0.9750 ;
+      END
+   END vssi
+   PIN vssa
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8000 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8000 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.5000 -0.0350 24.5000 34.7250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.7550 -0.0350 74.7000 34.7250 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 9.3150 100.1050 65.9550 167.5350 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 0.2400 0.9850 74.7550 197.7450 ;
+         LAYER met1 ;
+	    RECT 0.1200 1.2550 74.7850 197.8050 ;
+	    RECT 0.1200 0.1950 34.0550 1.2550 ;
+	    RECT 35.6150 0.1950 74.7850 1.2550 ;
+	    RECT 0.1200 -0.0350 74.7850 0.1950 ;
+         LAYER met2 ;
+	    RECT 0.5000 3.9050 74.7000 194.3950 ;
+	    RECT 0.5000 1.7300 54.4350 3.9050 ;
+	    RECT 20.7750 0.5700 54.4350 1.7300 ;
+	    RECT 20.7750 -0.0350 34.1600 0.5700 ;
+	    RECT 44.7200 -0.0350 54.4350 0.5700 ;
+         LAYER met3 ;
+	    RECT 0.4900 35.1250 74.7000 189.4800 ;
+	    RECT 24.9000 23.2650 50.3550 35.1250 ;
+	    RECT 24.9000 20.5850 37.9800 23.2650 ;
+	    RECT 24.9000 1.5450 25.6000 20.5850 ;
+	    RECT 37.2800 1.5450 37.9800 20.5850 ;
+	    RECT 49.6550 1.5450 50.3550 23.2650 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 169.1350 75.0000 197.9650 ;
+	    RECT 0.0000 98.5050 7.7150 169.1350 ;
+	    RECT 67.5550 98.5050 75.0000 169.1350 ;
+	    RECT 0.0000 94.5500 75.0000 98.5050 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vssa_lvc_pad
+MACRO s8iom0_vssa_hvc_pad
+   CLASS PAD GROUND ;
+   FOREIGN s8iom0_vssa_hvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 50.3900 -2.0350 74.2900 23.6250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 37.8900 -2.0350 48.8900 10.3450 ;
+      END
+   END drn_hvc
+   PIN src_bdy_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 0.4950 -2.0350 24.3950 0.0200 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 25.8950 -2.0350 36.8950 10.3900 ;
+      END
+   END src_bdy_hvc
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 6.1000 101.9750 68.8000 164.5900 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.4950 -2.0350 24.3950 30.4800 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.3900 -2.0350 74.2900 34.7250 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2050 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 74.3600 189.5650 74.3700 189.5750 ;
+      END
+   END vssio
+   OBS
+         LAYER li1 ;
+	    RECT 1.0700 -1.0350 72.7750 197.6600 ;
+         LAYER met1 ;
+	    RECT 0.1850 -1.0650 73.6200 197.6900 ;
+         LAYER met2 ;
+	    RECT 0.2650 23.9050 74.2900 193.0400 ;
+	    RECT 0.2650 0.3000 50.1100 23.9050 ;
+	    RECT 24.6750 -2.0350 50.1100 0.3000 ;
+         LAYER met3 ;
+	    RECT 0.2400 35.1250 74.2900 193.0650 ;
+	    RECT 0.2400 30.8800 49.9900 35.1250 ;
+	    RECT 24.7950 10.7900 49.9900 30.8800 ;
+	    RECT 24.7950 10.3450 25.4950 10.7900 ;
+	    RECT 37.2950 10.7450 49.9900 10.7900 ;
+	    RECT 37.2950 10.3450 37.4900 10.7450 ;
+	    RECT 49.2900 10.3450 49.9900 10.7450 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 54.4700 73.3300 55.1000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 1.6700 45.3000 73.3300 45.9300 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 166.1900 75.0000 197.9650 ;
+	    RECT 0.0000 100.3750 4.5000 166.1900 ;
+	    RECT 70.4000 100.3750 75.0000 166.1900 ;
+	    RECT 0.0000 94.5500 75.0000 100.3750 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vssa_hvc_pad
+MACRO s8iom0_vssd_hvc_pad
+   CLASS PAD GROUND ;
+   FOREIGN s8iom0_vssd_hvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 50.3900 -2.0350 74.2900 23.6250 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 37.8900 -2.0350 48.8900 10.3450 ;
+      END
+   END drn_hvc
+   PIN src_bdy_hvc
+      PORT
+         LAYER met2 ;
+	    RECT 0.4950 -2.0350 24.3950 0.0200 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 25.8950 -2.0350 36.8950 10.3900 ;
+      END
+   END src_bdy_hvc
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2050 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.2250 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 6.1000 101.9750 68.8000 164.5900 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.4950 -2.0350 24.3950 30.4800 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.3900 -2.0350 74.2900 39.5650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 1.0700 -1.0350 72.7750 197.6600 ;
+         LAYER met1 ;
+	    RECT 0.1850 -1.0650 73.6200 197.6900 ;
+         LAYER met2 ;
+	    RECT 0.2650 23.9050 74.2900 193.0400 ;
+	    RECT 0.2650 0.3000 50.1100 23.9050 ;
+	    RECT 24.6750 -2.0350 50.1100 0.3000 ;
+         LAYER met3 ;
+	    RECT 0.2400 39.9650 74.2900 193.0650 ;
+	    RECT 0.2400 30.8800 49.9900 39.9650 ;
+	    RECT 24.7950 10.7900 49.9900 30.8800 ;
+	    RECT 24.7950 10.3450 25.4950 10.7900 ;
+	    RECT 37.2950 10.7450 49.9900 10.7900 ;
+	    RECT 37.2950 10.3450 37.4900 10.7450 ;
+	    RECT 49.2900 10.3450 49.9900 10.7450 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 166.1900 75.0000 197.9650 ;
+	    RECT 0.0000 100.3750 4.5000 166.1900 ;
+	    RECT 70.4000 100.3750 75.0000 166.1900 ;
+	    RECT 0.0000 94.5500 75.0000 100.3750 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vssd_hvc_pad
+MACRO s8iom0_vssd_lvc_pad
+   CLASS PAD GROUND ;
+   FOREIGN s8iom0_vssd_lvc_pad ;
+   ORIGIN -0.0000 -0.0000 ;
+   SIZE 75.0000 BY 197.9650 ;
+   PIN amuxbus_a
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 75.0000 54.0700 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 51.0900 1.2700 54.0700 ;
+      END
+   END amuxbus_a
+   PIN amuxbus_b
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 75.0000 49.3100 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 46.3300 1.2700 49.3100 ;
+      END
+   END amuxbus_b
+   PIN drn_lvc1
+      PORT
+         LAYER met3 ;
+	    RECT 26.0000 -0.0350 36.8800 20.1850 ;
+      END
+   END drn_lvc1
+   PIN drn_lvc2
+      PORT
+         LAYER met3 ;
+	    RECT 38.3800 -0.0350 49.2550 22.8650 ;
+      END
+   END drn_lvc2
+   PIN src_bdy_lvc1
+      PORT
+         LAYER met2 ;
+	    RECT 0.5000 -0.0350 20.4950 1.4500 ;
+      END
+   END src_bdy_lvc1
+   PIN src_bdy_lvc2
+      PORT
+         LAYER met2 ;
+	    RECT 54.7150 -0.0350 74.7000 3.6250 ;
+      END
+   END src_bdy_lvc2
+   PIN bdy2_b2b
+      PORT
+         LAYER met2 ;
+	    RECT 34.4400 -0.0350 44.4400 0.2900 ;
+      END
+   END bdy2_b2b
+   PIN vssi
+      PORT
+         LAYER met1 ;
+	    RECT 34.3350 0.4750 35.3350 0.9750 ;
+      END
+   END vssi
+   PIN vssa
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 45.7000 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 34.8050 75.0000 38.0500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 45.7000 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 34.8050 1.2700 38.0500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 49.6100 75.0000 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 75.0000 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 75.0000 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 34.7000 75.0000 38.1500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 45.7000 1.2700 46.0300 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 49.6100 1.2700 50.7900 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 54.3700 1.2700 54.7000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 34.7000 1.2700 38.1500 ;
+      END
+   END vssa
+   PIN vdda
+      PORT
+         LAYER met5 ;
+	    RECT 74.0350 13.0000 75.0000 16.2500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 13.0000 0.9650 16.2500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 74.0350 12.9000 75.0000 16.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 12.9000 0.9650 16.3500 ;
+      END
+   END vdda
+   PIN vswitch
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 29.9500 75.0000 33.2000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 29.9500 1.2700 33.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 29.8500 75.0000 33.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 29.8500 1.2700 33.3000 ;
+      END
+   END vswitch
+   PIN vddio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 62.1500 75.0000 66.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 62.1500 1.2700 66.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 62.0500 75.0000 66.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 62.0500 1.2700 66.5000 ;
+      END
+   END vddio_q
+   PIN vcchib
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 0.1000 75.0000 5.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 0.1000 1.2700 5.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 0.0000 75.0000 5.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 0.0000 1.2700 5.4500 ;
+      END
+   END vcchib
+   PIN vddio
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 68.0000 75.0000 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 17.8500 75.0000 22.3000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 68.0000 1.2700 92.9500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 17.8500 1.2700 22.3000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 17.7500 75.0000 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 68.0000 75.0000 92.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 17.7500 1.2700 22.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 68.0000 1.2700 92.9650 ;
+      END
+   END vddio
+   PIN vccd
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 6.9500 75.0000 11.4000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 6.9500 1.2700 11.4000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 6.8500 75.0000 11.5000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 6.8500 1.2700 11.5000 ;
+      END
+   END vccd
+   PIN vssio
+      PORT
+         LAYER met4 ;
+	    RECT 74.2250 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2050 197.9650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 23.9000 75.0000 28.3500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 23.9000 1.2700 28.3500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 23.8000 75.0000 28.4500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 173.7500 75.0000 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 173.7500 1.2700 197.9650 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 23.8000 1.2700 28.4500 ;
+      END
+   END vssio
+   PIN vssd
+      PORT
+         LAYER met5 ;
+	    RECT 9.3150 100.1050 65.9550 167.5350 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 50.7550 -0.0350 74.7000 39.5650 ;
+      END
+      PORT
+         LAYER met3 ;
+	    RECT 0.5000 -0.0350 24.5000 39.5650 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 39.6500 75.0000 44.1000 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 39.6500 1.2700 44.1000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 39.5500 75.0000 44.2000 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 39.5500 1.2700 44.2000 ;
+      END
+   END vssd
+   PIN vssio_q
+      PORT
+         LAYER met5 ;
+	    RECT 73.7300 56.3000 75.0000 60.5500 ;
+      END
+      PORT
+         LAYER met5 ;
+	    RECT 0.0000 56.3000 1.2700 60.5500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 73.7300 56.2000 75.0000 60.6500 ;
+      END
+      PORT
+         LAYER met4 ;
+	    RECT 0.0000 56.2000 1.2700 60.6500 ;
+      END
+   END vssio_q
+   OBS
+         LAYER li1 ;
+	    RECT 0.2400 0.9850 74.7550 197.7450 ;
+         LAYER met1 ;
+	    RECT 0.1200 1.2550 74.7850 197.8050 ;
+	    RECT 0.1200 0.1950 34.0550 1.2550 ;
+	    RECT 35.6150 0.1950 74.7850 1.2550 ;
+	    RECT 0.1200 -0.0350 74.7850 0.1950 ;
+         LAYER met2 ;
+	    RECT 0.5000 3.9050 74.7000 194.3950 ;
+	    RECT 0.5000 1.7300 54.4350 3.9050 ;
+	    RECT 20.7750 0.5700 54.4350 1.7300 ;
+	    RECT 20.7750 -0.0350 34.1600 0.5700 ;
+	    RECT 44.7200 -0.0350 54.4350 0.5700 ;
+         LAYER met3 ;
+	    RECT 0.5000 39.9650 74.7000 189.4800 ;
+	    RECT 24.9000 23.2650 50.3550 39.9650 ;
+	    RECT 24.9000 20.5850 37.9800 23.2650 ;
+	    RECT 24.9000 17.7550 25.6000 20.5850 ;
+	    RECT 37.2800 17.7550 37.9800 20.5850 ;
+	    RECT 49.6550 17.7550 50.3550 23.2650 ;
+         LAYER met4 ;
+	    RECT 1.6700 173.3500 73.3300 197.9650 ;
+	    RECT 0.9650 93.3650 74.0350 173.3500 ;
+	    RECT 1.6700 67.6000 73.3300 93.3650 ;
+	    RECT 0.9650 66.9000 74.0350 67.6000 ;
+	    RECT 1.6700 61.6500 73.3300 66.9000 ;
+	    RECT 0.9650 61.0500 74.0350 61.6500 ;
+	    RECT 1.6700 55.8000 73.3300 61.0500 ;
+	    RECT 0.9650 55.1000 74.0350 55.8000 ;
+	    RECT 1.6700 49.7100 73.3300 50.6900 ;
+	    RECT 0.9650 44.6000 74.0350 45.3000 ;
+	    RECT 1.6700 39.1500 73.3300 44.6000 ;
+	    RECT 0.9650 38.5500 74.0350 39.1500 ;
+	    RECT 1.6700 34.3000 73.3300 38.5500 ;
+	    RECT 0.9650 33.7000 74.0350 34.3000 ;
+	    RECT 1.6700 29.4500 73.3300 33.7000 ;
+	    RECT 0.9650 28.8500 74.0350 29.4500 ;
+	    RECT 1.6700 23.4000 73.3300 28.8500 ;
+	    RECT 0.9650 22.8000 74.0350 23.4000 ;
+	    RECT 1.6700 17.3500 73.3300 22.8000 ;
+	    RECT 0.9650 16.7500 74.0350 17.3500 ;
+	    RECT 1.3650 12.5000 73.6350 16.7500 ;
+	    RECT 0.9650 11.9000 74.0350 12.5000 ;
+	    RECT 1.6700 6.4500 73.3300 11.9000 ;
+	    RECT 0.9650 5.8500 74.0350 6.4500 ;
+	    RECT 1.6700 0.0000 73.3300 5.8500 ;
+         LAYER met5 ;
+	    RECT 0.0000 169.1350 75.0000 197.9650 ;
+	    RECT 0.0000 98.5050 7.7150 169.1350 ;
+	    RECT 67.5550 98.5050 75.0000 169.1350 ;
+	    RECT 0.0000 94.5500 75.0000 98.5050 ;
+	    RECT 2.8700 16.2500 72.1300 94.5500 ;
+	    RECT 2.5650 13.0000 72.4350 16.2500 ;
+	    RECT 2.8700 0.1000 72.1300 13.0000 ;
+   END
+END s8iom0_vssd_lvc_pad
+END LIBRARY ;
diff --git a/sky130/custom/sky130_fd_io/mag/all_pads_test.mag b/sky130/custom/sky130_fd_io/mag/all_pads_test.mag
new file mode 100644
index 0000000..54d9f7a
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/all_pads_test.mag
@@ -0,0 +1,8491 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584383567
+<< error_s >>
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+rect 112405 45257 112455 46257
+rect 114055 45257 114105 46257
+rect 89425 44702 89751 44703
+rect 86297 44472 86383 44508
+use s8iom0_vdda_lvc_pad  s8iom0_vdda_lvc_pad_0
+timestamp 1584383356
+transform 1 0 -868 0 1 91931
+box 0 -61 15000 39593
+use s8iom0_vdda_hvc_pad  s8iom0_vdda_hvc_pad_0
+timestamp 1584383356
+transform 1 0 19686 0 1 92471
+box 0 -407 15000 39593
+use s8iom0_vccd_lvc_pad  s8iom0_vccd_lvc_pad_0
+timestamp 1584383356
+transform 1 0 38106 0 1 91155
+box 0 -61 15000 39593
+use s8iom0_vccd_hvc_pad  s8iom0_vccd_hvc_pad_0
+timestamp 1584383356
+transform 1 0 56526 0 1 91335
+box 0 -435 15000 39593
+use s8iom0_vddio_hvc_pad  s8iom0_vddio_hvc_pad_0
+timestamp 1584383356
+transform 1 0 77078 0 1 92305
+box 0 -435 15000 39593
+use s8iom0_vddio_lvc_pad  s8iom0_vddio_lvc_pad_0
+timestamp 1584383356
+transform 1 0 97048 0 1 92319
+box 0 -61 15000 39593
+use s8iom0_gpiov2_pad  s8iom0_gpiov2_pad_0
+timestamp 1584383356
+transform 1 0 119295 0 1 92724
+box -143 -466 16134 39593
+use s8iom0s8_top_xres4v2  s8iom0s8_top_xres4v2_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 140197 0 1 92452
+box -103 0 15124 40000
+use s8iom0s8_top_gpio_ovtv2  s8iom0s8_top_gpio_ovtv2_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 160920 0 1 92540
+box -80 -88 28211 40076
+use s8iom0_vssd_lvc_pad  s8iom0_vssd_lvc_pad_0
+timestamp 1584383356
+transform 1 0 -480 0 1 46173
+box 0 -61 15000 39593
+use s8iom0_vssd_hvc_pad  s8iom0_vssd_hvc_pad_0
+timestamp 1584383356
+transform 1 0 18134 0 1 46741
+box 0 -435 15000 39593
+use s8iom0_vssa_hvc_pad  s8iom0_vssa_hvc_pad_0
+timestamp 1584383356
+transform 1 0 37912 0 1 46935
+box 0 -435 15000 39593
+use s8iom0_vssa_lvc_pad  s8iom0_vssa_lvc_pad_0
+timestamp 1584383356
+transform 1 0 60016 0 1 44427
+box 0 -61 15000 39593
+use s8iom0_vssio_lvc_pad  s8iom0_vssio_lvc_pad_0
+timestamp 1584383356
+transform 1 0 79018 0 1 44233
+box 0 -61 15000 39593
+use s8iom0_vssio_hvc_pad  s8iom0_vssio_hvc_pad_0
+timestamp 1584383356
+transform 1 0 100540 0 1 44967
+box 0 -407 15000 39593
+use s8iom0_corner_pad  s8iom0_corner_pad_0
+timestamp 1584383356
+transform 1 0 123795 0 1 46420
+box -181 -114 40000 40800
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/power_pads_lib.mag b/sky130/custom/sky130_fd_io/mag/power_pads_lib.mag
new file mode 100644
index 0000000..a8876fa
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/power_pads_lib.mag
@@ -0,0 +1,65 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1585845698
+use s8iom0_vssd_lvc_pad  s8iom0_vssd_lvc_pad_0
+timestamp 1585845698
+transform 1 0 1268 0 1 -42858
+box 0 -61 15000 39593
+use s8iom0_vssd_hvc_pad  s8iom0_vssd_hvc_pad_0
+timestamp 1585845698
+transform 1 0 18322 0 1 -43322
+box 0 -435 15000 39593
+use s8iom0_vssa_hvc_pad  s8iom0_vssa_hvc_pad_0
+timestamp 1585845698
+transform 1 0 36302 0 1 -43582
+box 0 -435 15000 39593
+use s8iom0_vssa_lvc_pad  s8iom0_vssa_lvc_pad_0
+timestamp 1585845698
+transform 1 0 54022 0 1 -43956
+box 0 -61 15000 39593
+use s8iom0_vssio_lvc_pad  s8iom0_vssio_lvc_pad_0
+timestamp 1585845698
+transform 1 0 71611 0 1 -43826
+box 0 -7 15000 39593
+use s8iom0_corner_pad  s8iom0_corner_pad_0
+timestamp 1585845698
+transform 1 0 111407 0 1 -43193
+box -181 -114 40000 40800
+use s8iom0_vssio_hvc_pad  s8iom0_vssio_hvc_pad_0
+timestamp 1585845698
+transform 1 0 89461 0 1 -43192
+box 0 -407 15000 39593
+use s8iom0s8_com_bus_slice_1um  s8iom0s8_com_bus_slice_1um_0
+timestamp 1576684134
+transform 1 0 108518 0 1 -43389
+box 0 0 200 39593
+use s8iom0_vdda_lvc_pad  s8iom0_vdda_lvc_pad_0
+timestamp 1585845698
+transform 1 0 1952 0 1 -313
+box 0 -61 15000 39593
+use s8iom0_vdda_hvc_pad  s8iom0_vdda_hvc_pad_0
+timestamp 1585845698
+transform 1 0 20277 0 1 195
+box 0 -435 15000 39593
+use s8iom0_vccd_lvc_pad  s8iom0_vccd_lvc_pad_0
+timestamp 1585845698
+transform 1 0 37605 0 1 -49
+box 0 -61 15000 39593
+use s8iom0_vddio_hvc_pad  s8iom0_vddio_hvc_pad_0
+timestamp 1585845698
+transform 1 0 73415 0 1 258
+box 0 -435 15000 39593
+use s8iom0_vccd_hvc_pad  s8iom0_vccd_hvc_pad_0
+timestamp 1585845698
+transform 1 0 55455 0 1 325
+box 0 -435 15000 39593
+use s8iom0_gpiov2_pad  s8iom0_gpiov2_pad_0
+timestamp 1585845698
+transform 1 0 110622 0 1 590
+box -143 -466 16134 39593
+use s8iom0_vddio_lvc_pad  s8iom0_vddio_lvc_pad_0
+timestamp 1585845698
+transform 1 0 91354 0 1 -208
+box 0 -7 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_corner_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_corner_pad.mag
new file mode 100644
index 0000000..8da430c
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_corner_pad.mag
@@ -0,0 +1,199 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1576765820
+<< metal4 >>
+rect 0 35957 254 40800
+rect 0 14807 254 19800
+rect 0 13617 254 14507
+rect 0 12447 254 13337
+rect 0 12081 254 12147
+rect 0 11425 100 12021
+rect 0 11129 254 11365
+rect 0 10473 116 11069
+rect 0 10347 254 10413
+rect 0 9117 254 10047
+rect 0 8147 254 8837
+rect 0 7177 254 7867
+rect 0 5967 254 6897
+rect 0 4757 254 5687
+rect 0 3787 254 4477
+rect 0 2577 254 3507
+rect 0 1207 254 2297
+rect 407 0 1497 254
+rect 1777 0 2707 254
+rect 2987 0 3677 254
+rect 3957 0 4887 254
+rect 5167 0 6097 254
+rect 6377 0 7067 254
+rect 7347 0 8037 254
+rect 8317 0 9247 254
+rect 9547 0 9613 254
+rect 9673 0 10269 115
+rect 10329 0 10565 254
+rect 10625 0 11221 100
+rect 11281 0 11347 254
+rect 11647 0 12537 254
+rect 12817 0 13707 254
+rect 14007 0 19000 254
+rect 35157 0 40000 254
+<< metal5 >>
+rect 0 35957 254 40800
+rect 0 14807 254 19797
+rect 0 13637 254 14487
+rect 0 12467 254 13317
+rect 0 10347 254 12147
+rect 0 9137 254 10027
+rect 0 8167 254 8817
+rect 0 7197 254 7847
+rect 0 5987 254 6877
+rect 0 4777 254 5667
+rect 0 3807 254 4457
+rect 0 2597 254 3487
+rect 0 1227 254 2277
+rect 427 0 1477 254
+rect 1797 0 2687 254
+rect 3007 0 3657 254
+rect 3977 0 4867 254
+rect 5187 0 6077 254
+rect 6397 0 7047 254
+rect 7367 0 8017 254
+rect 8337 0 9227 254
+rect 9547 0 11347 254
+rect 11667 0 12517 254
+rect 12837 0 13687 254
+rect 14007 0 18997 254
+rect 35157 0 40000 254
+use s8iom0s8_corner_bus_overlay  s8iom0s8_corner_bus_overlay_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1576765096
+transform 1 0 0 0 1 67
+box 0 0 40000 40733
+<< labels >>
+flabel metal5 s 0 10347 254 12147 3 FreeSans 520 0 0 0 vssa
+port 2 nsew
+flabel metal5 s 127 11205 127 11205 3 FreeSans 520 180 0 0 vssa
+port 2 nsew
+flabel metal5 s 0 7197 254 7847 3 FreeSans 520 180 0 0 vswitch
+port 4 nsew
+flabel metal5 s 0 5987 254 6877 3 FreeSans 520 180 0 0 vssio
+port 9 nsew
+flabel metal5 s 0 9137 254 10027 3 FreeSans 520 180 0 0 vssd
+port 10 nsew
+flabel metal5 s 0 8168 254 8817 3 FreeSans 520 180 0 0 vssa
+port 2 nsew
+flabel metal5 s 0 12467 254 13317 3 FreeSans 520 180 0 0 vssio_q
+port 11 nsew
+flabel metal5 s 0 13637 254 14487 3 FreeSans 520 180 0 0 vddio_q
+port 5 nsew
+flabel metal5 s 0 14807 254 19797 3 FreeSans 520 180 0 0 vddio
+port 7 nsew
+flabel metal5 s 0 3807 251 4457 3 FreeSans 520 180 0 0 vdda
+port 3 nsew
+flabel metal5 s 0 1227 254 2277 3 FreeSans 520 180 0 0 vcchib
+port 6 nsew
+flabel metal5 s 0 2597 254 3487 3 FreeSans 520 180 0 0 vccd
+port 8 nsew
+flabel metal5 s 0 4777 254 5667 3 FreeSans 520 180 0 0 vddio
+port 7 nsew
+flabel metal4 s 0 11425 100 12021 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10473 115 11069 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 0 10347 254 10413 3 FreeSans 520 0 0 0 vssa
+port 2 nsew
+flabel metal4 s 0 1207 254 2297 3 FreeSans 520 180 0 0 vcchib
+port 6 nsew
+flabel metal4 s 0 2577 254 3507 3 FreeSans 520 180 0 0 vccd
+port 8 nsew
+flabel metal4 s 0 3787 251 4477 3 FreeSans 520 180 0 0 vdda
+port 3 nsew
+flabel metal4 s 0 4757 254 5687 3 FreeSans 520 180 0 0 vddio
+port 7 nsew
+flabel metal4 s 0 5967 254 6897 3 FreeSans 520 180 0 0 vssio
+port 9 nsew
+flabel metal4 s 0 7177 254 7867 3 FreeSans 520 180 0 0 vswitch
+port 4 nsew
+flabel metal4 s 0 8147 254 8837 3 FreeSans 520 180 0 0 vssa
+port 2 nsew
+flabel metal4 s 0 9117 254 10047 3 FreeSans 520 180 0 0 vssd
+port 10 nsew
+flabel metal4 s 0 11129 254 11365 3 FreeSans 520 0 0 0 vssa
+port 2 nsew
+flabel metal4 s 0 12081 254 12147 3 FreeSans 520 0 0 0 vssa
+port 2 nsew
+flabel metal4 s 0 12447 254 13337 3 FreeSans 520 180 0 0 vssio_q
+port 11 nsew
+flabel metal4 s 0 13617 254 14507 3 FreeSans 520 180 0 0 vddio_q
+port 5 nsew
+flabel metal4 s 0 14808 254 19800 3 FreeSans 520 180 0 0 vddio
+port 7 nsew
+flabel metal4 s 0 35957 254 40800 3 FreeSans 520 180 0 0 vssio
+port 9 nsew
+flabel metal4 s 127 38974 127 38974 3 FreeSans 520 180 0 0 vssio
+port 9 nsew
+flabel metal5 s 3977 0 4867 254 3 FreeSans 520 270 0 0 vddio
+port 7 nsew
+flabel metal5 s 1797 0 2687 254 3 FreeSans 520 270 0 0 vccd
+port 8 nsew
+flabel metal5 s 427 0 1477 254 3 FreeSans 520 270 0 0 vcchib
+port 6 nsew
+flabel metal5 s 3007 0 3657 251 3 FreeSans 520 270 0 0 vdda
+port 3 nsew
+flabel metal5 s 14007 0 18997 254 3 FreeSans 520 270 0 0 vddio
+port 7 nsew
+flabel metal5 s 12837 0 13687 254 3 FreeSans 520 270 0 0 vddio_q
+port 5 nsew
+flabel metal5 s 11667 0 12517 254 3 FreeSans 520 270 0 0 vssio_q
+port 11 nsew
+flabel metal5 s 7368 0 8017 254 3 FreeSans 520 270 0 0 vssa
+port 2 nsew
+flabel metal5 s 8337 0 9227 254 3 FreeSans 520 270 0 0 vssd
+port 10 nsew
+flabel metal5 s 5187 0 6077 254 3 FreeSans 520 270 0 0 vssio
+port 9 nsew
+flabel metal5 s 6397 0 7047 254 3 FreeSans 520 270 0 0 vswitch
+port 4 nsew
+flabel metal5 s 9547 0 11347 254 3 FreeSans 520 270 0 0 vssa
+port 2 nsew
+flabel metal5 s 10258 127 10258 127 3 FreeSans 520 90 0 0 vssa
+port 2 nsew
+flabel metal4 s 14008 0 19000 254 3 FreeSans 520 270 0 0 vddio
+port 7 nsew
+flabel metal4 s 12817 0 13707 254 3 FreeSans 520 270 0 0 vddio_q
+port 5 nsew
+flabel metal4 s 11647 0 12537 254 3 FreeSans 520 270 0 0 vssio_q
+port 11 nsew
+flabel metal4 s 11281 0 11347 254 3 FreeSans 520 90 0 0 vssa
+port 2 nsew
+flabel metal4 s 10329 0 10565 254 3 FreeSans 520 90 0 0 vssa
+port 2 nsew
+flabel metal4 s 8317 0 9247 254 3 FreeSans 520 270 0 0 vssd
+port 10 nsew
+flabel metal4 s 7347 0 8037 254 3 FreeSans 520 270 0 0 vssa
+port 2 nsew
+flabel metal4 s 6377 0 7067 254 3 FreeSans 520 270 0 0 vswitch
+port 4 nsew
+flabel metal4 s 5167 0 6097 254 3 FreeSans 520 270 0 0 vssio
+port 9 nsew
+flabel metal4 s 3957 0 4887 254 3 FreeSans 520 270 0 0 vddio
+port 7 nsew
+flabel metal4 s 2987 0 3677 251 3 FreeSans 520 270 0 0 vdda
+port 3 nsew
+flabel metal4 s 1777 0 2707 254 3 FreeSans 520 270 0 0 vccd
+port 8 nsew
+flabel metal4 s 407 0 1497 254 3 FreeSans 520 270 0 0 vcchib
+port 6 nsew
+flabel metal4 s 9547 0 9613 254 3 FreeSans 520 90 0 0 vssa
+port 2 nsew
+flabel metal4 s 10625 0 11221 100 3 FreeSans 520 90 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 9673 0 10269 115 3 FreeSans 520 90 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 35157 0 40000 254 3 FreeSans 520 270 0 0 vssio
+port 9 nsew
+flabel metal4 s 38174 127 38174 127 3 FreeSans 520 270 0 0 vssio
+port 9 nsew
+<< properties >>
+string LEFclass ENDCAP TOPRIGHT
+string FIXED_BBOX 0 0 40000 40800
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_gpiov2_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_gpiov2_pad.mag
new file mode 100644
index 0000000..1fea0c1
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_gpiov2_pad.mag
@@ -0,0 +1,286 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal1 >>
+rect 12486 -407 12538 -351
+<< metal2 >>
+rect 7956 15977 8019 15991
+rect 7956 15927 7969 15977
+tri 7969 15927 8019 15977 nw
+rect 675 -407 721 -361
+rect 1084 -407 1130 -328
+rect 1226 -407 1278 -355
+rect 2551 -407 2603 -363
+rect 3262 -407 3314 -306
+rect 4471 -407 4523 -340
+rect 5320 -407 5372 -379
+rect 5698 -407 5750 -355
+rect 6150 -407 6202 -351
+rect 6363 -407 6415 -363
+rect 7092 -407 7144 -351
+rect 7678 -407 7730 -318
+rect 9049 -407 9101 -355
+rect 9971 -407 10023 -355
+rect 13367 -407 13419 -355
+rect 13655 -407 13785 -363
+rect 15256 -407 15384 -363
+rect 15522 -407 15574 -363
+rect 15741 -407 15781 -363
+rect 15943 -407 15983 -215
+<< metal3 >>
+rect 80 -407 204 -244
+rect 9173 -407 9239 -355
+rect 12564 -407 12778 -260
+rect 15716 -407 15782 -254
+rect 15848 -407 15914 -244
+<< metal4 >>
+rect 0 34750 254 39593
+rect 15746 34750 16000 39593
+rect 0 13600 254 18593
+rect 15746 13600 16000 18593
+rect 0 12410 254 13300
+rect 15746 12410 16000 13300
+rect 0 11240 254 12130
+rect 15746 11240 16000 12130
+rect 0 10874 254 10940
+rect 15746 10874 16000 10940
+rect 0 10218 100 10814
+rect 15746 10218 15846 10814
+rect 0 9922 254 10158
+rect 15746 9922 16000 10158
+rect 0 9266 116 9862
+rect 15746 9266 15862 9862
+rect 0 9140 254 9206
+rect 15746 9140 16000 9206
+rect 0 7910 254 8840
+rect 15746 7910 16000 8840
+rect 0 6940 254 7630
+rect 15746 6940 16000 7630
+rect 0 5970 254 6660
+rect 15746 5970 16000 6660
+rect 0 4760 254 5690
+rect 15746 4760 16000 5690
+rect 0 3550 254 4480
+rect 15746 3550 16000 4480
+rect 0 2580 254 3270
+rect 15746 2580 16000 3270
+rect 0 1370 254 2300
+rect 15746 1370 16000 2300
+rect 0 0 254 1090
+rect 15746 0 16000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 15746 34750 16000 39593
+rect 6423 24687 10731 28996
+rect 0 13600 254 18590
+rect 15746 13600 16000 18590
+rect 0 12430 254 13280
+rect 15746 12430 16000 13280
+rect 0 11260 254 12110
+rect 15746 11260 16000 12110
+rect 0 9140 254 10940
+rect 15746 9140 16000 10940
+rect 0 7930 254 8820
+rect 15746 7930 16000 8820
+rect 0 6960 254 7610
+rect 15746 6960 16000 7610
+rect 0 5990 254 6640
+rect 15746 5990 16000 6640
+rect 0 4780 254 5670
+rect 15746 4780 16000 5670
+rect 0 3570 254 4460
+rect 15746 3570 16000 4460
+rect 0 2600 254 3250
+rect 15746 2600 16000 3250
+rect 0 1390 254 2280
+rect 15746 1390 16000 2280
+rect 0 20 254 1070
+rect 15746 20 16000 1070
+use s8iom0s8_overlay_gpiov2  s8iom0s8_overlay_gpiov2_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 407 16000 40000
+use s8iom0s8_top_gpiov2  s8iom0s8_top_gpiov2_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box -143 -7 16134 40000
+<< labels >>
+flabel metal4 s 127 37925 127 37925 3 FreeSans 520 0 0 0 vssio
+port 35 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 31 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 34 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 36 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 37 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 35 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 30 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 31 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 28 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 32 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 33 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 33 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 29 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 35 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 31 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 32 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 31 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 28 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 33 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 37 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 33 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 36 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 35 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 30 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 33 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 33 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 34 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 29 nsew
+flabel metal4 s 15873 37925 15873 37925 3 FreeSans 520 180 0 0 vssio
+port 35 nsew
+flabel metal5 s 15746 9140 16000 10940 3 FreeSans 520 180 0 0 vssa
+port 33 nsew
+flabel metal5 s 15807 2600 16000 3250 3 FreeSans 520 180 0 0 vdda
+port 30 nsew
+flabel metal5 s 15746 7930 16000 8820 3 FreeSans 520 180 0 0 vssd
+port 34 nsew
+flabel metal5 s 15746 11260 16000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 36 nsew
+flabel metal5 s 15746 4780 16000 5670 3 FreeSans 520 180 0 0 vssio
+port 35 nsew
+flabel metal5 s 15746 5990 16000 6640 3 FreeSans 520 180 0 0 vswitch
+port 37 nsew
+flabel metal5 s 15746 6961 16000 7610 3 FreeSans 520 180 0 0 vssa
+port 33 nsew
+flabel metal5 s 15746 1390 16000 2280 3 FreeSans 520 180 0 0 vccd
+port 28 nsew
+flabel metal5 s 15746 12430 16000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 32 nsew
+flabel metal5 s 15746 13600 16000 18590 3 FreeSans 520 180 0 0 vddio
+port 31 nsew
+flabel metal5 s 15746 20 16000 1070 3 FreeSans 520 180 0 0 vcchib
+port 29 nsew
+flabel metal5 s 15746 3570 16000 4460 3 FreeSans 520 180 0 0 vddio
+port 31 nsew
+flabel metal4 s 15746 7910 16000 8840 3 FreeSans 520 180 0 0 vssd
+port 34 nsew
+flabel metal4 s 15807 2580 16000 3270 3 FreeSans 520 180 0 0 vdda
+port 30 nsew
+flabel metal4 s 15746 11240 16000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 36 nsew
+flabel metal4 s 15746 4760 16000 5690 3 FreeSans 520 180 0 0 vssio
+port 35 nsew
+flabel metal4 s 15746 5970 16000 6660 3 FreeSans 520 180 0 0 vswitch
+port 37 nsew
+flabel metal4 s 15746 9922 16000 10158 3 FreeSans 520 180 0 0 vssa
+port 33 nsew
+flabel metal4 s 15746 10874 16000 10940 3 FreeSans 520 180 0 0 vssa
+port 33 nsew
+flabel metal4 s 15746 3550 16000 4480 3 FreeSans 520 180 0 0 vddio
+port 31 nsew
+flabel metal4 s 15746 9140 16000 9206 3 FreeSans 520 180 0 0 vssa
+port 33 nsew
+flabel metal4 s 15746 6940 16000 7630 3 FreeSans 520 180 0 0 vssa
+port 33 nsew
+flabel metal4 s 15746 12410 16000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 32 nsew
+flabel metal4 s 15746 1370 16000 2300 3 FreeSans 520 180 0 0 vccd
+port 28 nsew
+flabel metal4 s 15746 9266 16000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 15746 34750 16000 39593 3 FreeSans 520 180 0 0 vssio
+port 35 nsew
+flabel metal4 s 15746 10218 16000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 15746 13600 16000 18593 3 FreeSans 520 180 0 0 vddio
+port 31 nsew
+flabel metal4 s 15746 0 16000 1090 3 FreeSans 520 180 0 0 vcchib
+port 29 nsew
+flabel metal5 s 6423 24687 10731 28996 0 FreeSans 1600 0 0 0 pad
+port 21 nsew
+flabel metal3 s 80 -407 204 -244 0 FreeSans 640 0 0 0 in_h
+port 17 nsew
+flabel metal2 s 675 -407 721 -361 0 FreeSans 400 270 0 0 oe_n
+port 19 nsew
+flabel metal2 s 1084 -407 1130 -328 0 FreeSans 400 270 0 0 ib_mode_sel
+port 15 nsew
+flabel metal2 s 1226 -407 1278 -355 0 FreeSans 400 270 0 0 vtrip_sel
+port 38 nsew
+flabel metal2 s 2551 -407 2603 -363 0 FreeSans 400 270 0 0 enable_vdda_h
+port 10 nsew
+flabel metal2 s 3262 -407 3314 -306 0 FreeSans 400 270 0 0 enable_vswitch_h
+port 12 nsew
+flabel metal2 s 4471 -407 4523 -340 0 FreeSans 400 0 0 0 out
+port 20 nsew
+flabel metal2 s 5320 -407 5372 -379 0 FreeSans 400 270 0 0 hld_ovr
+port 14 nsew
+flabel metal2 s 5698 -407 5750 -355 0 FreeSans 400 270 0 0 dm<2>
+port 5 nsew
+flabel metal2 s 6150 -407 6202 -351 0 FreeSans 400 270 0 0 analog_sel
+port 4 nsew
+flabel metal2 s 6363 -407 6415 -363 0 FreeSans 400 270 0 0 hld_h_n
+port 13 nsew
+flabel metal2 s 7092 -407 7144 -351 0 FreeSans 400 270 0 0 enable_h
+port 8 nsew
+flabel metal2 s 7678 -407 7730 -318 0 FreeSans 400 270 0 0 enable_inp_h
+port 9 nsew
+flabel metal2 s 9049 -407 9101 -355 0 FreeSans 400 270 0 0 inp_dis
+port 18 nsew
+flabel metal3 s 9173 -407 9239 -355 0 FreeSans 400 270 0 0 analog_pol
+port 3 nsew
+flabel metal2 s 9971 -407 10023 -355 0 FreeSans 400 270 0 0 dm<0>
+port 7 nsew
+flabel metal1 s 12486 -407 12538 -351 0 FreeSans 400 270 0 0 analog_en
+port 2 nsew
+flabel metal2 s 13367 -407 13419 -355 0 FreeSans 400 270 0 0 dm<1>
+port 6 nsew
+flabel metal2 s 15522 -407 15574 -363 0 FreeSans 400 270 0 0 slow
+port 25 nsew
+flabel metal3 s 15848 -407 15914 -244 0 FreeSans 400 270 0 0 in
+port 16 nsew
+flabel metal3 s 12564 -407 12778 -260 0 FreeSans 400 270 0 0 pad_a_noesd_h
+port 24 nsew
+flabel metal2 s 13655 -407 13785 -363 0 FreeSans 400 270 0 0 pad_a_esd_1_h
+port 23 nsew
+flabel metal2 s 15256 -407 15384 -363 0 FreeSans 400 270 0 0 pad_a_esd_0_h
+port 22 nsew
+flabel metal2 s 15943 -407 15983 -215 0 FreeSans 400 270 0 0 tie_lo_esd
+port 27 nsew
+flabel metal2 s 15741 -407 15781 -363 0 FreeSans 400 270 0 0 tie_hi_esd
+port 26 nsew
+flabel metal3 s 15716 -407 15782 -254 0 FreeSans 400 270 0 0 enable_vddio
+port 11 nsew
+<< properties >>
+string LEFclass PAD INOUT
+string FIXED_BBOX 0 0 16000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vccd_hvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vccd_hvc_pad.mag
new file mode 100644
index 0000000..1e654d6
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vccd_hvc_pad.mag
@@ -0,0 +1,223 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1585845698
+<< metal2 >>
+rect 99 -407 4879 -259
+rect 5179 -407 5579 -193
+rect 10078 -407 14858 -259
+<< metal3 >>
+rect 99 -407 4879 -16
+rect 5179 -407 7379 -259
+rect 7578 -407 9778 -89
+rect 10078 -407 14858 -16
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 7329 27458 7594 28780
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vccd_hvc  s8iom0s8_overlay_vccd_hvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1585749841
+transform 1 0 0 0 1 -407
+box 0 407 15000 40000
+use s8iom0s8_top_power_hvc_wpad  s8iom0s8_top_power_hvc_wpad_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1585749839
+transform 1 0 0 0 1 -407
+box 0 0 15000 40000
+<< labels >>
+flabel metal5 s 7329 27458 7594 28780 0 FreeSans 2000 0 0 0 vccd
+port 11 nsew
+flabel metal4 s 127 37914 127 37914 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 14873 37914 14873 37914 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal2 s 10078 -407 14858 -259 2 FreeSans 2000 90 0 0 drn_hvc
+port 2 nsew
+flabel metal2 s 99 -407 4879 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal3 s 7578 -407 9778 -89 0 FreeSans 2000 0 0 0 drn_hvc
+port 2 nsew
+flabel metal3 s 10078 -407 14858 -16 0 FreeSans 2000 0 0 0 vccd
+port 11 nsew
+flabel metal3 s 99 -407 4879 -16 0 FreeSans 2000 0 0 0 vccd
+port 11 nsew
+flabel metal3 s 5179 -407 7379 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD POWER
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vccd_lvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vccd_lvc_pad.mag
new file mode 100644
index 0000000..c3127e9
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vccd_lvc_pad.mag
@@ -0,0 +1,230 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal1 >>
+rect 6867 95 7067 195
+rect 5242 -7 5540 69
+<< metal2 >>
+rect 98 0 4099 287
+rect 6888 -7 8888 58
+rect 10953 -7 14940 715
+<< metal3 >>
+rect 98 0 4900 862
+rect 5200 -7 7374 918
+rect 7676 -7 9850 918
+rect 10151 -7 14940 862
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 6339 32546 10468 33417
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vccd_lvc  s8iom0s8_overlay_vccd_lvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 7 15000 39600
+use s8iom0s8_top_power_lvc_wpad  s8iom0s8_top_power_lvc_wpad_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 0 15000 39600
+<< labels >>
+flabel metal4 s 14873 37925 14873 37925 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 127 37925 127 37925 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 6339 32546 10468 33417 0 FreeSans 2000 0 0 0 vccd
+port 15 nsew
+flabel metal2 s 100 -7 4099 287 0 FreeSans 2000 0 0 0 src_bdy_lvc1
+port 4 nsew
+flabel metal2 s 10953 -7 14940 715 0 FreeSans 2000 0 0 0 src_bdy_lvc2
+port 5 nsew
+flabel metal2 s 6888 -7 8888 58 0 FreeSans 400 0 0 0 bdy2_b2b
+port 6 nsew
+flabel metal3 s 7676 -7 9850 918 0 FreeSans 2000 0 0 0 drn_lvc2
+port 3 nsew
+flabel metal3 s 5200 -7 7374 918 0 FreeSans 2000 0 0 0 drn_lvc1
+port 2 nsew
+flabel metal3 s 10151 -7 14940 862 0 FreeSans 4000 0 0 0 vccd
+port 15 nsew
+flabel metal3 s 100 -7 4900 862 0 FreeSans 2000 0 0 0 vccd
+port 15 nsew
+flabel metal1 s 6867 95 7067 195 0 FreeSans 300 0 0 0 vssi
+port 7 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD POWER
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vdda_hvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vdda_hvc_pad.mag
new file mode 100644
index 0000000..b81c352
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vdda_hvc_pad.mag
@@ -0,0 +1,227 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal2 >>
+rect 99 -407 4879 -259
+rect 5179 -407 5579 -211
+rect 10078 -407 14858 -259
+<< metal3 >>
+rect 99 -407 4879 -16
+rect 5179 -407 7379 -259
+rect 7578 -407 9778 -89
+rect 10078 -407 14858 -16
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 7329 27458 7594 28780
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vccd_lvc  s8iom0s8_overlay_vccd_lvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 7 15000 39600
+use s8iom0s8_top_power_hvc_wpad  s8iom0s8_top_power_hvc_wpad_1 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 0 15000 40000
+<< labels >>
+flabel metal4 s 14873 37925 14873 37925 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 127 37925 127 37925 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal5 s 7329 27458 7594 28780 0 FreeSans 2000 0 0 0 vdda
+port 6 nsew
+flabel metal4 s 127 37914 127 37914 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 14873 37914 14873 37914 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal2 s 10078 -407 14858 -259 2 FreeSans 2000 90 0 0 drn_hvc
+port 2 nsew
+flabel metal2 s 99 -407 4879 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal3 s 7578 -407 9778 -89 0 FreeSans 2000 0 0 0 drn_hvc
+port 2 nsew
+flabel metal3 s 10078 -407 14858 -16 0 FreeSans 2000 0 0 0 vdda
+port 6 nsew
+flabel metal3 s 99 -407 4879 -16 0 FreeSans 2000 0 0 0 vdda
+port 6 nsew
+flabel metal3 s 5179 -407 7379 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD POWER
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vdda_lvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vdda_lvc_pad.mag
new file mode 100644
index 0000000..6cd80a1
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vdda_lvc_pad.mag
@@ -0,0 +1,226 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal1 >>
+rect 6867 95 7067 195
+rect 5242 -7 5540 61
+<< metal2 >>
+rect 98 0 4099 287
+rect 6888 -7 8888 58
+rect 10953 -7 14940 715
+<< metal3 >>
+rect 98 0 4900 862
+rect 5200 -7 7374 918
+rect 7676 -7 9850 918
+rect 10151 -7 14940 862
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 6339 32546 10467 33417
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vdda_lvc  s8iom0s8_overlay_vdda_lvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 7 15000 39600
+use s8iom0s8_top_power_lvc_wpad  s8iom0s8_top_power_lvc_wpad_1 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 0 15000 39600
+<< labels >>
+flabel metal2 s 100 -7 4099 287 0 FreeSans 2000 0 0 0 src_bdy_lvc1
+port 4 nsew
+flabel metal2 s 10953 -7 14940 715 0 FreeSans 2000 0 0 0 src_bdy_lvc2
+port 5 nsew
+flabel metal2 s 6888 -7 8888 58 0 FreeSans 400 0 0 0 bdy2_b2b
+port 6 nsew
+flabel metal3 s 7676 -7 9850 918 0 FreeSans 2000 0 0 0 drn_lvc2
+port 3 nsew
+flabel metal3 s 5200 -7 7374 918 0 FreeSans 2000 0 0 0 drn_lvc1
+port 2 nsew
+flabel metal3 s 10151 -7 14940 862 0 FreeSans 4000 0 0 0 vdda
+port 10 nsew
+flabel metal3 s 100 -7 4900 862 0 FreeSans 2000 0 0 0 vdda
+port 10 nsew
+flabel metal1 s 6867 95 7067 195 0 FreeSans 300 0 0 0 vssi
+port 7 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+flabel metal5 s 6339 32546 10468 33417 0 FreeSans 2000 0 0 0 vdda
+port 10 nsew
+<< properties >>
+string LEFclass PAD POWER
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vddio_hvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vddio_hvc_pad.mag
new file mode 100644
index 0000000..2f50667
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vddio_hvc_pad.mag
@@ -0,0 +1,223 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1585845698
+<< metal2 >>
+rect 99 -407 4879 -259
+rect 5179 -407 5579 -210
+rect 10078 -407 14858 -259
+<< metal3 >>
+rect 99 -407 4879 -16
+rect 5179 -407 7379 -259
+rect 7578 -407 9778 -89
+rect 10078 -407 14858 -16
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 7329 27458 7594 28780
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vddio_hvc  s8iom0s8_overlay_vddio_hvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1585749841
+transform 1 0 0 0 1 -407
+box 0 407 15000 40000
+use s8iom0s8_top_power_hvc_wpad  s8iom0s8_top_power_hvc_wpad_2 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1585749839
+transform 1 0 0 0 1 -407
+box 0 0 15000 40000
+<< labels >>
+flabel metal5 s 7329 27458 7594 28780 0 FreeSans 2000 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 127 37914 127 37914 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 14873 37914 14873 37914 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal2 s 10078 -407 14858 -259 2 FreeSans 2000 90 0 0 drn_hvc
+port 2 nsew
+flabel metal2 s 99 -407 4879 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal3 s 7578 -407 9778 -89 0 FreeSans 2000 0 0 0 drn_hvc
+port 2 nsew
+flabel metal3 s 10078 -407 14858 -16 0 FreeSans 2000 0 0 0 vddio
+port 10 nsew
+flabel metal3 s 99 -407 4879 -16 0 FreeSans 2000 0 0 0 vddio
+port 10 nsew
+flabel metal3 s 5179 -407 7379 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD POWER
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vddio_lvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vddio_lvc_pad.mag
new file mode 100644
index 0000000..d2e943c
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vddio_lvc_pad.mag
@@ -0,0 +1,225 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal1 >>
+rect 6867 95 7067 195
+rect 5242 -7 5540 78
+<< metal2 >>
+rect 98 0 4099 287
+rect 6888 -7 8888 58
+rect 10953 -7 14940 715
+<< metal3 >>
+rect 98 0 4900 862
+rect 5200 -7 7374 918
+rect 7676 -7 9850 918
+rect 10151 -7 14940 862
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vddio_lvc  s8iom0s8_overlay_vddio_lvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 7 15000 39600
+use s8iom0s8_top_power_lvc_wpad  s8iom0s8_top_power_lvc_wpad_2 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 0 15000 39600
+<< labels >>
+flabel metal5 s 6339 32546 10468 33417 0 FreeSans 2000 0 0 0 vddio
+port 14 nsew
+flabel metal2 s 100 -7 4099 287 0 FreeSans 2000 0 0 0 src_bdy_lvc1
+port 4 nsew
+flabel metal2 s 10953 -7 14940 715 0 FreeSans 2000 0 0 0 src_bdy_lvc2
+port 5 nsew
+flabel metal2 s 6888 -7 8888 58 0 FreeSans 400 0 0 0 bdy2_b2b
+port 6 nsew
+flabel metal3 s 7676 -7 9850 918 0 FreeSans 2000 0 0 0 drn_lvc2
+port 3 nsew
+flabel metal3 s 5200 -7 7374 918 0 FreeSans 2000 0 0 0 drn_lvc1
+port 2 nsew
+flabel metal3 s 10151 -7 14940 862 0 FreeSans 4000 0 0 0 vddio
+port 14 nsew
+flabel metal3 s 100 -7 4900 862 0 FreeSans 2000 0 0 0 vddio
+port 14 nsew
+flabel metal1 s 6867 95 7067 195 0 FreeSans 300 0 0 0 vssi
+port 7 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD POWER
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vssa_hvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vssa_hvc_pad.mag
new file mode 100644
index 0000000..dc6ca8d
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vssa_hvc_pad.mag
@@ -0,0 +1,225 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal2 >>
+rect 99 -407 4879 -259
+rect 5179 -407 5579 -184
+rect 10078 -407 14858 -259
+<< metal3 >>
+rect 99 -407 4879 -16
+rect 5179 -407 7379 -259
+rect 7578 -407 9778 -89
+rect 10078 -407 14858 -16
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 6 15000 1090
+rect 14746 0 14928 6
+rect 14939 3 15000 6
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 7329 27458 7594 28780
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vssa_hvc  s8iom0s8_overlay_vssa_hvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 407 15000 40000
+use s8iom0s8_top_ground_hvc_wpad  s8iom0s8_top_ground_hvc_wpad_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 0 15000 40000
+<< labels >>
+flabel metal5 s 7329 27458 7594 28780 0 FreeSans 2000 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 127 37914 127 37914 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 14873 37914 14873 37914 3 FreeSans 520 180 0 0 vssio
+port 15 nsew
+flabel metal2 s 10078 -407 14858 -259 2 FreeSans 2000 90 0 0 drn_hvc
+port 2 nsew
+flabel metal2 s 99 -407 4879 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal3 s 7578 -407 9778 -89 0 FreeSans 2000 0 0 0 drn_hvc
+port 2 nsew
+flabel metal3 s 99 -407 4879 -16 0 FreeSans 2000 0 0 0 vssa
+port 5 nsew
+flabel metal3 s 10078 -407 14858 -16 0 FreeSans 2000 0 0 0 vssa
+port 5 nsew
+flabel metal3 s 5179 -407 7379 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD GROUND
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vssa_lvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vssa_lvc_pad.mag
new file mode 100644
index 0000000..c832fc1
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vssa_lvc_pad.mag
@@ -0,0 +1,227 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal1 >>
+rect 6867 95 7067 195
+rect 5242 -7 5540 84
+<< metal2 >>
+rect 100 0 4099 287
+rect 6888 -7 8888 58
+rect 10953 -7 14940 715
+<< metal3 >>
+rect 98 309 4900 862
+rect 100 0 4900 309
+rect 5200 -7 7374 918
+rect 7676 -7 9850 918
+rect 10151 -7 14940 862
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 6339 32546 10468 33417
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vssa_lvc  s8iom0s8_overlay_vssa_lvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 7 15000 39600
+use s8iom0s8_top_ground_lvc_wpad  s8iom0s8_top_ground_lvc_wpad_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 0 15000 39600
+<< labels >>
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal1 s 6867 95 7067 195 0 FreeSans 300 0 0 0 vssi
+port 7 nsew
+flabel metal3 s 100 -7 4900 862 0 FreeSans 2000 0 0 0 vssa
+port 9 nsew
+flabel metal3 s 10151 -7 14940 862 0 FreeSans 4000 0 0 0 vssa
+port 9 nsew
+flabel metal3 s 5200 -7 7374 918 0 FreeSans 2000 0 0 0 drn_lvc1
+port 2 nsew
+flabel metal3 s 7676 -7 9850 918 0 FreeSans 2000 0 0 0 drn_lvc2
+port 3 nsew
+flabel metal2 s 6888 -7 8888 58 0 FreeSans 400 0 0 0 bdy2_b2b
+port 6 nsew
+flabel metal2 s 10953 -7 14940 715 0 FreeSans 2000 0 0 0 src_bdy_lvc2
+port 5 nsew
+flabel metal2 s 100 -7 4099 287 0 FreeSans 2000 0 0 0 src_bdy_lvc1
+port 4 nsew
+flabel metal5 s 6339 32546 10468 33417 0 FreeSans 2000 0 0 0 vssa
+port 9 nsew
+<< properties >>
+string LEFclass PAD GROUND
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vssd_hvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vssd_hvc_pad.mag
new file mode 100644
index 0000000..108c5f7
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vssd_hvc_pad.mag
@@ -0,0 +1,223 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal2 >>
+rect 99 -407 4879 -259
+rect 5179 -407 5579 -182
+rect 10078 -407 14858 -259
+<< metal3 >>
+rect 99 -407 4879 -16
+rect 5179 -407 7379 -259
+rect 7578 -407 9778 -89
+rect 10078 -407 14858 -16
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 7329 27458 7594 28780
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vssd_hvc  s8iom0s8_overlay_vssd_hvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 407 15000 40000
+use s8iom0s8_top_ground_hvc_wpad  s8iom0s8_top_ground_hvc_wpad_1 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 0 15000 40000
+<< labels >>
+flabel metal5 s 7329 27458 7594 28780 0 FreeSans 2000 0 0 0 vssd
+port 13 nsew
+flabel metal4 s 127 37914 127 37914 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 14873 37914 14873 37914 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal2 s 10078 -407 14858 -259 2 FreeSans 2000 90 0 0 drn_hvc
+port 2 nsew
+flabel metal2 s 99 -407 4879 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal3 s 7578 -407 9778 -89 0 FreeSans 2000 0 0 0 drn_hvc
+port 2 nsew
+flabel metal3 s 99 -407 4879 -16 0 FreeSans 2000 0 0 0 vssd
+port 13 nsew
+flabel metal3 s 10078 -407 14858 -16 0 FreeSans 2000 0 0 0 vssd
+port 13 nsew
+flabel metal3 s 5179 -407 7379 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD GROUND
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vssd_lvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vssd_lvc_pad.mag
new file mode 100644
index 0000000..7781fa8
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vssd_lvc_pad.mag
@@ -0,0 +1,230 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal1 >>
+rect 6867 95 7067 195
+rect 5242 -7 5540 83
+<< metal2 >>
+rect 101 0 4099 287
+rect 6888 -7 8888 58
+rect 10953 -7 14940 715
+<< metal3 >>
+rect 101 0 4900 862
+rect 5200 -7 7374 918
+rect 7676 -7 9850 918
+rect 10151 -7 14940 862
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 6339 32546 10468 33417
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vssd_lvc  s8iom0s8_overlay_vssd_lvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 7 15000 39600
+use s8iom0s8_top_ground_lvc_wpad  s8iom0s8_top_ground_lvc_wpad_1 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 0 15000 39600
+<< labels >>
+flabel metal4 s 14873 37925 14873 37925 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 127 37925 127 37925 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 6339 32546 10468 33417 0 FreeSans 2000 0 0 0 vssd
+port 17 nsew
+flabel metal2 s 100 -7 4099 287 0 FreeSans 2000 0 0 0 src_bdy_lvc1
+port 4 nsew
+flabel metal2 s 10953 -7 14940 715 0 FreeSans 2000 0 0 0 src_bdy_lvc2
+port 5 nsew
+flabel metal2 s 6888 -7 8888 58 0 FreeSans 400 0 0 0 bdy2_b2b
+port 6 nsew
+flabel metal3 s 7676 -7 9850 918 0 FreeSans 2000 0 0 0 drn_lvc2
+port 3 nsew
+flabel metal3 s 5200 -7 7374 918 0 FreeSans 2000 0 0 0 drn_lvc1
+port 2 nsew
+flabel metal3 s 10151 -7 14940 862 0 FreeSans 4000 0 0 0 vssd
+port 17 nsew
+flabel metal3 s 100 -7 4900 862 0 FreeSans 2000 0 0 0 vssd
+port 17 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+flabel metal1 s 6867 95 7067 195 0 FreeSans 300 0 0 0 vssi
+port 7 nsew
+<< properties >>
+string LEFclass PAD GROUND
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vssio_hvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vssio_hvc_pad.mag
new file mode 100644
index 0000000..db38a6c
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vssio_hvc_pad.mag
@@ -0,0 +1,226 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal2 >>
+rect 99 -407 4879 -259
+rect 5179 -407 5579 -181
+rect 10078 -407 14858 -259
+<< metal3 >>
+rect 99 -407 4879 -16
+rect 5179 -407 7379 -259
+rect 7578 -407 9778 -89
+rect 10078 -407 14858 -16
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 6 254 1090
+rect 14746 6 15000 1090
+rect 14934 5 15000 6
+rect 0 0 254 5
+rect 14746 0 15000 5
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 7329 27458 7594 28780
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vssio_hvc  s8iom0s8_overlay_vssio_hvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 407 15000 40000
+use s8iom0s8_top_ground_hvc_wpad  s8iom0s8_top_ground_hvc_wpad_2 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -407
+box 0 0 15000 40000
+<< labels >>
+flabel metal5 s 7329 27458 7594 28780 0 FreeSans 2000 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 127 37914 127 37914 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 14873 37914 14873 37914 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal2 s 10078 -407 14858 -259 2 FreeSans 2000 90 0 0 drn_hvc
+port 2 nsew
+flabel metal2 s 99 -407 4879 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal3 s 7578 -407 9778 -89 0 FreeSans 2000 0 0 0 drn_hvc
+port 2 nsew
+flabel metal3 s 99 -407 4879 -16 0 FreeSans 2000 0 0 0 vssio
+port 12 nsew
+flabel metal3 s 10078 -407 14858 -16 0 FreeSans 2000 0 0 0 vssio
+port 12 nsew
+flabel metal3 s 5179 -407 7379 -259 2 FreeSans 2000 90 0 0 src_bdy_hvc
+port 4 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 13 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 6 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 7 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 9 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 5 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 11 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 12 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 8 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 10 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 11 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 7 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 9 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 14 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 12 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 6 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 5 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 13 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD GROUND
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0_vssio_lvc_pad.mag b/sky130/custom/sky130_fd_io/mag/s8iom0_vssio_lvc_pad.mag
new file mode 100644
index 0000000..b467e36
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0_vssio_lvc_pad.mag
@@ -0,0 +1,227 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1584473789
+<< metal1 >>
+rect 6867 95 7067 195
+rect 5242 -7 5540 74
+<< metal2 >>
+rect 100 0 4099 287
+rect 6888 -7 8888 58
+rect 10953 -7 14940 715
+<< metal3 >>
+rect 98 339 4900 862
+rect 100 0 4900 339
+rect 5200 -7 7374 918
+rect 7676 -7 9850 918
+rect 10151 -7 14940 862
+<< metal4 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 0 13600 254 18593
+rect 14746 13600 15000 18593
+rect 0 12410 254 13300
+rect 14746 12410 15000 13300
+rect 0 11240 254 12130
+rect 14746 11240 15000 12130
+rect 0 10874 254 10940
+rect 14746 10874 15000 10940
+rect 0 10218 100 10814
+rect 14746 10218 14846 10814
+rect 0 9922 254 10158
+rect 14746 9922 15000 10158
+rect 0 9266 116 9862
+rect 14746 9266 14862 9862
+rect 0 9140 254 9206
+rect 14746 9140 15000 9206
+rect 0 7910 254 8840
+rect 14746 7910 15000 8840
+rect 0 6940 254 7630
+rect 14746 6940 15000 7630
+rect 0 5970 254 6660
+rect 14746 5970 15000 6660
+rect 0 4760 254 5690
+rect 14746 4760 15000 5690
+rect 0 3550 254 4480
+rect 14746 3550 15000 4480
+rect 0 2580 254 3270
+rect 14746 2580 15000 3270
+rect 0 1370 254 2300
+rect 14746 1370 15000 2300
+rect 0 0 254 1090
+rect 14746 0 15000 1090
+<< metal5 >>
+rect 0 34750 254 39593
+rect 14746 34750 15000 39593
+rect 6339 32546 10468 33417
+rect 0 13600 254 18590
+rect 14746 13600 15000 18590
+rect 0 12430 254 13280
+rect 14746 12430 15000 13280
+rect 0 11260 254 12110
+rect 14746 11260 15000 12110
+rect 0 9140 254 10940
+rect 14746 9140 15000 10940
+rect 0 7930 254 8820
+rect 14746 7930 15000 8820
+rect 0 6960 254 7610
+rect 14746 6960 15000 7610
+rect 0 5990 254 6640
+rect 14746 5990 15000 6640
+rect 0 4780 254 5670
+rect 14746 4780 15000 5670
+rect 0 3570 254 4460
+rect 14746 3570 15000 4460
+rect 0 2600 254 3250
+rect 14746 2600 15000 3250
+rect 0 1390 254 2280
+rect 14746 1390 15000 2280
+rect 0 20 254 1070
+rect 14746 20 15000 1070
+use s8iom0s8_overlay_vssio_lvc  s8iom0s8_overlay_vssio_lvc_0 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 7 15000 39600
+use s8iom0s8_top_ground_lvc_wpad  s8iom0s8_top_ground_lvc_wpad_2 ~/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/mag
+timestamp 1584046481
+transform 1 0 0 0 1 -7
+box 0 0 15000 39600
+<< labels >>
+flabel metal5 s 6339 32546 10468 33417 0 FreeSans 2000 0 0 0 vssio
+port 16 nsew
+flabel metal2 s 100 -7 4099 287 0 FreeSans 2000 0 0 0 src_bdy_lvc1
+port 4 nsew
+flabel metal2 s 10953 -7 14940 715 0 FreeSans 2000 0 0 0 src_bdy_lvc2
+port 5 nsew
+flabel metal2 s 6888 -7 8888 58 0 FreeSans 400 0 0 0 bdy2_b2b
+port 6 nsew
+flabel metal3 s 7676 -7 9850 918 0 FreeSans 2000 0 0 0 drn_lvc2
+port 3 nsew
+flabel metal3 s 5200 -7 7374 918 0 FreeSans 2000 0 0 0 drn_lvc1
+port 2 nsew
+flabel metal3 s 10151 -7 14940 862 0 FreeSans 4000 0 0 0 vssio
+port 16 nsew
+flabel metal3 s 100 -7 4900 862 0 FreeSans 2000 0 0 0 vssio
+port 16 nsew
+flabel metal1 s 6867 95 7067 195 0 FreeSans 300 0 0 0 vssi
+port 7 nsew
+flabel metal5 s 14746 9140 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14807 2600 15000 3250 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal5 s 14746 7930 15000 8820 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal5 s 14746 11260 15000 12110 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 14746 4780 15000 5670 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal5 s 14746 5990 15000 6640 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal5 s 14746 6961 15000 7610 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal5 s 14746 1390 15000 2280 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal5 s 14746 12430 15000 13280 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 14746 13600 15000 18590 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 14746 20 15000 1070 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal5 s 14746 3570 15000 4460 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 13600 254 18590 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 7930 254 8820 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal5 s 0 11260 254 12110 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal5 s 0 5990 254 6640 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal5 s 0 4780 254 5670 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal5 s 0 2600 193 3250 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal5 s 0 3570 254 4460 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal5 s 0 1390 254 2280 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal5 s 0 12430 254 13280 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal5 s 0 9140 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 6961 254 7610 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal5 s 0 20 254 1070 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 7910 15000 8840 3 FreeSans 520 180 0 0 vssd
+port 17 nsew
+flabel metal4 s 14807 2580 15000 3270 3 FreeSans 520 180 0 0 vdda
+port 10 nsew
+flabel metal4 s 14746 11240 15000 12130 3 FreeSans 520 180 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 14746 4760 15000 5690 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 5970 15000 6660 3 FreeSans 520 180 0 0 vswitch
+port 11 nsew
+flabel metal4 s 14746 9922 15000 10158 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 10874 15000 10940 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 0 15000 1090 3 FreeSans 520 180 0 0 vcchib
+port 13 nsew
+flabel metal4 s 14746 3550 15000 4480 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 14746 9140 15000 9206 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 6940 15000 7630 3 FreeSans 520 180 0 0 vssa
+port 9 nsew
+flabel metal4 s 14746 12410 15000 13300 3 FreeSans 520 180 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 14746 1370 15000 2300 3 FreeSans 520 180 0 0 vccd
+port 15 nsew
+flabel metal4 s 14746 9266 15000 9862 3 FreeSans 520 180 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 14746 34750 15000 39593 3 FreeSans 520 180 0 0 vssio
+port 16 nsew
+flabel metal4 s 14746 10218 15000 10814 3 FreeSans 520 180 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 14746 13600 15000 18593 3 FreeSans 520 180 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 34750 254 39593 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 3550 254 4480 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 12410 254 13300 3 FreeSans 520 0 0 0 vddio_q
+port 12 nsew
+flabel metal4 s 0 13600 254 18593 3 FreeSans 520 0 0 0 vddio
+port 14 nsew
+flabel metal4 s 0 1370 254 2300 3 FreeSans 520 0 0 0 vccd
+port 15 nsew
+flabel metal4 s 0 9140 254 9206 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 5970 254 6660 3 FreeSans 520 0 0 0 vswitch
+port 11 nsew
+flabel metal4 s 0 0 254 1090 3 FreeSans 520 0 0 0 vcchib
+port 13 nsew
+flabel metal4 s 0 9922 254 10158 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 11240 254 12130 3 FreeSans 520 0 0 0 vssio_q
+port 18 nsew
+flabel metal4 s 0 4760 254 5690 3 FreeSans 520 0 0 0 vssio
+port 16 nsew
+flabel metal4 s 0 2580 193 3270 3 FreeSans 520 0 0 0 vdda
+port 10 nsew
+flabel metal4 s 0 10218 254 10814 3 FreeSans 520 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 10874 254 10940 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 6940 254 7630 3 FreeSans 520 0 0 0 vssa
+port 9 nsew
+flabel metal4 s 0 7910 254 8840 3 FreeSans 520 0 0 0 vssd
+port 17 nsew
+flabel metal4 s 0 9266 254 9862 3 FreeSans 520 0 0 0 amuxbus_b
+port 1 nsew
+<< properties >>
+string LEFclass PAD GROUND
+string FIXED_BBOX 0 0 15000 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/s8iom0s8_com_bus_slice_1um.mag b/sky130/custom/sky130_fd_io/mag/s8iom0s8_com_bus_slice_1um.mag
new file mode 100644
index 0000000..2349822
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/s8iom0s8_com_bus_slice_1um.mag
@@ -0,0 +1,99 @@
+magic
+tech EFS8A
+magscale 1 2
+timestamp 1586352185
+<< metal4 >>
+rect 0 34750 200 39593
+rect 0 13600 200 18593
+rect 0 12410 200 13300
+rect 0 11240 200 12130
+rect 0 10874 200 10940
+rect 0 10218 200 10814
+rect 0 9922 200 10158
+rect 0 9266 200 9862
+rect 0 9140 200 9206
+rect 0 7910 200 8840
+rect 0 6940 200 7630
+rect 0 5970 200 6660
+rect 0 4760 200 5690
+rect 0 3550 200 4480
+rect 0 2580 200 3270
+rect 0 1370 200 2300
+rect 0 0 200 1090
+<< metal5 >>
+rect 0 34750 200 39593
+rect 0 13600 200 18590
+rect 0 12430 200 13280
+rect 0 11260 200 12110
+rect 0 9140 200 10940
+rect 0 7930 200 8820
+rect 0 6960 200 7610
+rect 0 5990 200 6640
+rect 0 4780 200 5670
+rect 0 3570 200 4460
+rect 0 2600 200 3250
+rect 0 1390 200 2280
+rect 0 20 200 1070
+<< labels >>
+flabel metal4 s 0 13600 200 18593 0 FreeSans 640 0 0 0 vddio
+port 7 nsew
+flabel metal5 s 0 12430 200 13280 0 FreeSans 640 0 0 0 vddio_q
+port 5 nsew
+flabel metal4 s 0 12410 200 13300 0 FreeSans 640 0 0 0 vddio_q
+port 5 nsew
+flabel metal5 s 0 11260 200 12110 0 FreeSans 640 0 0 0 vssio_q
+port 11 nsew
+flabel metal4 s 0 11240 200 12130 0 FreeSans 640 0 0 0 vssio_q
+port 11 nsew
+flabel metal5 s 0 9140 200 10940 0 FreeSans 640 0 0 0 vssa
+port 2 nsew
+flabel metal4 s 0 10874 200 10940 0 FreeSans 640 0 0 0 vssa
+port 2 nsew
+flabel metal4 s 0 10218 200 10814 0 FreeSans 640 0 0 0 amuxbus_a
+port 0 nsew
+flabel metal4 s 0 9266 200 9862 0 FreeSans 640 0 0 0 amuxbus_b
+port 1 nsew
+flabel metal4 s 0 9140 200 9206 0 FreeSans 640 0 0 0 vssa
+port 2 nsew
+flabel metal5 s 0 7930 200 8820 0 FreeSans 640 0 0 0 vssd
+port 10 nsew
+flabel metal4 s 0 7910 200 8840 0 FreeSans 640 0 0 0 vssd
+port 10 nsew
+flabel metal5 s 0 6960 200 7610 0 FreeSans 640 0 0 0 vssa
+port 2 nsew
+flabel metal4 s 0 6940 200 7630 0 FreeSans 640 0 0 0 vssa
+port 2 nsew
+flabel metal5 s 0 5990 200 6640 0 FreeSans 640 0 0 0 vswitch
+port 4 nsew
+flabel metal4 s 0 5970 200 6660 0 FreeSans 640 0 0 0 vswitch
+port 4 nsew
+flabel metal5 s 0 4780 200 5670 0 FreeSans 640 0 0 0 vssio
+port 9 nsew
+flabel metal4 s 0 4760 200 5690 0 FreeSans 640 0 0 0 vssio
+port 9 nsew
+flabel metal5 s 0 3570 200 4460 0 FreeSans 640 0 0 0 vddio
+port 7 nsew
+flabel metal4 s 0 3550 200 4480 0 FreeSans 640 0 0 0 vddio
+port 7 nsew
+flabel metal5 s 0 2600 200 3250 0 FreeSans 640 0 0 0 vdda
+port 3 nsew
+flabel metal4 s 0 2580 200 3270 0 FreeSans 640 0 0 0 vdda
+port 3 nsew
+flabel metal5 s 0 1390 200 2280 0 FreeSans 640 0 0 0 vccd
+port 8 nsew
+flabel metal4 s 0 1370 200 2300 0 FreeSans 640 0 0 0 vccd
+port 8 nsew
+flabel metal5 s 0 20 200 1070 0 FreeSans 640 0 0 0 vcchib
+port 6 nsew
+flabel metal4 s 0 0 200 1090 0 FreeSans 640 0 0 0 vcchib
+port 6 nsew
+flabel metal5 s 0 34750 200 39593 0 FreeSans 640 0 0 0 vssio
+port 9 nsew
+flabel metal5 s 0 13600 200 18590 0 FreeSans 640 0 0 0 vddio
+port 7 nsew
+flabel metal4 s 0 9922 200 10158 0 FreeSans 640 0 0 0 vssa
+port 2 nsew
+<< properties >>
+string LEFclass PAD SPACER
+string FIXED_BBOX 0 0 200 39593
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/verilog/power_pads_lib.v b/sky130/custom/sky130_fd_io/verilog/power_pads_lib.v
new file mode 100644
index 0000000..f12b529
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/verilog/power_pads_lib.v
@@ -0,0 +1,714 @@
+//-----------------------------------------------------------------------
+// Verilog entries for standard power pads (s8 power pads + overlays)
+// Also includes stub entries for the corner and fill cells
+// Also includes the custom gpiov2 cell (adds m5 on buses), which is a wrapper
+// for the s8 gpiov2 cell.
+//
+// This file is distributed as open source under the Apache 2.0 license
+// Copyright 2019 efabless, Inc.
+// Written by Tim Edwards 
+//-----------------------------------------------------------------------
+
+module s8iom0_vccd_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc,
+	src_bdy_hvc, vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_hvc;
+  inout src_bdy_hvc;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying power pad (connects p_pad to vccd)
+  s8iom0s8_top_power_hvc_wpad s8iom0s8_top_power_hvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.p_pad(vccd),
+	.ogc_hvc(),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_hvc(drn_hvc),
+	.src_bdy_hvc(src_bdy_hvc)
+  );
+
+endmodule
+
+module s8iom0_vccd_lvc_pad (amuxbus_a, amuxbus_b,
+	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_lvc1;
+  inout drn_lvc2;
+  inout src_bdy_lvc1;
+  inout src_bdy_lvc2;
+  inout bdy2_b2b;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying power pad (connects p_pad to vccd)
+  s8iom0s8_top_power_lvc_wpad s8iom0s8_top_power_lvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.p_pad(vccd),
+	.ogc_lvc(),
+	.bdy2_b2b(bdy2_b2b),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_lvc1(drn_lvc1),
+	.drn_lvc2(drn_lvc2),
+	.src_bdy_lvc1(src_bdy_lvc1),
+	.src_bdy_lvc2(src_bdy_lvc2)
+  );
+
+endmodule
+
+module s8iom0_vdda_lvc_pad (amuxbus_a, amuxbus_b,
+	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_lvc1;
+  inout drn_lvc2;
+  inout src_bdy_lvc1;
+  inout src_bdy_lvc2;
+  inout bdy2_b2b;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying power pad (connects p_pad to vdda)
+  s8iom0s8_top_power_lvc_wpad s8iom0s8_top_power_lvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.p_pad(vdda),
+	.ogc_lvc(),
+	.bdy2_b2b(bdy2_b2b),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_lvc1(drn_lvc1),
+	.drn_lvc2(drn_lvc2),
+	.src_bdy_lvc1(src_bdy_lvc1),
+	.src_bdy_lvc2(src_bdy_lvc2)
+  );
+
+endmodule
+
+module s8iom0_vdda_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc,
+	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_hvc;
+  inout src_bdy_hvc;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying power pad (connects p_pad to vdda)
+  s8iom0s8_top_power_hvc_wpad s8iom0s8_top_power_hvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.p_pad(vdda),
+	.ogc_hvc(),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_hvc(drn_hvc),
+	.src_bdy_hvc(src_bdy_hvc)
+  );
+
+endmodule
+
+module s8iom0_vddio_lvc_pad (amuxbus_a, amuxbus_b,
+	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_lvc1;
+  inout drn_lvc2;
+  inout src_bdy_lvc1;
+  inout src_bdy_lvc2;
+  inout bdy2_b2b;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying power pad (connects p_pad and vddio_q to vddio)
+  s8iom0s8_top_power_lvc_wpad s8iom0s8_top_power_lvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.p_pad(vddio),
+	.ogc_lvc(),
+	.bdy2_b2b(bdy2_b2b),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_lvc1(drn_lvc1),
+	.drn_lvc2(drn_lvc2),
+	.src_bdy_lvc1(src_bdy_lvc1),
+	.src_bdy_lvc2(src_bdy_lvc2)
+  );
+
+  assign vddio_q = vddio;
+
+endmodule
+
+module s8iom0_vddio_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc,
+	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_hvc;
+  inout src_bdy_hvc;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying power pad (connects p_pad and vddio_q to vddio)
+  s8iom0s8_top_power_hvc_wpad s8iom0s8_top_power_hvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.p_pad(vddio),
+	.ogc_hvc(),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_hvc(drn_hvc),
+	.src_bdy_hvc(src_bdy_hvc)
+  );
+
+  assign vddio_q = vddio;
+
+endmodule
+
+module s8iom0_vssd_lvc_pad (amuxbus_a, amuxbus_b,
+	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_lvc1;
+  inout drn_lvc2;
+  inout src_bdy_lvc1;
+  inout src_bdy_lvc2;
+  inout bdy2_b2b;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying ground pad (connects g_pad to vssd)
+  s8iom0s8_top_ground_lvc_wpad s8iom0s8_top_ground_lvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.g_pad(vssd),
+	.ogc_lvc(),
+	.bdy2_b2b(bdy2_b2b),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_lvc1(drn_lvc1),
+	.drn_lvc2(drn_lvc2),
+	.src_bdy_lvc1(src_bdy_lvc1),
+	.src_bdy_lvc2(src_bdy_lvc2)
+  );
+
+endmodule
+
+module s8iom0_vssd_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc,
+	src_bdy_hvc, vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_hvc;
+  inout src_bdy_hvc;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying ground pad (connects g_pad to vssd)
+  s8iom0s8_top_ground_hvc_wpad s8iom0s8_top_ground_hvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.g_pad(vssd),
+	.ogc_hvc(),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_hvc(drn_hvc),
+	.src_bdy_hvc(src_bdy_hvc)
+  );
+
+endmodule
+
+module s8iom0_vssio_lvc_pad (amuxbus_a, amuxbus_b,
+	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_lvc1;
+  inout drn_lvc2;
+  inout src_bdy_lvc1;
+  inout src_bdy_lvc2;
+  inout bdy2_b2b;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying ground pad (connects g_pad and vssio_q to vssio)
+  s8iom0s8_top_ground_lvc_wpad s8iom0s8_top_ground_lvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.g_pad(vssio),
+	.ogc_lvc(),
+	.bdy2_b2b(bdy2_b2b),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_lvc1(drn_lvc1),
+	.drn_lvc2(drn_lvc2),
+	.src_bdy_lvc1(src_bdy_lvc1),
+	.src_bdy_lvc2(src_bdy_lvc2)
+  );
+
+  assign vssio_q = vssio;
+
+endmodule
+
+
+module s8iom0_vssio_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc,
+	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_hvc;
+  inout src_bdy_hvc;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying ground pad (connects g_pad and vssio_q to vssio)
+  s8iom0s8_top_ground_hvc_wpad s8iom0s8_top_ground_hvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.g_pad(vssio),
+	.ogc_hvc(),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_hvc(drn_hvc),
+	.src_bdy_hvc(src_bdy_hvc)
+  );
+
+  assign vssio_q = vssio;
+
+endmodule
+
+module s8iom0_vssa_lvc_pad (amuxbus_a, amuxbus_b,
+	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_lvc1;
+  inout drn_lvc2;
+  inout src_bdy_lvc1;
+  inout src_bdy_lvc2;
+  inout bdy2_b2b;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying ground pad (connects g_pad to vssa)
+  s8iom0s8_top_ground_lvc_wpad s8iom0s8_top_ground_lvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.g_pad(vssa),
+	.ogc_lvc(),
+	.bdy2_b2b(bdy2_b2b),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_lvc1(drn_lvc1),
+	.drn_lvc2(drn_lvc2),
+	.src_bdy_lvc1(src_bdy_lvc1),
+	.src_bdy_lvc2(src_bdy_lvc2)
+  );
+
+endmodule
+
+module s8iom0_vssa_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc,
+	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout drn_hvc;
+  inout src_bdy_hvc;
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+  // Instantiate the underlying ground pad (connects g_pad to vssa)
+  s8iom0s8_top_ground_hvc_wpad s8iom0s8_top_ground_hvc_base ( 
+	.vssa(vssa),
+	.vdda(vdda),
+	.vswitch(vswitch),
+	.vddio_q(vddio_q),
+	.vcchib(vcchib),
+	.vddio(vddio),
+	.vccd(vccd),
+	.vssio(vssio),
+	.vssd(vssd),
+	.vssio_q(vssio_q),
+	.g_pad(vssa),
+	.ogc_hvc(),
+	.amuxbus_a(amuxbus_a),
+	.amuxbus_b(amuxbus_b),
+	.drn_hvc(drn_hvc),
+	.src_bdy_hvc(src_bdy_hvc)
+  );
+
+endmodule
+
+module s8iom0_corner_pad (amuxbus_a, amuxbus_b, 
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+endmodule
+
+module s8iom0s8_com_bus_slice (amuxbus_a, amuxbus_b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+endmodule
+
+module s8iom0s8_com_bus_slice_1um (amuxbus_a, amuxbus_b,
+	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+	vssio, vssd, vssio_q
+);
+  inout amuxbus_a;
+  inout amuxbus_b;
+
+  inout vddio;	
+  inout vddio_q;	
+  inout vdda;
+  inout vccd;
+  inout vswitch;
+  inout vcchib;
+  inout vssa;
+  inout vssd;
+  inout vssio_q;
+  inout vssio;
+
+endmodule
+
+module s8iom0_gpiov2_pad (in_h, pad_a_noesd_h, pad_a_esd_0_h, pad_a_esd_1_h,
+    pad, dm, hld_h_n, in, inp_dis, ib_mode_sel, enable_h, enable_vdda_h,
+    enable_inp_h, oe_n, tie_hi_esd, tie_lo_esd, slow, vtrip_sel, hld_ovr,
+    analog_en, analog_sel, enable_vddio, enable_vswitch_h, analog_pol, out,
+    amuxbus_a, amuxbus_b,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+    vssio, vssd, vssio_q 
+    );
+
+input out;  		
+input oe_n;  		
+input hld_h_n;		
+input enable_h;
+input enable_inp_h;	
+input enable_vdda_h;	
+input enable_vswitch_h;	
+input enable_vddio;	
+input inp_dis;		
+input ib_mode_sel;
+input vtrip_sel;	
+input slow;		
+input hld_ovr;		
+input analog_en;	
+input analog_sel;	
+input analog_pol;	
+input [2:0] dm;		
+
+	inout vddio;	
+	inout vddio_q;	
+	inout vdda;
+	inout vccd;
+	inout vswitch;
+	inout vcchib;
+	inout vssa;
+	inout vssd;
+	inout vssio_q;
+	inout vssio;
+
+inout pad;
+inout pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h;
+inout amuxbus_a;
+inout amuxbus_b;
+
+output in;
+output in_h;
+output tie_hi_esd, tie_lo_esd;
+
+// Instantiate original version with metal4-only power bus
+s8iom0s8_top_gpiov2 gpiov2_base (
+    .in_h(in_h),
+    .pad_a_noesd_h(pad_a_noesd_h),
+    .pad_a_esd_0_h(pad_a_esd_0_h),
+    .pad_a_esd_1_h(pad_a_esd_1_h),
+    .pad(pad),
+    .dm(dm),
+    .hld_h_n(hld_h_n),
+    .in(in),
+    .inp_dis(inp_dis),
+    .ib_mode_sel(ib_mode_sel),
+    .enable_h(enable_h),
+    .enable_vdda_h(enable_vdda_h),
+    .enable_inp_h(enable_inp_h),
+    .oe_n(oe_n),
+    .tie_hi_esd(tie_hi_esd),
+    .tie_lo_esd(tie_lo_esd),
+    .slow(slow),
+    .vtrip_sel(vtrip_sel),
+    .hld_ovr(hld_ovr),
+    .analog_en(analog_en),
+    .analog_sel(analog_sel),
+    .enable_vddio(enable_vddio),
+    .enable_vswitch_h(enable_vswitch_h),
+    .analog_pol(analog_pol),
+    .out(out),
+    .amuxbus_a(amuxbus_a),
+    .amuxbus_b(amuxbus_b) ,
+    .vssa(vssa),
+    .vdda(vdda),
+    .vswitch(vswitch),
+    .vddio_q(vddio_q),
+    .vcchib(vcchib),
+    .vddio(vddio),
+    .vccd(vccd),
+    .vssio(vssio),
+    .vssd(vssd),
+    .vssio_q(vssio_q) 
+);
+
+endmodule
diff --git a/sky130/custom/sky130_fd_sc_hd/scs8hd_diode_1.cdl b/sky130/custom/sky130_fd_sc_hd/scs8hd_diode_1.cdl
new file mode 100644
index 0000000..2ae2f88
--- /dev/null
+++ b/sky130/custom/sky130_fd_sc_hd/scs8hd_diode_1.cdl
@@ -0,0 +1,7 @@
+* Additional subcircuits not in the vendor CDL library
+
+.SUBCKT scs8hd_diode_1 DIODE vgnd vnb vpb vpwr
+*.PININFO DIODE:I vgnd:I vnb:I vpb:I vpwr:I
+* NOTE:  Tap diode is not represented here.
+.ENDS
+
diff --git a/sky130/custom/sky130_fd_sc_hd/scs8hd_diode_2.cdl b/sky130/custom/sky130_fd_sc_hd/scs8hd_diode_2.cdl
new file mode 100644
index 0000000..2abb8b4
--- /dev/null
+++ b/sky130/custom/sky130_fd_sc_hd/scs8hd_diode_2.cdl
@@ -0,0 +1,6 @@
+* Additional subcircuits not in the vendor CDL library
+
+.SUBCKT scs8hd_diode_2 DIODE vgnd vnb vpb vpwr
+*.PININFO DIODE:I vgnd:I vnb:I vpb:I vpwr:I
+* NOTE:  Tap diode is not represented here.
+.ENDS
diff --git a/sky130/custom/techLEF/sky130_fd_sc_hd_tech.lef b/sky130/custom/techLEF/sky130_fd_sc_hd_tech.lef
new file mode 100644
index 0000000..d5e0b31
--- /dev/null
+++ b/sky130/custom/techLEF/sky130_fd_sc_hd_tech.lef
@@ -0,0 +1,746 @@
+VERSION 5.7 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+  TIME NANOSECONDS 1 ;
+  CAPACITANCE PICOFARADS 1 ;
+  RESISTANCE OHMS 1 ;
+  DATABASE MICRONS 1000 ;
+END UNITS
+MANUFACTURINGGRID 0.005 ;
+
+SITE unithd
+    SYMMETRY Y  ;
+    CLASS CORE  ;
+    SIZE  0.460 BY 2.720 ;
+END unithd
+
+LAYER li1
+    TYPE ROUTING ;
+    DIRECTION VERTICAL ;
+
+    PITCH 0.46 0.34 ;
+    OFFSET 0.23 0.17 ;
+
+    WIDTH    0.170 ;                    # LI 1
+    # SPACING  0.170 ;                    # LI 2
+  SPACINGTABLE
+    PARALLELRUNLENGTH 0
+    WIDTH 0 0.170000 ;
+    AREA 0.0561 ;                       # LI 6
+    THICKNESS 0.10 ; 
+
+    RESISTANCE RPERSQ 12.2 ;
+
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNADIFFSIDEAREARATIO PWL ( ( 0.0 75.0 ) ( 0.0125 75.0 ) ( 0.0225 85.125 ) ( 22.5 10200.0 ) ) ;
+
+
+END li1
+
+LAYER mcon
+  TYPE CUT ;
+  WIDTH   0.17 ;		# Mcon 1
+  SPACING 0.19 ;		# Mcon 2
+  ENCLOSURE BELOW 0.0 0.0 ;	# Mcon 4
+  ENCLOSURE ABOVE 0.030 0.060 ; # Met1 4 / Met1 5
+
+  DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC
+  ANTENNADIFFAREARATIO PWL ( ( 0.0 3.0 ) ( 0.0125 3.0 ) ( 0.0225 3.405 ) ( 22.5 408.0 ) ) ;
+
+END mcon
+
+LAYER met1
+    TYPE ROUTING ;
+    DIRECTION HORIZONTAL ;
+
+    PITCH 0.34 ;
+    OFFSET 0.17 ;
+
+    WIDTH    0.140 ;                    # Met1 1
+    #SPACING  0.140 ;                    # Met1 2
+    #SPACING  0.280 RANGE 3.001 100 ;	# Met1 3b
+    SPACINGTABLE
+	  PARALLELRUNLENGTH 0.000
+	    WIDTH 0.000 0.140000
+	    WIDTH 3.000000 0.280000
+	    ;
+    AREA 0.083 ;                        # Met1 6
+    THICKNESS 0.35 ; 
+
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNADIFFSIDEAREARATIO PWL ( ( 0.000000 400.000000 ) ( 0.012500 400.000000 ) ( 0.022500 2609.000000 ) ( 22.500000 11600.000000 ) ) ;
+
+    EDGECAPACITANCE 1.79E-6 ;
+    CAPACITANCE CPERSQDIST 25.8E-6 ;
+    DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+    ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+    MAXIMUMDENSITY 70.0 ;
+    DENSITYCHECKWINDOW 700.0 700.0 ;
+    DENSITYCHECKSTEP 70.0 ;
+
+    RESISTANCE RPERSQ 0.125 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+  WIDTH   0.15 ;		# Via 1a
+  SPACING 0.17  ;		# Via 2
+  ENCLOSURE BELOW 0.055 0.085 ; # Via 4a / Via 5a
+  ENCLOSURE ABOVE 0.055 0.085 ; # Met2 4 / Met2 5
+  ANTENNADIFFAREARATIO PWL ( ( 0.0 6.0 ) ( 0.0125 6.0 ) ( 0.0225 6.81 ) ( 22.5 816.0 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC
+END via
+
+LAYER met2
+    TYPE ROUTING ;
+    DIRECTION VERTICAL ;
+
+    PITCH  0.46 ;
+    OFFSET 0.23 ;
+
+    WIDTH    0.140 ;                    # Met2 1
+    #SPACING  0.140 ;                    # Met2 2
+    #SPACING  0.280 RANGE 3.001 100 ;	# Met2 3b
+    SPACINGTABLE
+	  PARALLELRUNLENGTH 0.000
+	    WIDTH 0.000 0.140000
+	    WIDTH 3.000000 0.28000 ;
+    AREA 0.0676 ;                       # Met2 6
+    THICKNESS 0.35 ; 
+
+    ANTENNAMODEL OXIDE1 ;
+    CAPACITANCE CPERSQDIST 17.5E-6 ;
+    DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+    ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+    ANTENNADIFFSIDEAREARATIO PWL ( ( 0.0 400.0 ) ( 0.0125 400.0 ) ( 0.0225 2609.0 ) ( 22.5 11600.0 ) ) ;
+    
+    MAXIMUMDENSITY 70.0 ;
+    DENSITYCHECKWINDOW 700.0 700.0 ;
+    DENSITYCHECKSTEP 70.0 ;
+    RESISTANCE RPERSQ 0.125 ;
+END met2
+
+LAYER via2
+  TYPE CUT ;
+  WIDTH   0.20 ;		# Via2 1
+  SPACING 0.20 ;		# Via2 2
+  ENCLOSURE BELOW 0.040 0.085 ;	# Via2 4
+  ENCLOSURE ABOVE 0.065 0.065 ;	# Met3 4
+  ANTENNADIFFAREARATIO PWL ( ( 0.0 6.0 ) ( 0.0125 6.0 ) ( 0.0225 6.81 ) ( 22.5 816.0 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+
+END via2
+
+LAYER met3
+    TYPE ROUTING ;
+    DIRECTION HORIZONTAL ;
+
+    PITCH  0.68 ;
+    OFFSET 0.34 ;
+
+    WIDTH    0.300 ;            # Met3 1
+    #SPACING  0.300 ;		# Met3 2
+    SPACINGTABLE
+	    PARALLELRUNLENGTH 0
+	    WIDTH 0 0.30
+	    WIDTH 3.0 0.40 ;
+    AREA     0.240 ;            # Met3 6
+    THICKNESS 0.8 ;
+
+    EDGECAPACITANCE 1.86E-6 ;
+    CAPACITANCE CPERSQDIST 12.6E-6 ;
+    DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+    ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNADIFFSIDEAREARATIO PWL ( ( 0.0 400.0 ) ( 0.0125 400.0 ) ( 0.0225 2609.0 ) ( 22.5 11600.0 ) ) ;
+
+    MAXIMUMDENSITY 70.0 ;
+    DENSITYCHECKWINDOW 700.0 700.0 ;
+    DENSITYCHECKSTEP 70.0 ;
+    RESISTANCE RPERSQ 0.047 ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+
+  WIDTH   0.20 ;		# Via3 1
+  SPACING 0.20 ;		# Via3 2
+  ENCLOSURE BELOW 0.060 0.090 ;	# Via3 4 / Via3 5
+  ENCLOSURE ABOVE 0.065 0.065 ;	# Met4 3
+  ANTENNADIFFAREARATIO PWL ( ( 0.0 6.0 ) ( 0.0125 6.0 ) ( 0.0225 6.81 ) ( 22.5 816.0 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+END via3
+
+LAYER met4
+    TYPE ROUTING ;
+    DIRECTION VERTICAL ;
+
+    PITCH  0.92 ;
+    OFFSET 0.46 ;
+
+    WIDTH    0.300 ;            # Met4 1
+    #SPACING  0.300 ;		# Met4 2
+    
+    SPACINGTABLE
+	    PARALLELRUNLENGTH 0
+	    WIDTH 0 0.30
+	    WIDTH 3.0 0.40 ;
+    AREA     0.240 ;            # Met4 4a
+
+    THICKNESS 0.8 ;
+
+    EDGECAPACITANCE 1.29E-6 ;
+    CAPACITANCE CPERSQDIST 8.67E-6 ;
+    DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+    ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+    ANTENNAMODEL OXIDE1 ;
+    ANTENNADIFFSIDEAREARATIO PWL ( ( 0.0 400.0 ) ( 0.0125 400.0 ) ( 0.0225 2609.0 ) ( 22.5 11600.0 ) ) ;
+
+    MAXIMUMDENSITY 70.0 ;
+    DENSITYCHECKWINDOW 700.0 700.0 ;
+    DENSITYCHECKSTEP 70.0 ;
+    RESISTANCE RPERSQ 0.047 ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+
+  WIDTH   0.80 ;		# Via4 1
+  SPACING 0.80 ;		# Via4 2
+  ENCLOSURE BELOW 0.190 0.190 ;	# Via4 4
+  ENCLOSURE ABOVE 0.310 0.310 ;	# Met5 3
+  ANTENNADIFFAREARATIO PWL ( ( 0.0 6.0 ) ( 0.0125 6.0 ) ( 0.0225 6.81 ) ( 22.5 816.0 ) ) ;
+  DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC
+END via4
+
+LAYER met5
+    TYPE ROUTING ;
+    DIRECTION HORIZONTAL ;
+
+    PITCH  3.4 ;
+    OFFSET 1.7 ; 
+
+    WIDTH    1.600 ;       # Met5 1
+    #SPACING  1.600 ;       # Met5 2
+    SPACINGTABLE
+	    PARALLELRUNLENGTH 0
+	    WIDTH 0 1.600 ;
+    AREA     4.000 ;       # Met5 4
+
+    THICKNESS 1.2 ;
+
+    ANTENNAMODEL OXIDE1 ;
+    EDGECAPACITANCE 4.96E-6 ;
+    CAPACITANCE CPERSQDIST 6.48E-6 ;
+    DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC
+    ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC
+    ANTENNADIFFSIDEAREARATIO PWL ( ( 0.0 400.0 ) ( 0.0125 400.0 ) ( 0.0225 2609.0 ) ( 22.5 11600.0 ) ) ;
+    
+    RESISTANCE RPERSQ 0.0285 ;
+END met5
+
+### Routing via cells section   ###
+# Plus via rule, metals are along the prefered direction
+VIA L1M1_PR DEFAULT
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER li1 ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER met1 ;
+  RECT -0.145000 -0.115000 0.145000 0.115000 ;
+END L1M1_PR
+
+VIARULE L1M1_PR GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0.000000 0.000000 ;
+  LAYER met1 ;
+  ENCLOSURE 0.060000 0.030000 ;
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  SPACING 0.360000 BY 0.360000 ;
+END L1M1_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA L1M1_PR_R DEFAULT
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER li1 ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER met1 ;
+  RECT -0.115000 -0.145000 0.115000 0.145000 ;
+END L1M1_PR_R
+
+VIARULE L1M1_PR_R GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0.000000 0.000000 ;
+  LAYER met1 ;
+  ENCLOSURE 0.030000 0.060000 ;
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  SPACING 0.360000 BY 0.360000 ;
+END L1M1_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA L1M1_PR_M DEFAULT
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER li1 ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER met1 ;
+  RECT -0.115000 -0.145000 0.115000 0.145000 ;
+END L1M1_PR_M
+
+VIARULE L1M1_PR_M GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0.000000 0.000000 ;
+  LAYER met1 ;
+  ENCLOSURE 0.030000 0.060000 ;
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  SPACING 0.360000 BY 0.360000 ;
+END L1M1_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA L1M1_PR_MR DEFAULT
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER li1 ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER met1 ;
+  RECT -0.145000 -0.115000 0.145000 0.115000 ;
+END L1M1_PR_MR
+
+VIARULE L1M1_PR_MR GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0.000000 0.000000 ;
+  LAYER met1 ;
+  ENCLOSURE 0.060000 0.030000 ;
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  SPACING 0.360000 BY 0.360000 ;
+END L1M1_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA L1M1_PR_C DEFAULT
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER li1 ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  LAYER met1 ;
+  RECT -0.145000 -0.145000 0.145000 0.145000 ;
+END L1M1_PR_C
+
+VIARULE L1M1_PR_C GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0.000000 0.000000 ;
+  LAYER met1 ;
+  ENCLOSURE 0.060000 0.060000 ;
+  LAYER mcon ;
+  RECT -0.085000 -0.085000 0.085000 0.085000 ;
+  SPACING 0.360000 BY 0.360000 ;
+END L1M1_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M1M2_PR DEFAULT
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  LAYER met1 ;
+  RECT -0.160000 -0.130000 0.160000 0.130000 ;
+  LAYER met2 ;
+  RECT -0.130000 -0.160000 0.130000 0.160000 ;
+END M1M2_PR
+
+VIARULE M1M2_PR GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.085000 0.055000 ;
+  LAYER met2 ;
+  ENCLOSURE 0.055000 0.085000 ;
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  SPACING 0.320000 BY 0.320000 ;
+END M1M2_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M1M2_PR_R DEFAULT
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  LAYER met1 ;
+  RECT -0.130000 -0.160000 0.130000 0.160000 ;
+  LAYER met2 ;
+  RECT -0.160000 -0.130000 0.160000 0.130000 ;
+END M1M2_PR_R
+
+VIARULE M1M2_PR_R GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.055000 0.085000 ;
+  LAYER met2 ;
+  ENCLOSURE 0.085000 0.055000 ;
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  SPACING 0.320000 BY 0.320000 ;
+END M1M2_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M1M2_PR_M DEFAULT
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  LAYER met1 ;
+  RECT -0.160000 -0.130000 0.160000 0.130000 ;
+  LAYER met2 ;
+  RECT -0.160000 -0.130000 0.160000 0.130000 ;
+END M1M2_PR_M
+
+VIARULE M1M2_PR_M GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.085000 0.055000 ;
+  LAYER met2 ;
+  ENCLOSURE 0.085000 0.055000 ;
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  SPACING 0.320000 BY 0.320000 ;
+END M1M2_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M1M2_PR_MR DEFAULT
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  LAYER met1 ;
+  RECT -0.130000 -0.160000 0.130000 0.160000 ;
+  LAYER met2 ;
+  RECT -0.130000 -0.160000 0.130000 0.160000 ;
+END M1M2_PR_MR
+
+VIARULE M1M2_PR_MR GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.055000 0.085000 ;
+  LAYER met2 ;
+  ENCLOSURE 0.055000 0.085000 ;
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  SPACING 0.320000 BY 0.320000 ;
+END M1M2_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M1M2_PR_C DEFAULT
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  LAYER met1 ;
+  RECT -0.160000 -0.160000 0.160000 0.160000 ;
+  LAYER met2 ;
+  RECT -0.160000 -0.160000 0.160000 0.160000 ;
+END M1M2_PR_C
+
+VIARULE M1M2_PR_C GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.085000 0.085000 ;
+  LAYER met2 ;
+  ENCLOSURE 0.085000 0.085000 ;
+  LAYER via ;
+  RECT -0.075000 -0.075000 0.075000 0.075000 ;
+  SPACING 0.320000 BY 0.320000 ;
+END M1M2_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M2M3_PR DEFAULT
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met2 ;
+  RECT -0.140000 -0.185000 0.140000 0.185000 ;
+  LAYER met3 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M2M3_PR
+
+VIARULE M2M3_PR GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.040000 0.085000 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M2M3_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M2M3_PR_R DEFAULT
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met2 ;
+  RECT -0.185000 -0.140000 0.185000 0.140000 ;
+  LAYER met3 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M2M3_PR_R
+
+VIARULE M2M3_PR_R GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.085000 0.040000 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M2M3_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M2M3_PR_M DEFAULT
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met2 ;
+  RECT -0.140000 -0.185000 0.140000 0.185000 ;
+  LAYER met3 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M2M3_PR_M
+
+VIARULE M2M3_PR_M GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.040000 0.085000 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M2M3_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M2M3_PR_MR DEFAULT
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met2 ;
+  RECT -0.185000 -0.140000 0.185000 0.140000 ;
+  LAYER met3 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M2M3_PR_MR
+
+VIARULE M2M3_PR_MR GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.085000 0.040000 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M2M3_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M2M3_PR_C DEFAULT
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met2 ;
+  RECT -0.185000 -0.185000 0.185000 0.185000 ;
+  LAYER met3 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M2M3_PR_C
+
+VIARULE M2M3_PR_C GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.085000 0.085000 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M2M3_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M3M4_PR DEFAULT
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met3 ;
+  RECT -0.190000 -0.160000 0.190000 0.160000 ;
+  LAYER met4 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M3M4_PR
+
+VIARULE M3M4_PR GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.090000 0.060000 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M3M4_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M3M4_PR_R DEFAULT
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met3 ;
+  RECT -0.160000 -0.190000 0.160000 0.190000 ;
+  LAYER met4 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M3M4_PR_R
+
+VIARULE M3M4_PR_R GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.060000 0.090000 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M3M4_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M3M4_PR_M DEFAULT
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met3 ;
+  RECT -0.190000 -0.160000 0.190000 0.160000 ;
+  LAYER met4 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M3M4_PR_M
+
+VIARULE M3M4_PR_M GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.090000 0.060000 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M3M4_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M3M4_PR_MR DEFAULT
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met3 ;
+  RECT -0.160000 -0.190000 0.160000 0.190000 ;
+  LAYER met4 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M3M4_PR_MR
+
+VIARULE M3M4_PR_MR GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.060000 0.090000 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M3M4_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M3M4_PR_C DEFAULT
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met3 ;
+  RECT -0.190000 -0.190000 0.190000 0.190000 ;
+  LAYER met4 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M3M4_PR_C
+
+VIARULE M3M4_PR_C GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.090000 0.090000 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M3M4_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M4M5_PR DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR
+
+VIARULE M4M5_PR GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M4M5_PR_R DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR_R
+
+VIARULE M4M5_PR_R GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M4M5_PR_M DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR_M
+
+VIARULE M4M5_PR_M GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M4M5_PR_MR DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR_MR
+
+VIARULE M4M5_PR_MR GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M4M5_PR_C DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR_C
+
+VIARULE M4M5_PR_C GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR_C
+###  end of single via cells   ###
+
+END LIBRARY
diff --git a/sky130/custom/techLEF/sky130_fd_sc_hs_tech.lef b/sky130/custom/techLEF/sky130_fd_sc_hs_tech.lef
new file mode 100644
index 0000000..7f8f3af
--- /dev/null
+++ b/sky130/custom/techLEF/sky130_fd_sc_hs_tech.lef
@@ -0,0 +1,712 @@
+
+NAMESCASESENSITIVE ON ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+  TIME NANOSECONDS 1 ;
+  CAPACITANCE PICOFARADS 1 ;
+  RESISTANCE OHMS 1 ;
+  DATABASE MICRONS 1000 ;
+END UNITS
+MANUFACTURINGGRID 0.005 ;
+
+SITE unitehd
+    SYMMETRY Y  ;
+    CLASS CORE  ;
+    SIZE  0.460 BY 3.400 ;
+END unitehd
+
+######  Starting overlap layers #####
+# ******** Layer OverlapCheck, type blockage, number 90 **************
+LAYER OverlapCheck
+  TYPE OVERLAP ;
+END OverlapCheck
+
+######  Starting routing layers - metal and via #####
+# ******** Layer li1, type routing, number 56 **************
+LAYER li1
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.48 ;
+  MINWIDTH 0.170000 ;
+  WIDTH 0.170000 ;
+  AREA 0.028900 ;
+  SPACINGTABLE
+    PARALLELRUNLENGTH 0
+    WIDTH 0 0.170000 ;
+  THICKNESS 0.100000 ;
+  EDGECAPACITANCE 3.26E-6 ;
+  CAPACITANCE CPERSQDIST 36.9E-6 ;
+  RESISTANCE RPERSQ 12.2 ;
+#  DCCURRENTDENSITY AVERAGE (no limit on this layer) ;
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0.000000 75.000000 ) ( 0.012500 75.000000 ) ( 0.022500 85.125000 ) ( 22.500000 10200.000000 ) ) ;
+END li1
+
+# ******** Layer mcon, type routing, number 35 **************
+LAYER mcon
+  TYPE CUT ;
+  SPACING 0.190000 ;
+  WIDTH 0.170000 ;
+  ANTENNADIFFAREARATIO PWL ( ( 0.000000 3.000000 ) ( 0.012500 3.000000 ) ( 0.022500 3.405000 ) ( 22.500000 408.000000 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC
+  ENCLOSURE BELOW 0.000000 0.000000 ;
+  ENCLOSURE ABOVE 0.000000 0.000000 ;
+END mcon
+
+# ******** Layer met1, type routing, number 36 **************
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.37 ;
+  MINENCLOSEDAREA 0.140000 ;
+  MINWIDTH 0.140000 ;
+  WIDTH 0.140000 ;
+  AREA 0.083000 ;
+  SPACINGTABLE
+  PARALLELRUNLENGTH 0.000
+    WIDTH 0.000 0.140000
+    WIDTH 3.000000 0.280000
+    ;
+  THICKNESS 0.350000 ;
+  EDGECAPACITANCE 1.79E-6 ;
+  CAPACITANCE CPERSQDIST 25.8E-6 ;
+  RESISTANCE RPERSQ 0.125 ;
+  DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0.000000 400.000000 ) ( 0.012500 400.000000 ) ( 0.022500 2609.000000 ) ( 22.500000 11600.000000 ) ) ;
+END met1
+
+# ******** Layer via, type routing, number 40 **************
+LAYER via1
+  TYPE CUT ;
+  SPACING 0.170000 ;
+  WIDTH 0.150000 ;
+  ANTENNADIFFAREARATIO PWL ( ( 0.000000 6.000000 ) ( 0.012500 6.000000 ) ( 0.022500 6.810000 ) ( 22.500000 816.000000 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC
+  ENCLOSURE BELOW 0.000000 0.000000 ;
+  ENCLOSURE ABOVE 0.000000 0.000000 ;
+END via1
+
+# ******** Layer met2, type routing, number 41 **************
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.48 ;
+  MINENCLOSEDAREA 0.140000 ;
+  MINWIDTH 0.140000 ;
+  WIDTH 0.140000 ;
+  AREA 0.067600 ;
+  SPACINGTABLE
+  PARALLELRUNLENGTH 0.000
+    WIDTH 0.000 0.140000
+    WIDTH 3.000000 0.280000
+    ;
+  THICKNESS 0.350000 ;
+  EDGECAPACITANCE 1.22E-6 ;
+  CAPACITANCE CPERSQDIST 17.5E-6 ;
+  RESISTANCE RPERSQ 0.125 ;
+  DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0.000000 400.000000 ) ( 0.012500 400.000000 ) ( 0.022500 2609.000000 ) ( 22.500000 11600.000000 ) ) ;
+END met2
+
+# ******** Layer via2, type routing, number 44 **************
+LAYER via2
+  TYPE CUT ;
+  SPACING 0.200000 ;
+  WIDTH 0.200000 ;
+  ANTENNADIFFAREARATIO PWL ( ( 0.000000 6.000000 ) ( 0.012500 6.000000 ) ( 0.022500 6.810000 ) ( 22.500000 816.000000 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+  ENCLOSURE BELOW 0.000000 0.000000 ;
+  ENCLOSURE ABOVE 0.000000 0.000000 ;
+END via2
+
+# ******** Layer met3, type routing, number 34 **************
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 0.666 ;
+  MINWIDTH 0.300000 ;
+  WIDTH 0.300000 ;
+  AREA 0.240000 ;
+  SPACINGTABLE
+  PARALLELRUNLENGTH 0.000
+    WIDTH 0.000 0.300000
+    WIDTH 3.000000 0.400000
+    ;
+  THICKNESS 0.800000 ;
+  EDGECAPACITANCE 1.86E-6 ;
+  CAPACITANCE CPERSQDIST 12.6E-6 ;
+  RESISTANCE RPERSQ 0.047 ;
+  DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0.000000 400.000000 ) ( 0.012500 400.000000 ) ( 0.022500 2609.000000 ) ( 22.500000 11600.000000 ) ) ;
+END met3
+
+# ******** Layer via3, type routing, number 70 **************
+LAYER via3
+  TYPE CUT ;
+  SPACING 0.200000 ;
+  WIDTH 0.200000 ;
+  ANTENNADIFFAREARATIO PWL ( ( 0.000000 6.000000 ) ( 0.012500 6.000000 ) ( 0.022500 6.810000 ) ( 22.500000 816.000000 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+  ENCLOSURE BELOW 0.000000 0.000000 ;
+  ENCLOSURE ABOVE 0.000000 0.000000 ;
+END via3
+
+# ******** Layer met4, type routing, number 71 **************
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+  PITCH 0.96 ;
+  MINWIDTH 0.300000 ;
+  WIDTH 0.300000 ;
+  AREA 0.240000 ;
+  SPACINGTABLE
+  PARALLELRUNLENGTH 0.000
+    WIDTH 0.000 0.300000
+    WIDTH 3.000000 0.400000
+    ;
+  THICKNESS 0.800000 ;
+  EDGECAPACITANCE 1.29E-6 ;
+  CAPACITANCE CPERSQDIST 8.67E-6 ;
+  RESISTANCE RPERSQ 0.047 ;
+  DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0.000000 400.000000 ) ( 0.012500 400.000000 ) ( 0.022500 2609.000000 ) ( 22.500000 11600.000000 ) ) ;
+END met4
+
+# ******** Layer via4, type routing, number 58 **************
+LAYER via4
+  TYPE CUT ;
+  SPACING 0.800000 ;
+  WIDTH 0.800000 ;
+  ANTENNADIFFAREARATIO PWL ( ( 0.000000 6.000000 ) ( 0.012500 6.000000 ) ( 0.022500 6.810000 ) ( 22.500000 816.000000 ) ) ;
+  DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC
+  ENCLOSURE BELOW 0.000000 0.000000 ;
+  ENCLOSURE ABOVE 0.000000 0.000000 ;
+END via4
+
+# ******** Layer met5, type routing, number 72 **************
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+  PITCH 3.3 ;
+  MINWIDTH 1.600000 ;
+  WIDTH 1.600000 ;
+  AREA 2.560000 ;
+  SPACINGTABLE
+    PARALLELRUNLENGTH 0
+    WIDTH 0 1.600000 ;
+  THICKNESS 1.200000 ;
+  EDGECAPACITANCE 4.96E-6 ;
+  CAPACITANCE CPERSQDIST 6.48E-6 ;
+  RESISTANCE RPERSQ 0.047 ;
+  DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0.000000 400.000000 ) ( 0.012500 400.000000 ) ( 0.022500 2609.000000 ) ( 22.500000 11600.000000 ) ) ;
+END met5
+
+######  completed routing layers - metal and via #####
+
+### Routing via cells section   ###
+# Plus via rule, metals are along the prefered direction
+VIA L1M1_PR DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.085 -0.165 0.085 0.165 ;
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END L1M1_PR
+
+VIARULE L1M1_PR GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0.000 0.080 ;
+ LAYER met1 ;
+ ENCLOSURE 0.030 0.060 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.360 BY 0.360 ;
+END L1M1_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA L1M1_PR_R DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.165 -0.085 0.165 0.085 ;
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END L1M1_PR_R
+
+VIARULE L1M1_PR_R GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0.000 0.080 ;
+ LAYER met1 ;
+ ENCLOSURE 0.030 0.060 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.360 BY 0.360 ;
+END L1M1_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA L1M1_PR_M DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.085 -0.165 0.085 0.165 ;
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END L1M1_PR_M
+
+VIARULE L1M1_PR_M GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0.000 0.080 ;
+ LAYER met1 ;
+ ENCLOSURE 0.030 0.060 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.360 BY 0.360 ;
+END L1M1_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA L1M1_PR_MR DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.165 -0.085 0.165 0.085 ;
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END L1M1_PR_MR
+
+VIARULE L1M1_PR_MR GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0.000 0.080 ;
+ LAYER met1 ;
+ ENCLOSURE 0.030 0.060 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.360 BY 0.360 ;
+END L1M1_PR_MR
+
+# Centered via rule, we really do not want to use it
+# VIA L1M1_PR_C DEFAULT
+#   LAYER mcon ;
+#   RECT -0.085000 -0.085000 0.085000 0.085000 ;
+#   LAYER li1 ;
+#   RECT -0.085000 -0.085000 0.085000 0.085000 ;
+#   LAYER met1 ;
+#   RECT -0.145000 -0.145000 0.145000 0.145000 ;
+# END L1M1_PR_C
+
+# VIARULE L1M1_PR_C GENERATE
+#   LAYER li1 ;
+#   ENCLOSURE 0.000000 0.000000 ;
+#   LAYER met1 ;
+#   ENCLOSURE 0.060000 0.060000 ;
+#   LAYER mcon ;
+#   RECT -0.085000 -0.085000 0.085000 0.085000 ;
+#   SPACING 0.360000 BY 0.360000 ;
+# END L1M1_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M1M2_PR DEFAULT
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIARULE M1M2_PR GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER met2 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.320 BY 0.320 ;
+END M1M2_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M1M2_PR_R DEFAULT
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIARULE M1M2_PR_R GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER met2 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.320 BY 0.320 ;
+END M1M2_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M1M2_PR_M DEFAULT
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIARULE M1M2_PR_M GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER met2 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.320 BY 0.320 ;
+END M1M2_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M1M2_PR_MR DEFAULT
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIARULE M1M2_PR_MR GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER met2 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER via1 ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.320 BY 0.320 ;
+END M1M2_PR_MR
+
+# # Centered via rule, we really do not want to use it
+# VIA M1M2_PR_C DEFAULT
+#   LAYER via ;
+#   RECT -0.075000 -0.075000 0.075000 0.075000 ;
+#   LAYER met1 ;
+#   RECT -0.160000 -0.160000 0.160000 0.160000 ;
+#   LAYER met2 ;
+#   RECT -0.160000 -0.160000 0.160000 0.160000 ;
+# END M1M2_PR_C
+
+# VIARULE M1M2_PR_C GENERATE
+#   LAYER met1 ;
+#   ENCLOSURE 0.085000 0.085000 ;
+#   LAYER met2 ;
+#   ENCLOSURE 0.085000 0.085000 ;
+#   LAYER via ;
+#   RECT -0.075000 -0.075000 0.075000 0.075000 ;
+#   SPACING 0.320000 BY 0.320000 ;
+# END M1M2_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M2M3_PR DEFAULT
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIARULE M2M3_PR GENERATE
+ LAYER met2 ;
+ ENCLOSURE 0.040 0.085 ;
+ LAYER met3 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.40 BY 0.40 ;
+END M2M3_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M2M3_PR_R DEFAULT
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIARULE M2M3_PR_R GENERATE
+ LAYER met2 ;
+ ENCLOSURE 0.040 0.085 ;
+ LAYER met3 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.40 BY 0.40 ;
+END M2M3_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M2M3_PR_M DEFAULT
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met2 ;
+  RECT -0.140000 -0.185000 0.140000 0.185000 ;
+  LAYER met3 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M2M3_PR_M
+
+VIARULE M2M3_PR_M GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.040000 0.085000 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M2M3_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M2M3_PR_MR DEFAULT
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met2 ;
+  RECT -0.185000 -0.140000 0.185000 0.140000 ;
+  LAYER met3 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M2M3_PR_MR
+
+VIARULE M2M3_PR_MR GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.085000 0.040000 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via2 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M2M3_PR_MR
+
+# # Centered via rule, we really do not want to use it
+# VIA M2M3_PR_C DEFAULT
+#   LAYER via2 ;
+#   RECT -0.100000 -0.100000 0.100000 0.100000 ;
+#   LAYER met2 ;
+#   RECT -0.185000 -0.185000 0.185000 0.185000 ;
+#   LAYER met3 ;
+#   RECT -0.165000 -0.165000 0.165000 0.165000 ;
+# END M2M3_PR_C
+
+# VIARULE M2M3_PR_C GENERATE
+#   LAYER met2 ;
+#   ENCLOSURE 0.085000 0.085000 ;
+#   LAYER met3 ;
+#   ENCLOSURE 0.065000 0.065000 ;
+#   LAYER via2 ;
+#   RECT -0.100000 -0.100000 0.100000 0.100000 ;
+#   SPACING 0.400000 BY 0.400000 ;
+# END M2M3_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M3M4_PR DEFAULT
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIARULE M3M4_PR GENERATE
+ LAYER met3 ;
+ ENCLOSURE 0.06 0.09 ;
+ LAYER met4 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.40 BY 0.40 ;
+END M3M4_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M3M4_PR_R DEFAULT
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIARULE M3M4_PR_R GENERATE
+ LAYER met3 ;
+ ENCLOSURE 0.06 0.09 ;
+ LAYER met4 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.40 BY 0.40 ;
+END M3M4_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M3M4_PR_M DEFAULT
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met3 ;
+  RECT -0.190000 -0.160000 0.190000 0.160000 ;
+  LAYER met4 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M3M4_PR_M
+
+VIARULE M3M4_PR_M GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.090000 0.060000 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M3M4_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M3M4_PR_MR DEFAULT
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  LAYER met3 ;
+  RECT -0.160000 -0.190000 0.160000 0.190000 ;
+  LAYER met4 ;
+  RECT -0.165000 -0.165000 0.165000 0.165000 ;
+END M3M4_PR_MR
+
+VIARULE M3M4_PR_MR GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.060000 0.090000 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065000 0.065000 ;
+  LAYER via3 ;
+  RECT -0.100000 -0.100000 0.100000 0.100000 ;
+  SPACING 0.400000 BY 0.400000 ;
+END M3M4_PR_MR
+
+# # Centered via rule, we really do not want to use it
+# VIA M3M4_PR_C DEFAULT
+#   LAYER via3 ;
+#   RECT -0.100000 -0.100000 0.100000 0.100000 ;
+#   LAYER met3 ;
+#   RECT -0.190000 -0.190000 0.190000 0.190000 ;
+#   LAYER met4 ;
+#   RECT -0.165000 -0.165000 0.165000 0.165000 ;
+# END M3M4_PR_C
+
+# VIARULE M3M4_PR_C GENERATE
+#   LAYER met3 ;
+#   ENCLOSURE 0.090000 0.090000 ;
+#   LAYER met4 ;
+#   ENCLOSURE 0.065000 0.065000 ;
+#   LAYER via3 ;
+#   RECT -0.100000 -0.100000 0.100000 0.100000 ;
+#   SPACING 0.400000 BY 0.400000 ;
+# END M3M4_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M4M5_PR DEFAULT
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIARULE M4M5_PR GENERATE
+ LAYER met4 ;
+ ENCLOSURE 0.190 0.190 ;
+ LAYER met5 ;
+ ENCLOSURE 0.310 0.310 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ SPACING 1.60 BY 1.60 ;
+END M4M5_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M4M5_PR_R DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR_R
+
+VIARULE M4M5_PR_R GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M4M5_PR_M DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR_M
+
+VIARULE M4M5_PR_M GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M4M5_PR_MR DEFAULT
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  LAYER met4 ;
+  RECT -0.590000 -0.590000 0.590000 0.590000 ;
+  LAYER met5 ;
+  RECT -0.710000 -0.710000 0.710000 0.710000 ;
+END M4M5_PR_MR
+
+VIARULE M4M5_PR_MR GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.190000 0.190000 ;
+  LAYER met5 ;
+  ENCLOSURE 0.310000 0.310000 ;
+  LAYER via4 ;
+  RECT -0.400000 -0.400000 0.400000 0.400000 ;
+  SPACING 1.600000 BY 1.600000 ;
+END M4M5_PR_MR
+
+# # Centered via rule, we really do not want to use it
+# VIA M4M5_PR_C DEFAULT
+#   LAYER via4 ;
+#   RECT -0.400000 -0.400000 0.400000 0.400000 ;
+#   LAYER met4 ;
+#   RECT -0.590000 -0.590000 0.590000 0.590000 ;
+#   LAYER met5 ;
+#   RECT -0.710000 -0.710000 0.710000 0.710000 ;
+# END M4M5_PR_C
+
+# VIARULE M4M5_PR_C GENERATE
+#   LAYER met4 ;
+#   ENCLOSURE 0.190000 0.190000 ;
+#   LAYER met5 ;
+#   ENCLOSURE 0.310000 0.310000 ;
+#   LAYER via4 ;
+#   RECT -0.400000 -0.400000 0.400000 0.400000 ;
+#   SPACING 1.600000 BY 1.600000 ;
+# END M4M5_PR_C
+
diff --git a/sky130/sky130.json b/sky130/sky130.json
new file mode 100644
index 0000000..bf54238
--- /dev/null
+++ b/sky130/sky130.json
@@ -0,0 +1,53 @@
+#define DESCRIPTION Skywater 0.13um CMOS, local interconntect + high-resistance poly
+#ifdef METAL5
+#define OPTION1 + 5 metal layer backend stack
+#endif (METAL5)
+#ifdef MIM
+#define OPTION2 + MiM caps
+#endif (MIM)
+#ifdef REDISTRIBUTION
+#define OPTION3 + redistribution layer
+#endif (REDISTRIBUTION)
+{
+    "foundry" : "SW",
+    "foundry-name" : "SkyWater",
+    "node" : "TECHNAME",
+    "feature-size" : "130nm",
+    "status" : "active",
+    "description" : "DESCRIPTION OPTION1 OPTION2 OPTION3",
+    "options" : [
+#ifdef METAL5
+#undef METAL5
+#ifdef MIM || REDISTRIBUTION
+        "METAL5",
+#else (!(MIM || REDISTRIBUTION))
+        "METAL5"
+#endif (!(MIM || REDISTRIBUTION))
+#endif (METAL5)
+#ifdef MIM
+#undef MIM
+#ifdef REDISTRIBUTION
+        "MIM",
+#else
+        "MIM"
+#endif (REDISTRIBUTION)
+#endif (MIM)
+#ifdef REDISTRIBUTION
+#undef REDISTRIBUTION
+        "REDISTRIBUTION"
+#endif (REDISTRIBUTION)
+    ],
+    "stdcells" : [
+	"sky130_fd_sc_hd",
+	"sky130_fd_sc_hdll",
+	"sky130_fd_sc_hs",
+	"sky130_fd_sc_hvl",
+	"sky130_fd_sc_lp",
+	"sky130_fd_sc_ls",
+	"sky130_fd_sc_ms",
+	"sky130_osu130"
+    ],
+    "iocells" : [
+        "sky130_fd_io"
+    ]
+}
diff --git a/sky130/sky130.lyp b/sky130/sky130.lyp
new file mode 100644
index 0000000..cf7ec0b
--- /dev/null
+++ b/sky130/sky130.lyp
@@ -0,0 +1,8241 @@
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+   <line>.*.......*......</line>
+  </pattern>
+  <order>39</order>
+  <name>backSlash2</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>*.....*.*.....*.</line>
+   <line>.*...*...*...*..</line>
+   <line>..*.*.....*.*...</line>
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+   <line>*.....*.*.....*.</line>
+   <line>...*...*...*...*</line>
+   <line>*.....*.*.....*.</line>
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+   <line>...*...*...*...*</line>
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+   <line>*.....*.*.....*.</line>
+   <line>...*...*...*...*</line>
+  </pattern>
+  <order>40</order>
+  <name>lattice</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>**..**..**..**..</line>
+   <line>**..**..**..**..</line>
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+   <line>**..**..**..**..</line>
+   <line>..**..**..**..**</line>
+   <line>..**..**..**..**</line>
+  </pattern>
+  <order>41</order>
+  <name>smallChecker</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>....*...........</line>
+   <line>...*.*..........</line>
+   <line>..*...*.........</line>
+   <line>.*.....*........</line>
+   <line>*.......*.......</line>
+   <line>.*.......*......</line>
+   <line>..*.......*.....</line>
+   <line>...*.......*....</line>
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+   <line>......*.......*.</line>
+   <line>.......*.......*</line>
+   <line>........*.....*.</line>
+   <line>.........*...*..</line>
+   <line>..........*.*...</line>
+   <line>...........*....</line>
+  </pattern>
+  <order>42</order>
+  <name>slantBox</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>.*...*...*...*..</line>
+   <line>*...*...*...*...</line>
+   <line>...*...*...*...*</line>
+   <line>..*...*...*...*.</line>
+   <line>.*...*...*...*..</line>
+   <line>*...*...*...*...</line>
+   <line>...*...*...*...*</line>
+   <line>..*...*...*...*.</line>
+   <line>.*...*...*...*..</line>
+   <line>*...*...*...*...</line>
+   <line>...*...*...*...*</line>
+   <line>..*...*...*...*.</line>
+   <line>.*...*...*...*..</line>
+   <line>*...*...*...*...</line>
+   <line>...*...*...*...*</line>
+   <line>..*...*...*...*.</line>
+  </pattern>
+  <order>43</order>
+  <name>slash2</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>...*.......*....</line>
+   <line>..*.......*.....</line>
+   <line>.*.......*......</line>
+   <line>*.......*.......</line>
+   <line>.......*.......*</line>
+   <line>......*.......*.</line>
+   <line>.....*.......*..</line>
+   <line>....*.......*...</line>
+   <line>...*.......*....</line>
+   <line>..*.......*.....</line>
+   <line>.*.......*......</line>
+   <line>*.......*.......</line>
+   <line>.......*.......*</line>
+   <line>......*.......*.</line>
+   <line>.....*.......*..</line>
+   <line>....*.......*...</line>
+  </pattern>
+  <order>44</order>
+  <name>bigSlash</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>****....****....</line>
+   <line>*..*....*..*....</line>
+   <line>*..*....*..*....</line>
+   <line>****....****....</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>****....****....</line>
+   <line>*..*....*..*....</line>
+   <line>*..*....*..*....</line>
+   <line>****....****....</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+  </pattern>
+  <order>45</order>
+  <name>boxes</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>..**......**....</line>
+   <line>.*..*....*..*...</line>
+   <line>*....*..*....*..</line>
+   <line>*....*..*....*..</line>
+   <line>.*..*....*..*...</line>
+   <line>..**......**....</line>
+   <line>................</line>
+   <line>................</line>
+   <line>..**......**....</line>
+   <line>.*..*....*..*...</line>
+   <line>*....*..*....*..</line>
+   <line>*....*..*....*..</line>
+   <line>.*..*....*..*...</line>
+   <line>..**......**....</line>
+   <line>................</line>
+   <line>................</line>
+  </pattern>
+  <order>46</order>
+  <name>circles</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>.**..**..**..**.</line>
+   <line>...*...*...*...*</line>
+   <line>*...*...*...*...</line>
+   <line>.**..**..**..**.</line>
+   <line>.**..**..**..**.</line>
+   <line>*...*...*...*...</line>
+   <line>...*...*...*...*</line>
+   <line>.**..**..**..**.</line>
+   <line>.**..**..**..**.</line>
+   <line>...*...*...*...*</line>
+   <line>*...*...*...*...</line>
+   <line>.**..**..**..**.</line>
+   <line>.**..**..**..**.</line>
+   <line>*...*...*...*...</line>
+   <line>...*...*...*...*</line>
+   <line>.**..**..**..**.</line>
+  </pattern>
+  <order>47</order>
+  <name>zigzag</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>................</line>
+   <line>*.*.*.*.*.*.*.*.</line>
+   <line>................</line>
+   <line>...*....*....*..</line>
+   <line>................</line>
+   <line>*.*.*.*.*.*.*.*.</line>
+   <line>................</line>
+   <line>...*....*....*..</line>
+   <line>................</line>
+   <line>*.*.*.*.*.*.*.*.</line>
+   <line>................</line>
+   <line>...*....*....*..</line>
+   <line>................</line>
+   <line>*.*.*.*.*.*.*.*.</line>
+   <line>................</line>
+   <line>...*....*....*..</line>
+  </pattern>
+  <order>48</order>
+  <name>lightMesh</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>...............*</line>
+   <line>..............*.</line>
+   <line>.............*..</line>
+   <line>............*...</line>
+   <line>...........*....</line>
+   <line>..........*.....</line>
+   <line>.........*......</line>
+   <line>........*.......</line>
+   <line>.......*........</line>
+   <line>......*.........</line>
+   <line>.....*..........</line>
+   <line>....*...........</line>
+   <line>...*............</line>
+   <line>..*.............</line>
+   <line>.*..............</line>
+   <line>*...............</line>
+  </pattern>
+  <order>49</order>
+  <name>hugeSlash</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>*...............</line>
+   <line>.*..............</line>
+   <line>..*.............</line>
+   <line>...*............</line>
+   <line>....*...........</line>
+   <line>.....*..........</line>
+   <line>......*.........</line>
+   <line>.......*........</line>
+   <line>........*.......</line>
+   <line>.........*......</line>
+   <line>..........*.....</line>
+   <line>...........*....</line>
+   <line>............*...</line>
+   <line>.............*..</line>
+   <line>..............*.</line>
+   <line>...............*</line>
+  </pattern>
+  <order>50</order>
+  <name>hugeSlash2</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>*.........*.....</line>
+   <line>.....*..........</line>
+   <line>..*.........*...</line>
+   <line>.......*........</line>
+   <line>....*.........*.</line>
+   <line>.*.......*......</line>
+   <line>......*.........</line>
+   <line>...*.......*....</line>
+   <line>........*.......</line>
+   <line>.....*.......*..</line>
+   <line>*.........*.....</line>
+   <line>.......*........</line>
+   <line>..*.........*...</line>
+   <line>.........*......</line>
+   <line>....*.........*.</line>
+   <line>...........*....</line>
+  </pattern>
+  <order>51</order>
+  <name>curve</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>....*....*....*.</line>
+   <line>..*.............</line>
+   <line>*.......*.......</line>
+   <line>.............*..</line>
+   <line>.......*........</line>
+   <line>............*...</line>
+   <line>.....*..........</line>
+   <line>...*.......*....</line>
+   <line>*...............</line>
+   <line>................</line>
+   <line>.........*......</line>
+   <line>................</line>
+   <line>......*........*</line>
+   <line>...*............</line>
+   <line>*............*..</line>
+   <line>..........*.....</line>
+  </pattern>
+  <order>52</order>
+  <name>curve2</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>...........*....</line>
+   <line>..........*.*...</line>
+   <line>.........*...*..</line>
+   <line>........*.....*.</line>
+   <line>.........*...*..</line>
+   <line>..........*.*...</line>
+   <line>...........*....</line>
+   <line>................</line>
+   <line>................</line>
+   <line>...*............</line>
+   <line>..*.*...........</line>
+   <line>.*...*..........</line>
+   <line>*.....*.........</line>
+   <line>.*...*..........</line>
+   <line>..*.*...........</line>
+   <line>...*............</line>
+  </pattern>
+  <order>53</order>
+  <name>diams</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>...*............</line>
+   <line>..*.*...........</line>
+   <line>.*...*..........</line>
+   <line>*.....*.........</line>
+   <line>.*...*..........</line>
+   <line>..*.*...........</line>
+   <line>...*............</line>
+  </pattern>
+  <order>54</order>
+  <name>sparsediam</name>
+ </custom-dither-pattern>
+ <custom-dither-pattern>
+  <pattern>
+   <line>.......*.......*</line>
+   <line>......*.........</line>
+   <line>.....*..........</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>.*..............</line>
+   <line>*...............</line>
+   <line>.......*.......*</line>
+   <line>..............*.</line>
+   <line>.............*..</line>
+   <line>................</line>
+   <line>................</line>
+   <line>................</line>
+   <line>.........*......</line>
+   <line>........*.......</line>
+  </pattern>
+  <order>55</order>
+  <name>rain</name>
+ </custom-dither-pattern>
+ <custom-line-style>
+  <pattern>***</pattern>
+  <order>1</order>
+  <name>solid</name>
+ </custom-line-style>
+ <custom-line-style>
+  <pattern>****..</pattern>
+  <order>2</order>
+  <name>dashed</name>
+ </custom-line-style>
+ <custom-line-style>
+  <pattern>*..</pattern>
+  <order>3</order>
+  <name>dots</name>
+ </custom-line-style>
+ <custom-line-style>
+  <pattern>***..*..</pattern>
+  <order>4</order>
+  <name>dashDot</name>
+ </custom-line-style>
+ <custom-line-style>
+  <pattern>**..</pattern>
+  <order>5</order>
+  <name>shortDash</name>
+ </custom-line-style>
+ <custom-line-style>
+  <pattern>****..**..</pattern>
+  <order>6</order>
+  <name>doubleDash</name>
+ </custom-line-style>
+ <custom-line-style>
+  <pattern>*...</pattern>
+  <order>7</order>
+  <name>hidden</name>
+ </custom-line-style>
+ <custom-line-style>
+  <pattern>***</pattern>
+  <order>8</order>
+  <name>thickLine</name>
+ </custom-line-style>
+</layer-properties>
diff --git a/sky130/sky130.lyt b/sky130/sky130.lyt
new file mode 100644
index 0000000..139f6cc
--- /dev/null
+++ b/sky130/sky130.lyt
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="utf-8"?>
+<technology>
+ <name>EFS8A</name>
+ <description>EFS8A 5-metals</description>
+ <layer-properties_file>EFS8A.lyp</layer-properties_file>
+ <add-other-layers>true</add-other-layers>
+ <layer-map>
+'66/15 : PY_SHORT	';
+'72/15 : M5_SHORT	';
+'81/14 : LDID	';
+'122/16 :PWELL_PIN	';
+'64/5  : NWELLLABEL	';
+'64/16 : NWELLPT ';
+'64/59 : PWELLLABEL	';
+'64/20 : NWELL	';
+'64/18 : DNWELL ';
+'65/20 : DIFF	';
+'65/44 : TAP	';
+'125/44 : LVTN	';
+'78/44 : HVTP	';
+'75/20 : HVI	';
+'80/20 : TUNM	';
+'66/20 : POLY	';
+'95/20 : NPC	';
+'94/20 : PSDM	';
+'93/44 : NSDM	';
+'66/44 : LICON1 ';
+'67/20 : LI1	';
+'67/16 : LI1T	';
+'67/5  : LI1P	';
+'67/44 : MCON	';
+'68/20 : MET1	';
+'68/16 : MET1T  ';
+'68/5  : MET1P  ';
+'68/44 : VIA1	';
+'69/20 : MET2	';
+'69/16 : MET2T  ';
+'69/5  : MET2P  ';
+'69/44 : VIA2	';
+'70/20 : MET3	';
+'70/16 : MET3T  ';
+'70/5  : MET3P  ';
+'70/44 : VIA3	';
+'71/20 : MET4	';
+'71/16 : MET4T  ';
+'71/5  : MET4P  ';
+'71/44 : VIA4	';
+'72/20 : MET5	';
+'72/16 : MET5T  ';
+'72/5  : MET5P  ';
+'76/20 : PAD	';
+'76/16 : PADT	';
+'76/5  : PADP	';
+'81/4  : BOUND  ';
+'83/44 : TEXT	';
+'18/20 : HVTR	';
+'92/44 : NCM	';
+'86/20 : RPM	';
+'61/20 : NSM	';
+'74/20 : RDL	';
+'74/21 : VHVI	';
+'11/44 : LDNTM  ';
+'125/20 : HVNTM  ';
+'85/44 : PMM	';
+'82/44 : PNP	';
+'82/64 : CAP	';
+'82/24 : IND	';
+'64/13 : PWRES  ';
+'66/13 : POLYRES';
+'65/13 : DIFFRES';
+'81/23 : DIODE  ';
+</layer-map>
+ <create-other-layers>true</create-other-layers>
+ <lef-def-import>
+  <read-all-layers>true</read-all-layers>
+  <layer-map/>
+  <produce-net-names>true</produce-net-names>
+  <net-property-name>#1</net-property-name>
+  <produce-cell-outlines>true</produce-cell-outlines>
+  <cell-outline-layer>OUTLINE</cell-outline-layer>
+  <produce-placement-blockages>true</produce-placement-blockages>
+  <placement-blockage-layer>PLACEMENT_BLK</placement-blockage-layer>
+  <produce-via-geometry>true</produce-via-geometry>
+  <via-geometry-suffix/>
+  <via-geometry-datatype>0</via-geometry-datatype>
+  <produce-pins>true</produce-pins>
+  <pins-suffix>.PIN</pins-suffix>
+  <pins-datatype>2</pins-datatype>
+  <produce-obstructions>true</produce-obstructions>
+  <obstructions-suffix>.OBS</obstructions-suffix>
+  <obstructions-datatype>3</obstructions-datatype>
+  <produce-blockages>true</produce-blockages>
+  <blockages-suffix>.BLK</blockages-suffix>
+  <blockages-datatype>4</blockages-datatype>
+  <produce-labels>true</produce-labels>
+  <labels-suffix>.LABEL</labels-suffix>
+  <labels-datatype>1</labels-datatype>
+  <produce-routing>true</produce-routing>
+  <routing-suffix/>
+  <routing-datatype>0</routing-datatype>
+ </lef-def-import>
+ <connectivity>
+  <connection>LI1,LICON1,SRCDRN</connection>
+  <connection>LI1,LICON1,POLY</connection>
+  <connection>MET1,MCON,LI1</connection>
+  <connection>MET1,VIA1,MET2</connection>
+  <connection>MET2,VIA2,MET3</connection>
+  <connection>MET3,VIA3,MET4</connection>
+  <connection>MET4,VIA4,MET5</connection>
+  <connection>LI1,LICON1,NWP</connection>
+  <symbols>SRCDRN='DIFF-POLY'</symbols>
+  <symbols>PTAP='TAP'</symbols>
+  <symbols>NWP='TAP+NWELL'</symbols>
+  <symbols>DIFF='65/20'</symbols>
+  <symbols>POLY='66/20'</symbols>
+  <symbols>LICON1='66/44'</symbols>
+  <symbols>LI1='67/20'</symbols>
+  <symbols>MCON='67/44'</symbols>
+  <symbols>MET1='68/20'</symbols>
+  <symbols>VIA1='68/44'</symbols>
+  <symbols>MET2='69/20'</symbols>
+  <symbols>VIA2='69/44'</symbols>
+  <symbols>MET3='70/20'</symbols>
+  <symbols>VIA3='70/44'</symbols>
+  <symbols>MET4='71/20'</symbols>
+  <symbols>VIA4='71/44'</symbols>
+  <symbols>MET5='72/20'</symbols>
+ </connectivity>
+</technology>
diff --git a/sky130/sky130.magicrc b/sky130/sky130.magicrc
new file mode 100644
index 0000000..feaf6b5
--- /dev/null
+++ b/sky130/sky130.magicrc
@@ -0,0 +1,114 @@
+###
+###	Source file sky130.magicrc
+###	Process this file with the m4 processor
+###
+puts stdout "Sourcing design .magicrc for technology TECHNAME ..."
+
+# Put grid on 0.005 pitch.  This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+    scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+    set PDKPATH "STAGING_PATH/TECHNAME"
+}
+
+# loading technology
+#ifdef FULLTECH
+tech load $PDKPATH/MAGIC_CURRENT/TECHNAME-F.tech
+#else
+tech load $PDKPATH/MAGIC_CURRENT/TECHNAME.tech
+#endif
+
+# load device generator
+source $PDKPATH/MAGIC_CURRENT/TECHNAME.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/MAGIC_CURRENT/TECHNAME-BindKeys
+
+# set units to lambda grid 
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+   set MAGTYPE maglef
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr_base
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr_rf
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr_rf2
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu130
+} else {
+    addpath ${PDKPATH}/libs.ref/sky130_fd_pr_base/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_pr_rf/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_pr_rf2/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_osu130/${MAGTYPE}
+}
+
+# add path to GDS cells
+#ifdef FULLTECH
+if {[file isdir ${PDKPATH}/libs.ref/gds}]} {
+    path cell ${PDKPATH}/libs.ref/gds/sky130_fd_pr_base
+    path cell ${PDKPATH}/libs.ref/gds/sky130_fd_pr_rf
+    path cell ${PDKPATH}/libs.ref/gds/sky130_fd_pr_rf2
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_io
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_hd
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_hdll
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_hs
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_hvl
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_lp
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_ls
+    path cell +${PDKPATH}/libs.ref/gds/sky130_fd_sc_ms
+    path cell +${PDKPATH}/libs.ref/gds/sky130_osu130
+} else {
+    path cell ${PDKPATH}/libs.ref/sky130_fd_pr_base/gds
+    path cell ${PDKPATH}/libs.ref/sky130_fd_pr_rf/gds
+    path cell ${PDKPATH}/libs.ref/sky130_fd_pr_rf2/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_io/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_sc_hd/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_sc_hdll/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_sc_hs/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_sc_hvl/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_sc_lp/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_sc_ls/gds
+    path cell +${PDKPATH}/libs.ref/sky130_fd_sc_ms/gds
+    path cell +${PDKPATH}/libs.ref/sky130_osu130/gds
+}
+#endif (FULLTECH)
+
+# add path to IP from catalog.  This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space.  Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/sky130/sky130.par b/sky130/sky130.par
new file mode 100644
index 0000000..afd9190
--- /dev/null
+++ b/sky130/sky130.par
@@ -0,0 +1,108 @@
+# TECHNAME.par --- Parameter file for GrayWolf
+# NOTE:  all distance units are in centimicrons unless otherwise stated
+# WARNING: this is NOT tcl syntax! No Comments on end of actual data line.
+# The vast majority of quantities here are not used (read instead from techLEF, etc.)
+
+RULES
+    # values are resistance in ohms/sq and capacitance in fF/um^2
+    # TODO: properly pick directions
+    layer metal1 0.105 0.0001 horizontal
+    layer metal2 0.105 0.0001 vertical
+    layer metal3 0.105 0.0001 horizontal
+#ifdef METAL5
+    layer metal4 0.105 0.0001 vertical
+    layer metal5 0.105 0.0001 horizontal
+#endif
+
+    via via12 metal1 metal2
+    via via23 metal2 metal3
+#ifdef METAL5
+    via via34 metal3 metal4
+    via via45 metal4 metal5
+#endif
+
+              # 0.5 um
+    width metal1 50
+    width metal2 60
+              # 0.6 um
+    width metal3 60
+#ifdef METAL5
+    width metal4 60
+    width metal5 60
+#endif
+
+    # TODO verify these two numbers
+    width via12 50
+    width via23 50
+#ifdef METAL5
+    width via34 50
+    width via45 50
+#endif
+
+    # Set spacing = track pitch - width, so that GrayWolf places pins
+    # on the right pitch.
+    # Pitches are (in um):
+    # metal1 = 200,  metal2 = 160,  metal3 = 200,  metal4 = 320
+## pitch m1: 1.3um  m2: 1.4um  m3: 1.3um
+## width m1: 0.5um  m2: 0.6um  m3: 0.6um
+## space     0.8        0.8        0.7     (pitch calc)
+## fab-space 0.45       0.5        0.6
+
+    spacing metal1 metal1 80
+    spacing metal2 metal2 80
+    spacing metal3 metal3 80
+#ifdef METAL5
+    spacing metal4 metal4 80
+    spacing metal5 metal5 80
+#endif
+
+    # (WAS:) Stacked vias allowed
+    # spacing via12 via23 0
+
+    # To disable Stacked?: give non-zero spacing (centimicrons = 10 nanometer = 1/100 of micron)
+    # TODO need real value here:
+    spacing via12 via23 0
+#ifdef METAL5
+    spacing via23 via34 0
+    spacing via34 via45 0
+#endif
+
+                       # .2um .15um
+    overhang via12 metal1 20
+    overhang via12 metal2 15
+
+    overhang via23 metal2 20
+    overhang via23 metal3 15
+
+#ifdef METAL5
+    overhang via34 metal3 14
+    overhang via34 metal4 16
+    overhang via45 metal4 14
+    overhang via45 metal5 16
+#endif
+ENDRULES
+
+*vertical_wire_weight : 1.0
+*vertical_path_weight : 1.0
+*padspacing           : variable
+*rowSep		      : 0.0   0
+# min pitch of m1,m2,m3 (FIXME):
+*track.pitch	      : 130
+*graphics.wait        : off
+*last_chance.wait     : off
+*random.seed	      : 12345
+# TODO: proper track.pitch number above, plus feedThruWidth below
+
+TWMC*chip.aspect.ratio : 1.0
+
+# FIXME:  Change width to width of minimum fill cell
+TWSC*feedThruWidth    : 280 layer 1
+TWSC*do.global.route  : on
+TWSC*ignore_feeds     : true
+TWSC*call_row_evener  : true
+TWSC*even_rows_maximally : true
+# TWSC*no.graphics    : on
+
+GENR*row_to_tile_spacing: 1
+# GENR*numrows		: 6
+GENR*flip_alternate_rows : 1
diff --git a/sky130/sky130.sh b/sky130/sky130.sh
new file mode 100644
index 0000000..9d8e6ac
--- /dev/null
+++ b/sky130/sky130.sh
@@ -0,0 +1,93 @@
+#!/bin/tcsh
+#---------------------------------------------------------------
+# Shell script setting up all variables used by the qflow scripts
+# for this project
+#---------------------------------------------------------------
+
+# The LEF file containing standard cell macros
+
+#ifdef EF_FORMAT
+set leffile=STAGING_PATH/TECHNAME/libs.ref/lef/LIBRARY/LIBRARY.lef
+#else (!EF_FORMAT)
+set leffile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/lef/LIBRARY.lef
+#endif (!EF_FORMAT)
+
+# The SPICE netlist containing subcell definitions for all the standard cells
+#ifdef EF_FORMAT
+set spicefile=STAGING_PATH/TECHNAME/libs.ref/spi/LIBRARY/LIBRARY.spi
+#else (!EF_FORMAT)
+set spicefile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/spice/LIBRARY.spi
+#endif (!EF_FORMAT)
+
+# The liberty format file containing standard cell timing and function information
+#ifdef EF_FORMAT
+set libertyfile=STAGING_PATH/TECHNAME/libs.ref/lib/LIBRARY/LIBRARY__ff_n40C_1v95.lib
+#else (!EF_FORMAT)
+set libertyfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/lib/LIBRARY__ff_n40C_1v95.lib
+#endif (!EF_FORMAT)
+
+# If there is another LEF file containing technology information
+# that is separate from the file containing standard cell macros,
+# set this.  Otherwise, leave it defined as an empty string.
+
+#ifdef METAL5
+#ifdef EF_FORMAT
+set techleffile=STAGING_PATH/TECHNAME/libs.ref/techLEF/LIBRARY/LIBRARY_tech.lef
+#else (!EF_FORMAT)
+set techleffile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/techlef/LIBRARY_tech.lef
+#endif (!EF_FORMAT)
+#else
+# NOTE:  There is no technology LEF file for the 3-metal stack!
+#endif
+
+# All cells below should be the lowest output drive strength value,
+# if the standard cell set has multiple cells with different drive
+# strengths.  Comment out any cells that do not exist.
+
+set bufcell=LIBRARY__buf_1	;# Minimum drive strength buffer cell
+set bufpin_in=A			;# Name of input port to buffer cell
+set bufpin_out=X		;# Name of output port to buffer cell
+set clkbufcell=LIBRARY__clkbuf_1	;# Minimum drive strength buffer cell
+set clkbufpin_in=A		;# Name of input port to buffer cell
+set clkbufpin_out=X		;# Name of output port to buffer cell
+
+set fillcell=LIBRARY__fill_	;# Spacer (filler) cell (prefix, if more than one)
+set decapcell=LIBRARY__decap_	;# Decap (filler) cell (prefix, if more than one)
+set antennacell=LIBRARY__diode_	;# Antenna (filler) cell (prefix, if more than one)
+set antennapin_in=vpb		;# Antenna cell input connection
+set bodytiecell=LIBRARY__tapvpwrvgnd_	;# Body tie (filler) cell (prefix, if more than one)
+
+# yosys tries to eliminate use of these; depends on source .v
+set tiehi="LIBRARY__conb_1"	;# Cell to connect to power, if one exists
+set tiehipin_out="HI"		;# Output pin name of tiehi cell, if it exists
+set tielo="LIBRARY__conb_1"	;# Cell to connect to ground, if one exists
+set tielopin_out="LO"		;# Output pin name of tielo cell, if it exists
+
+set gndnet="vgnd,vnb"		;# Name used for ground pins and taps in standard cells
+set vddnet="vpwr,vpb"		;# Name used for power pins and taps in standard cells
+
+set separator=""		;# Separator between gate names and drive strengths
+set techfile=STAGING_PATH/TECHNAME/MAGIC_CURRENT/TECHNAME.tech	;# magic techfile
+set magicrc=STAGING_PATH/TECHNAME/MAGIC_CURRENT/TECHNAME.magicrc	;# magic startup script
+set magic_display="XR" 	;# magic display, defeat display query and OGL preference
+set netgen_setup=STAGING_PATH/TECHNAME/libs.tech/netgen/TECHNAME_setup.tcl	;# netgen setup file for LVS
+#ifdef EF_FORMAT
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/gds/LIBRARY/LIBRARY.gds	;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/verilog/LIBRARY/LIBRARY.v	;# Verilog models of standard cells
+#else (!EF_FORMAT)
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/gds/LIBRARY.gds	;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/LIBRARY/verilog/LIBRARY.v	;# Verilog models of standard cells
+#endif (!EF_FORMAT)
+
+# Set a conditional default in the project_vars.sh file for this process
+set postproc_options="-anchors"
+#ifdef METAL5
+# Normally one does not want to use the top metal for signal routing
+set route_layers = 5
+#else
+set route_layers = 3
+#endif
+set fill_ratios="0,70,10,20"
+set fanout_options="-l 200 -c 20"
+set addspacers_options="-stripe 2.5 50.0 PG"
+set xspice_options="-io_time=500p -time=50p -idelay=5p -odelay=50p -cload=250f"
diff --git a/sky130/sky130.tcl b/sky130/sky130.tcl
new file mode 100644
index 0000000..684aee5
--- /dev/null
+++ b/sky130/sky130.tcl
@@ -0,0 +1,5596 @@
+###
+###     Source file sky130.tcl
+###     Process this file with the preprocessor script
+###
+#-----------------------------------------------------
+# Magic/TCL design kit for SKYWATER TECHNAME
+#-----------------------------------------------------
+# Tim Edwards
+# Revision 0	PRE-ALPHA   3/21/2019
+#-----------------------------------------------------
+
+set TECHPATH STAGING_PATH
+if [catch {set PDKPATH}] {set PDKPATH ${TECHPATH}/TECHNAME}
+set PDKNAME TECHNAME
+# "sky130" is the namespace used for all devices
+set PDKNAMESPACE sky130
+puts stdout "Loading TECHNAME Device Generator Menu ..."
+
+# Initialize toolkit menus to the wrapper window
+
+global Opts
+namespace eval sky130 {}
+
+# Set the window callback
+if [catch {set Opts(callback)}] {set Opts(callback) ""}
+set Opts(callback) [subst {sky130::addtechmenu \$framename; $Opts(callback)}]
+
+# if {![info exists Opts(cmdentry)]} {set Opts(cmdentry) 1}
+
+# Set options specific to this PDK
+set Opts(hidelocked) 1
+set Opts(hidespecial) 1
+
+# Create new "tool" proc that doesn't have the netlist tool.
+proc magic::nexttool {} {
+   global Opts
+
+   # Don't attempt to switch tools while a selection drag is active
+   if {$Opts(motion) == {}} {
+      switch $Opts(tool) {
+         box { magic::tool wiring }
+         wiring { magic::tool pick }
+         default { magic::tool box }
+      }
+   }
+}
+
+# This shoule be part of sitedef. . .
+macro space magic::nexttool
+
+# Wrap the closewrapper procedure so that closing the last
+# window is equivalent to quitting.
+if {[info commands closewrapper] == "closewrapper"} {
+   rename closewrapper closewrapperonly
+   proc closewrapper { framename } {
+      if {[llength [windownames all]] <= 1} {
+         magic::quit
+      } else {
+         closewrapperonly $framename
+      }
+   }
+}
+
+# Remove maze router layers from the toolbar by locking them
+tech lock fence,magnet,rotate
+
+namespace eval sky130 {
+    namespace path {::tcl::mathop ::tcl::mathfunc}
+
+    set ruleset [dict create]
+
+    # Process DRC rules (magic style)
+
+    dict set ruleset poly_surround    0.08      ;# Poly surrounds contact
+    dict set ruleset diff_surround    0.06      ;# Diffusion surrounds contact
+    dict set ruleset gate_to_diffcont 0.145     ;# Gate to diffusion contact center
+    dict set ruleset gate_to_polycont 0.275     ;# Gate to poly contact center
+    dict set ruleset gate_extension   0.13      ;# Poly extension beyond gate
+    dict set ruleset diff_extension   0.29      ;# Diffusion extension beyond gate
+    dict set ruleset contact_size     0.17      ;# Minimum contact size
+    dict set ruleset via_size         0.17      ;# Minimum via size
+    dict set ruleset metal_surround   0.08      ;# Local interconnect overlaps contact
+    dict set ruleset sub_surround     0.18      ;# Sub/well surrounds diffusion
+    dict set ruleset diff_spacing     0.28      ;# Diffusion spacing rule
+    dict set ruleset poly_spacing     0.21      ;# Poly spacing rule
+    dict set ruleset diff_poly_space  0.075     ;# Diffusion to poly spacing rule
+    dict set ruleset diff_gate_space  0.20      ;# Diffusion to gate poly spacing rule
+    dict set ruleset metal_spacing    0.23      ;# Local interconnect spacing rule
+    dict set ruleset mmetal_spacing   0.14      ;# Metal spacing rule (above local interconnect)
+    dict set ruleset res_to_cont      0.20      ;# resistor to contact center
+    dict set ruleset res_diff_space   0.20      ;# resistor to guard ring
+}
+
+#-----------------------------------------------------
+# magic::addtechmenu
+#-----------------------------------------------------
+
+proc sky130::addtechmenu {framename} {
+   global Winopts Opts
+   
+   # Check for difference between magic 8.1.125 and earlier, and 8.1.126 and later
+   if {[catch {${framename}.titlebar cget -height}]} {
+      set layoutframe ${framename}.pane.top
+   } else {
+      set layoutframe ${framename}
+   }
+
+   # List of devices is long.  Divide into two sections for active and passive deivces
+   magic::add_toolkit_menu $layoutframe "Devices 1" pdk1
+
+   magic::add_toolkit_command $layoutframe "nmos (MOSFET)" \
+	    "magic::gencell sky130::nshort" pdk1
+   magic::add_toolkit_command $layoutframe "pmos (MOSFET)" \
+	    "magic::gencell sky130::pshort" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+   magic::add_toolkit_command $layoutframe "n-diode" \
+	    "magic::gencell sky130::ndiode" pdk1
+   magic::add_toolkit_command $layoutframe "p-diode" \
+	    "magic::gencell sky130::pdiode" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+   magic::add_toolkit_command $layoutframe "MOS varactor" \
+	    "magic::gencell sky130::xcnwvc" pdk1
+   magic::add_toolkit_separator	$layoutframe pdk1
+
+   magic::add_toolkit_command $layoutframe "NPN 1x1" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_npn_1x1" pdk1
+   magic::add_toolkit_command $layoutframe "NPN 1x2" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_npn_1x2" pdk1
+   magic::add_toolkit_command $layoutframe "PNP 5x" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_pnp5x" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+
+   magic::add_toolkit_command $layoutframe "balun" \
+	    "magic::gencell sky130::balun" pdk1
+   magic::add_toolkit_command $layoutframe "inductor 011" \
+	    "magic::gencell sky130::xind4_011" pdk1
+   magic::add_toolkit_command $layoutframe "inductor 02" \
+	    "magic::gencell sky130::xind4_02" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+
+   magic::add_toolkit_command $layoutframe "substrate contact (1.8V)" \
+	    "sky130::subconn_draw" pdk1
+   magic::add_toolkit_command $layoutframe "substrate contact (5.0V)" \
+	    "sky130::mvsubconn_draw" pdk1
+   magic::add_toolkit_command $layoutframe "deep n-well region" \
+	    "sky130::deep_nwell_draw" pdk1
+   magic::add_toolkit_command $layoutframe "mcon" \
+	    "sky130::mcon_draw" pdk1
+   magic::add_toolkit_command $layoutframe "via1" \
+	    "sky130::via1_draw" pdk1
+   magic::add_toolkit_command $layoutframe "via2" \
+	    "sky130::via2_draw" pdk1
+#ifdef METAL5
+   magic::add_toolkit_command $layoutframe "via3" \
+	    "sky130::via3_draw" pdk1
+   magic::add_toolkit_command $layoutframe "via4" \
+	    "sky130::via4_draw" pdk1
+#endif (METAL5)
+   
+
+   magic::add_toolkit_menu $layoutframe "Devices 2" pdk2
+
+   magic::add_toolkit_command $layoutframe "mrdn (1.8V) - 120 Ohm/sq" \
+	    "magic::gencell sky130::mrdn" pdk2
+   magic::add_toolkit_command $layoutframe "mrdp (1.8V) - 197 Ohm/sq" \
+	    "magic::gencell sky130::mrdp" pdk2
+   magic::add_toolkit_command $layoutframe "mrdn_hv (5.0V) - 114 Ohm/sq" \
+	    "magic::gencell sky130::mrdn_hv" pdk2
+   magic::add_toolkit_command $layoutframe "mrdp_hv (5.0V) - 191 Ohm/sq" \
+	    "magic::gencell sky130::mrdp_hv" pdk2
+
+   magic::add_toolkit_command $layoutframe "mrp1 - 48.2 Ohm/sq" \
+	    "magic::gencell sky130::mrp1" pdk2
+   magic::add_toolkit_command $layoutframe "xhrpoly - 319.8 Ohm/sq" \
+	    "magic::gencell sky130::xhrpoly" pdk2
+   magic::add_toolkit_command $layoutframe "uhrpoly - 2000 Ohm/sq" \
+	    "magic::gencell sky130::uhrpoly" pdk2
+   magic::add_toolkit_command $layoutframe "xpwres - 3050 Ohm/sq" \
+	    "magic::gencell sky130::xpwres" pdk2
+   magic::add_toolkit_separator	$layoutframe pdk2
+
+   magic::add_toolkit_command $layoutframe "mrl1 - 12.2 Ohm/sq" \
+	    "magic::gencell sky130::mrl1" pdk2
+   magic::add_toolkit_command $layoutframe "mrm1 - 125 mOhm/sq" \
+	    "magic::gencell sky130::mrm1" pdk2
+   magic::add_toolkit_command $layoutframe "mrm2 - 125 mOhm/sq" \
+	    "magic::gencell sky130::mrm2" pdk2
+   magic::add_toolkit_command $layoutframe "mrm3 - 47 mOhm/sq" \
+	    "magic::gencell sky130::mrm3" pdk2
+#ifdef METAL5
+   magic::add_toolkit_command $layoutframe "mrm4 - 47 mOhm/sq" \
+	    "magic::gencell sky130::mrm4" pdk2
+   magic::add_toolkit_command $layoutframe "mrm5 - 29 mOhm/sq" \
+	    "magic::gencell sky130::mrm5" pdk2
+#endif (METAL5)
+
+#ifdef MIM
+   magic::add_toolkit_command $layoutframe "xcmimc1 - 1fF/um^2 MiM cap" \
+	    "magic::gencell sky130::xcmimc1" pdk2
+   magic::add_toolkit_command $layoutframe "xcmimc2 - 1fF/um^2 MiM cap" \
+	    "magic::gencell sky130::xcmimc2" pdk2
+#endif (MIM)
+   magic::add_toolkit_separator	$layoutframe pdk2
+
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 li/m5 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 li/m3/m5 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 m4 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 p/m4 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield" pdk2
+   # magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 p/m5 shield" \
+   #	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 4.4x4.6 li/m3/m5 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 6.8x6.1 li/m4 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 6.8x6.1 p/m4 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 8.6x7.9 li/m3/m5 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 4.2x2 nhvnat" \
+	    "magic::gencell sky130::sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 li/m3 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 m3 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield" pdk2
+   # magic::add_toolkit_command $layoutframe "vpp 1.8x1.8 li shield" \
+   #	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield" pdk2
+   # magic::add_toolkit_command $layoutframe "vpp 1.8x1.8 m3 shield" \
+   #	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 4.4x4.6 li/m3 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 4.4x4.6 m3 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 8.6x7.9 li/m3 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 8.6x7.9 m3 shield" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp2" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp2" pdk2
+   magic::add_toolkit_command $layoutframe "vpp2 nwell" \
+	    "magic::gencell sky130::sky130_fd_pr_rf_xcmvpp2_nwell" pdk2
+
+   ${layoutframe}.titlebar.mbuttons.drc.toolmenu add command -label "DRC Routing" -command {drc style drc(routing)}
+
+   # Add command entry window by default if enabled
+   if {[info exists Opts(cmdentry)]} {
+      set Winopts(${framename},cmdentry) $Opts(cmdentry)
+   } else {
+      set Winopts(${framename},cmdentry) 0
+   }
+   if {$Winopts(${framename},cmdentry) == 1} {
+      addcommandentry $framename
+   }
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mcon_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.17} {
+      puts stderr "Mcon width must be at least 0.17um"
+      return
+   }
+   if {$h < 0.17} {
+      puts stderr "Mcon height must be at least 0.17um"
+      return
+   }
+   paint lic
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m1
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint li
+   box grow e -0.05um
+   box grow w -0.05um
+}
+
+proc sky130::via1_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.26} {
+      puts stderr "Via1 width must be at least 0.26um"
+      return
+   }
+   if {$h < 0.26} {
+      puts stderr "Via1 height must be at least 0.26um"
+      return
+   }
+   paint via1
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m2
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m1
+   box grow e -0.05um
+   box grow w -0.05um
+}
+
+proc sky130::via2_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.28} {
+      puts stderr "Via2 width must be at least 0.28um"
+      return
+   }
+   if {$h < 0.28} {
+      puts stderr "Via2 height must be at least 0.28um"
+      return
+   }
+   paint via2
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m2
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m3
+   box grow e -0.05um
+   box grow w -0.05um
+}
+
+#ifdef METAL5
+proc sky130::via3_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.32} {
+      puts stderr "Via3 width must be at least 0.32um"
+      return
+   }
+   if {$h < 0.32} {
+      puts stderr "Via3 height must be at least 0.32um"
+      return
+   }
+   paint via3
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m4
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m3
+   box grow e -0.05um
+   box grow w -0.05um
+}
+
+proc sky130::via4_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 1.18} {
+      puts stderr "Via3 width must be at least 1.18um"
+      return
+   }
+   if {$h < 1.18} {
+      puts stderr "Via3 height must be at least 1.18um"
+      return
+   }
+   paint via4
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m5
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m4
+   box grow e -0.05um
+   box grow w -0.05um
+}
+#endif (METAL5)
+
+proc sky130::subconn_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.17} {
+      puts stderr "Substrate tap width must be at least 0.17um"
+      return
+   }
+   if {$h < 0.17} {
+      puts stderr "Substrate tap height must be at least 0.17um"
+      return
+   }
+   paint nsc
+   box grow c 0.1um
+   paint nsd
+   box grow c -0.1um
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mvsubconn_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.17} {
+      puts stderr "Substrate tap width must be at least 0.17um"
+      return
+   }
+   if {$h < 0.17} {
+      puts stderr "Substrate tap height must be at least 0.17um"
+      return
+   }
+   paint mvnsc
+   box grow c 0.1um
+   paint mvnsd
+   box grow c -0.1um
+}
+
+#----------------------------------------------------------------
+
+proc sky130::deep_nwell_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 3.0} {
+      puts stderr "Deep-nwell region width must be at least 3.0um"
+      return
+   }
+   if {$h < 3.0} {
+      puts stderr "Deep-nwell region height must be at least 3.0um"
+      return
+   }
+   suspendall
+   tech unlock *
+   paint dnwell
+   pushbox
+   pushbox
+   box grow c 0.4um
+   paint nwell
+   box grow c -1.43um
+   erase nwell
+   popbox
+   box grow c 0.03um
+
+   pushbox
+   box width 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow n -0.3um
+   box grow s -0.3um
+   paint nsc
+   popbox
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   pushbox
+   box height 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow e -0.3um
+   box grow w -0.3um
+   paint nsc
+   popbox
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   pushbox
+   box move n [box height]i
+   box height 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow e -0.3um
+   box grow w -0.3um
+   paint nsc
+   popbox
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   pushbox
+   box move e [box width]i
+   box width 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow n -0.3um
+   box grow s -0.3um
+   paint nsc
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   popbox
+   tech revert
+   resumeall
+}
+
+#----------------------------------------------------------------
+
+proc sky130::res_recalc {field parameters} {
+    set snake 0
+    set sterm 0.0
+    set caplen 0
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set val [magic::spice2float $val]
+    set l [magic::spice2float $l]
+    set w [magic::spice2float $w]
+
+    if {$snake == 0} {
+	# Straight resistor calculation
+	switch  $field {
+	    val { set l [expr ($val * ($w - $dw) - (2 * $term)) / $rho]
+		  set w [expr ((2 * $term + $l * $rho) / $val) + $dw]
+		}
+	    w   { set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+		  set l [expr ($val * ($w - $dw) - (2 * $term)) / $rho]
+		}
+	    l   { set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+		  set w [expr ((2 * $term + $l * $rho) / $val) + $dw]
+		}
+	}
+    } else {
+        set term [expr $term + $sterm]
+	# Snake resistor calculation
+	switch  $field {
+	    val { set l [expr (($val - $rho * ($nx - 1)) * ($w - $dw) \
+			- (2 * $term) - ($rho * $caplen * ($nx - 1))) \
+			/ ($rho * $nx)]
+
+		  set w [expr ((2 * $term + $l * $rho * $nx \
+			+ $caplen * $rho * ($nx - 1)) \
+			/ ($val - $rho * ($nx - 1))) + $dw]
+		}
+	    w   { set val [expr $rho * ($nx - 1) + ((2 * $term) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+
+		  set l [expr (($val - $rho * ($nx - 1)) * ($w - $dw) \
+			- (2 * $term) - ($rho * $caplen * ($nx - 1))) \
+			/ ($rho * $nx)]
+		}
+	    l   { set val [expr $rho * ($nx - 1) + ((2 * $term) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+
+		  set w [expr ((2 * $term + $l * $rho * $nx \
+			+ $caplen * $rho * ($nx - 1)) \
+			/ ($val - $rho * ($nx - 1))) + $dw]
+		}
+	}
+    }
+
+    set val [magic::3digitpastdecimal $val]
+    set w [magic::3digitpastdecimal $w]
+    set l [magic::3digitpastdecimal $l]
+
+    dict set parameters val $val
+    dict set parameters w $w
+    dict set parameters l $l
+
+    return $parameters
+}
+
+#----------------------------------------------------------------
+# Drawn diode routines
+#----------------------------------------------------------------
+
+proc sky130::diode_recalc {field parameters} {
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    switch  $field {
+	area { puts stdout "area changed" }
+	peri { puts stdout "perimeter changed" }
+	w   { puts stdout "width changed" }
+	l   { puts stdout "length changed" }
+    }
+    dict set parameters area $area
+    dict set parameters peri $peri
+    dict set parameters w $w
+    dict set parameters l $l
+}
+
+#----------------------------------------------------------------
+# diode: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::diode_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w -
+	    peri {
+		# Length, width, and perimeter are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    area {
+		# area also converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e12]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+                # Convert m to ny
+		dict set pdkparams ny $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+# diode: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::diode_dialog {device parameters} {
+    # Editable fields:      w, l, area, perim, nx, ny
+
+    magic::add_entry area "Area (um^2)" $parameters
+    magic::add_entry peri "Perimeter (um)" $parameters
+    sky130::compute_aptot $parameters
+    magic::add_message atot "Total area (um^2)" $parameters
+    magic::add_message ptot "Total perimeter (um)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry ny "Y Repeat" $parameters
+
+    if {[dict exists $parameters compatible]} {
+       set sellist [dict get $parameters compatible]
+       magic::add_selectlist gencell "Device type" $sellist $parameters $device
+    }
+
+    if {[dict exists $parameters doverlap]} {
+	magic::add_checkbox doverlap "Overlap at end contact" $parameters
+    }
+    if {[dict exists $parameters elc]} {
+        magic::add_checkbox elc "Add left end contact" $parameters
+    }
+    if {[dict exists $parameters erc]} {
+        magic::add_checkbox erc "Add right end contact" $parameters
+    }
+    if {[dict exists $parameters etc]} {
+        magic::add_checkbox etc "Add top end contact" $parameters
+    }
+    if {[dict exists $parameters ebc]} {
+        magic::add_checkbox ebc "Add bottom end contact" $parameters
+    }
+
+    if {[dict exists $parameters guard]} {
+        magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    }
+    if {[dict exists $parameters glc]} {
+        magic::add_checkbox glc "Add left guard ring contact" $parameters
+    }
+    if {[dict exists $parameters grc]} {
+        magic::add_checkbox grc "Add right guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+        magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gbc]} {
+        magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+
+    magic::add_dependency sky130::diode_recalc $device sky130 l w area peri
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+}
+
+#----------------------------------------------------------------
+# Diode total area and perimeter computation
+#----------------------------------------------------------------
+
+proc sky130::compute_aptot {parameters} {
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set area [magic::spice2float $area]
+    set area [magic::3digitpastdecimal $area]
+    set peri [magic::spice2float $peri]
+    set peri [magic::3digitpastdecimal $peri]
+
+    # Compute total area
+    catch {set magic::atot_val [expr ($area * $nx * $ny)]}
+    # Compute total perimeter
+    catch {set magic::ptot_val [expr ($peri * $nx * $ny)]}
+}
+
+#----------------------------------------------------------------
+# diode: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::diode_check {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l] 
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w] 
+
+    set area [magic::spice2float $area]
+    set area [magic::3digitpastdecimal $area] 
+    set peri [magic::spice2float $peri]
+    set peri [magic::3digitpastdecimal $peri] 
+
+    if {$l == 0} {
+        # Calculate L from W and area
+	set l [expr ($area / $w)]
+	dict set parameters l [magic::float2spice $l]
+    } elseif {$w == 0} {
+        # Calculate W from L and area
+	set w [expr ($area / $l)]
+	dict set parameters w [magic::float2spice $w]
+    }
+    if {$w < $wmin} {
+	puts stderr "Diode width must be >= $wmin"
+	dict set parameters w $wmin
+    } 
+    if {$l < $lmin} {
+	puts stderr "Diode length must be >= $lmin"
+	dict set parameters l $lmin
+    } 
+    # Calculate area and perimeter from L and W
+    set area [expr ($l * $w)]
+    dict set parameters area [magic::float2spice $area]
+    set peri [expr (2 * ($l + $w))]
+    dict set parameters peri [magic::float2spice $peri]
+    sky130::compute_aptot $parameters
+
+    return $parameters
+}
+
+#------------------------------------------------------------------
+# NOTE:  ndiode_lvt, ndiode_native, pdiode_lvt, and pdiode_hvt are
+# all considered parasitic diodes.  They may be generated by
+# invoking the build procedure on the command line.  To enable them
+# in the PDK, add them to the appropriate compatible {} list.
+#------------------------------------------------------------------
+
+proc sky130::ndiode_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	compatible {ndiode ndiode_h} full_metal 1}
+}
+
+proc sky130::ndiode_lvt_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	full_metal 1}
+}
+
+proc sky130::pdiode_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	compatible {pdiode pdiode_h} full_metal 1}
+}
+
+proc sky130::pdiode_lvt_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	full_metal 1}
+}
+
+proc sky130::pdiode_hvt_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	full_metal 1}
+}
+
+proc sky130::ndiode_h_defaults {} {
+    return {w 0.45 l 0.45 area 0.2024 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	compatible {ndiode ndiode_h} full_metal 1}
+}
+
+proc sky130::ndiode_native_defaults {} {
+    return {w 0.45 l 0.45 area 0.2024 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	full_metal 1}
+}
+
+proc sky130::pdiode_h_defaults {} {
+    return {w 0.45 l 0.45 area 0.2024 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	compatible {pdiode pdiode_h} full_metal 1}
+}
+
+#----------------------------------------------------------------
+
+proc sky130::ndiode_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::ndiode_lvt_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::pdiode_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::pdiode_lvt_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::pdiode_hvt_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::ndiode_h_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::ndiode_native_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::pdiode_h_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::ndiode_dialog {parameters} {
+    sky130::diode_dialog ndiode $parameters
+}
+
+proc sky130::ndiode_lvt_dialog {parameters} {
+    sky130::diode_dialog ndiode_lvt $parameters
+}
+
+proc sky130::pdiode_dialog {parameters} {
+    sky130::diode_dialog pdiode $parameters
+}
+
+proc sky130::pdiode_lvt_dialog {parameters} {
+    sky130::diode_dialog pdiode_lvt $parameters
+}
+
+proc sky130::pdiode_hvt_dialog {parameters} {
+    sky130::diode_dialog pdiode_hvt $parameters
+}
+
+proc sky130::ndiode_h_dialog {parameters} {
+    sky130::diode_dialog ndiode_h $parameters
+}
+
+proc sky130::ndiode_native_dialog {parameters} {
+    sky130::diode_dialog ndiode_native $parameters
+}
+
+proc sky130::pdiode_h_dialog {parameters} {
+    sky130::diode_dialog pdiode_h $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::ndiode_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::ndiode_lvt_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::pdiode_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::pdiode_lvt_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::pdiode_hvt_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::ndiode_h_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::ndiode_native_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::pdiode_h_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+#----------------------------------------------------------------
+# Diode: Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::diode_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set dev_surround 0
+    set dev_sub_type ""
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # If there is no end_sub_surround, set it to sub_surround
+    if {![dict exists $parameters end_sub_surround]} {
+	set end_sub_surround $sub_surround
+    }
+
+    # Draw the device
+    pushbox
+    box size 0 0
+
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    # Calculate ring size (measured to contact center)
+    set gx [+ $w [* 2.0 [+ $dev_spacing $dev_surround]] $contact_size]
+    set gy [+ $l [* 2.0 [+ $dev_spacing $dev_surround]] $contact_size]
+
+    # Draw the ring first, because diode may occupy well/substrate plane
+    set guardparams $parameters
+    dict set guardparams plus_diff_type $end_type
+    dict set guardparams plus_contact_type $end_contact_type
+    dict set guardparams diff_surround $end_surround
+    dict set guardparams sub_type $end_sub_type
+    dict set guardparams sub_surround $sub_surround
+    dict set guardparams guard_sub_surround $end_sub_surround
+    dict set guardparams glc $elc
+    dict set guardparams grc $erc
+    dict set guardparams gtc $etc
+    dict set guardparams gbc $ebc
+    set cext [sky130::guard_ring $gx $gy $guardparams]
+
+    pushbox
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+    paint ${dev_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+
+    if {$dev_sub_type != ""} {
+	box grow n ${sub_surround}um
+	box grow s ${sub_surround}um
+	box grow e ${sub_surround}um
+	box grow w ${sub_surround}um
+	paint ${dev_sub_type}
+    }
+    popbox
+
+    if {${w} < ${l}} {
+	set orient vert
+    } else {
+	set orient horz
+    }
+
+    # Reduce width by surround amount
+    set w [- $w [* ${dev_surround} 2.0]]
+    set l [- $l [* ${dev_surround} 2.0]]
+
+    set cext [sky130::unionbox $cext [sky130::draw_contact ${w} ${l} \
+		${dev_surround} ${metal_surround} ${contact_size} \
+		${dev_type} ${dev_contact_type} li ${orient}]]
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Diode: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::diode_draw {parameters} {
+    tech unlock *
+
+    # Set defaults if they are not in parameters
+    set doverlap 0	;# overlap diodes at contacts
+    set guard 0		;# draw a guard ring
+    set prohibit_overlap false  ;# don't prohibit overlaps
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set bbox [sky130::diode_device $parameters]
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # If prohibit_overlap is true, then end overlapping is prohibited when
+    # nx or ny is > 1 to prevent DRC errors (typically from well spacing rule)
+    if {$prohibit_overlap == true} {
+        if {($nx > 1) || ($ny > 1)} {
+	    set doverlap 0
+	}
+    }
+
+    # Determine tile width and height (depends on overlap)
+
+    if {$doverlap == 0} {
+	set dx [+ $fw $end_spacing]
+        set dy [+ $fh $end_spacing]
+    } else {
+        # overlap contact
+        set dx [- $fw [+ [* 2.0 $sub_surround] [* 2.0 $end_surround] $contact_size]]
+        set dy [- $fh [+ [* 2.0 $sub_surround] [* 2.0 $end_surround] $contact_size]]
+    }
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $ny 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $diff_spacing $diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $diff_spacing $diff_surround]] $contact_size]
+
+	# Draw the guard ring first, because diode may occupy well/substrate plane
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    if {($nx > 1) || ($ny > 1)} {
+	pushbox
+	set hfw [/ $fw 2.0]
+	set hfh [/ $fh 2.0]
+	box move w ${hfw}um
+	box move s ${hfh}um
+	box size ${corex}um ${corey}um
+	paint $end_sub_type
+	popbox
+    }
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $ny} {incr yp} {
+	    sky130::diode_device $parameters
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+proc sky130::ndiode_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		ndiode \
+	    dev_contact_type	ndic \
+	    end_type		psd \
+	    end_contact_type	psc \
+	    end_sub_type	psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	0 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+} 
+
+#----------------------------------------------------------------
+# NOTE:  Use ppd instead of psd so that there is additional
+# diffusion around the contact, allowing more space for the
+# implant (likewise pdiode_lvt and pdiode_hvt).
+
+proc sky130::ndiode_lvt_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		ndiodelvt \
+	    dev_contact_type	ndilvtc \
+	    end_type		ppd \
+	    end_contact_type	psc \
+	    end_sub_type	psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+} 
+
+#----------------------------------------------------------------
+
+proc sky130::pdiode_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		pdiode \
+	    guard		1 \
+	    dev_contact_type	pdic \
+	    end_type		nsd \
+	    end_contact_type	nsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	0 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::pdiode_lvt_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		pdiodelvt \
+	    guard		1 \
+	    dev_contact_type	pdilvtc \
+	    end_type		nnd \
+	    end_contact_type	nsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::pdiode_hvt_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		pdiodehvt \
+	    guard		1 \
+	    dev_contact_type	pdihvtc \
+	    end_type		nnd \
+	    end_contact_type	nsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::ndiode_h_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		mvndiode \
+	    dev_contact_type	mvndic \
+	    end_type		mvpsd \
+	    end_contact_type	mvpsc \
+	    end_sub_type	psub \
+	    diff_spacing	0.37 \
+	    dev_spacing		0.39 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.36 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+
+proc sky130::ndiode_native_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		nndiode \
+	    dev_contact_type	nndic \
+	    end_type		mvpsd \
+	    end_contact_type	mvpsc \
+	    end_sub_type	psub \
+	    dev_spacing		0.37 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.30 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+} 
+
+
+#----------------------------------------------------------------
+
+proc sky130::pdiode_h_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		1 \
+	    dev_type 		mvpdiode \
+	    dev_contact_type	mvpdic \
+	    end_type		mvnsd \
+	    end_contact_type	mvnsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    sub_type		psub \
+	    diff_spacing	0.58 \
+	    dev_spacing		0.37 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.30 \
+	    end_sub_surround	0.33 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# Drawn capactitor routines
+# NOTE:  Work in progress.  These values need to be corrected.
+#----------------------------------------------------------------
+
+#ifdef MIM
+proc sky130::xcmimc1_defaults {} {
+    return {w 2.00 l 2.00 val 4.0 carea 1.00 cperi 0.17 \
+		nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 \
+		lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1}
+}
+proc sky130::xcmimc2_defaults {} {
+    return {w 2.00 l 2.00 val 4.0 carea 1.00 cperi 0.17 \
+		nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 \
+		lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1}
+}
+#endif (MIM)
+
+
+#----------------------------------------------------------------
+# Recalculate capacitor values from GUI entries.
+# Recomputes W/L and Value as long as 2 of them are present
+# (To be completed)
+#----------------------------------------------------------------
+
+proc sky130::cap_recalc {field parameters} {
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    switch  $field {
+	val { puts stdout "value changed" }
+	w   { puts stdout "width changed" }
+	l   { puts stdout "length changed" }
+    }
+    dict set parameters val $val
+    dict set parameters w $w
+    dict set parameters l $l
+}
+
+#----------------------------------------------------------------
+# Capacitor defaults:
+#----------------------------------------------------------------
+#  w      Width of drawn cap
+#  l      Length of drawn cap
+#  nx     Number of devices in X
+#  ny     Number of devices in Y
+#  val    Default cap value
+#  carea  Area
+#  cperi  Perimeter
+#  dummy  Add dummy cap
+#  square Make square capacitor
+#
+#  (not user-editable)
+#
+#  wmin   Minimum allowed width
+#  lmin   Minimum allowed length
+#  dc     Area to remove to calculated area 
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# capacitor: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::cap_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w {
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+                # Convert m to ny
+		dict set pdkparams ny $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#ifdef MIM
+proc sky130::xcmimc1_convert {parameters} {
+    return [cap_convert $parameters]
+}
+proc sky130::xcmimc2_convert {parameters} {
+    return [cap_convert $parameters]
+}
+#endif (MIM)
+
+#----------------------------------------------------------------
+# capacitor: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::cap_dialog {device parameters} {
+    # Editable fields:      w, l, nx, ny, val
+    # Checked fields:  	    square, dummy
+
+    magic::add_entry val "Value (fF)" $parameters
+    sky130::compute_ctot $parameters
+    magic::add_message ctot "Total capacitance (pF)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry ny "Y Repeat" $parameters
+
+    if {[dict exists $parameters square]} {
+	magic::add_checkbox square "Square capacitor" $parameters
+    }
+    if {[dict exists $parameters bconnect]} {
+	magic::add_checkbox bconnect "Connect bottom plates in array" $parameters
+    }
+    if {[dict exists $parameters tconnect]} {
+	magic::add_checkbox tconnect "Connect top plates in array" $parameters
+    }
+    if {[dict exists $parameters guard]} {
+	magic::add_checkbox guard "Add guard ring" $parameters
+    }
+
+    magic::add_dependency sky130::cap_recalc $device sky130 l w val
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+}
+
+#ifdef MIM
+proc sky130::xcmimc1_dialog {parameters} {
+    sky130::cap_dialog xcmimc1 $parameters
+}
+proc sky130::xcmimc2_dialog {parameters} {
+    sky130::cap_dialog xcmimc2 $parameters
+}
+#endif (MIM)
+
+#----------------------------------------------------------------
+# Capacitor total capacitance computation
+#----------------------------------------------------------------
+
+proc sky130::compute_ctot {parameters} {
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set val [magic::spice2float $val]
+    set val [magic::3digitpastdecimal $val]
+
+    # Compute total capacitance (and convert fF to pF)
+    catch {set magic::ctot_val [expr (0.001 * $val * $nx * $ny)]}
+}
+
+#----------------------------------------------------------------
+# Capacitor: Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::cap_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set cap_surround 0
+    set bot_surround 0
+    set top_surround 0
+    set bconnect 0	    ;# bottom plates are connected in array
+    set cap_spacing 0	    ;# cap spacing in array
+    set top_metal_space 0   ;# top metal spacing (if larger than cap spacing)
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    if {![dict exists $parameters top_metal_space]} {
+	set top_metal_space $metal_spacing
+    }
+
+    # Draw the device
+    pushbox
+    box size 0 0
+
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    box grow e ${hw}um
+    box grow w ${hw}um
+    box grow n ${hl}um
+    box grow s ${hl}um
+    paint ${cap_type}
+    pushbox
+    box grow n -${cap_surround}um
+    box grow s -${cap_surround}um
+    box grow e -${cap_surround}um
+    box grow w -${cap_surround}um
+    paint ${cap_contact_type}
+    pushbox
+    box grow n ${top_surround}um
+    box grow s ${top_surround}um
+    box grow e ${top_surround}um
+    box grow w ${top_surround}um
+    paint ${top_type}
+    set cext [sky130::getbox]
+    popbox
+    popbox
+    pushbox
+    box grow n ${bot_surround}um
+    box grow s ${bot_surround}um
+    box grow e ${bot_surround}um
+    box grow w ${bot_surround}um
+
+    paint ${bot_type}
+    # Create boundary using properties
+    property FIXED_BBOX [box values]
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+
+    # Extend bottom metal under contact to right
+    box grow e ${end_spacing}um
+    set chw [/ ${contact_size} 2.0]
+    box grow e ${chw}um
+    box grow e ${end_surround}um
+    paint ${bot_type}
+
+    popbox
+    popbox
+
+    # Draw contact to right.  Reduce contact extent if devices are not
+    # wired together and the top metal spacing rule limits the distance
+    set lcont $l
+    if {($bconnect == 0) && ($ny > 1)} {
+	if {$cap_spacing < $top_metal_space} {
+	    set cspace [- $top_metal_space $cap_spacing]
+	    set lcont [- $l $cspace]
+	}
+    }
+
+    pushbox
+    box move e ${hw}um
+    box move e ${bot_surround}um
+    box move e ${end_spacing}um
+    set cl [- [+ ${lcont} [* ${bot_surround} 2.0]] [* ${end_surround} 2.0]]
+    set cl [- ${cl} ${metal_surround}]  ;# see below
+    set cext [sky130::unionbox $cext [sky130::draw_contact 0 ${cl} \
+		${end_surround} ${metal_surround} ${contact_size} \
+		${bot_type} ${top_contact_type} ${top_type} full]]
+    popbox
+    popbox
+
+    return $cext
+
+    # cl shrinks top and bottom to accomodate larger bottom metal
+    # surround rule for contacts near a MiM cap.  This should be its
+    # own variable, but metal_surround is sufficient.
+}
+
+#----------------------------------------------------------------
+# Metal plate sandwich capacitor:  Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::sandwich_cap_device {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    pushbox
+    box size 0 0
+
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    set cw [- [* $hw [/ 2.0 3]] [* $cont_surround 2.0]]
+    set cl [- [* $hl [/ 2.0 3]] [* $cont_surround 2.0]]
+
+    # plate capacitor defines layers p0, p1, etc.
+    for {set i 0} {$i < 20} {incr i} {
+        if {[catch {set layer [subst \$p${i}_type]}]} {break}  ;# no more layers defined
+	pushbox
+	box grow e ${hw}um
+	box grow w ${hw}um
+	box grow n ${hl}um
+	box grow s ${hl}um
+        if {![catch {set shrink [subst \$p${i}_shrink]}]} {
+	    box grow e -${shrink}um
+	    box grow w -${shrink}um
+	    box grow n -${shrink}um
+	    box grow s -${shrink}um
+	    set cutout_spacing [+ [* ${shrink} 2.0] [/ $via_size 2.0] $cont_surround]
+	} else {
+	    set cutout_spacing 0
+	}
+
+	paint ${layer}
+
+	if {$i == 1} {
+	    # Note that cap_type geometry is coincident with p1_type.
+	    # Typically, this will define a layer that outputs as both
+	    # poly and a capacitor definition layer.
+	    if {[dict exists $parameters cap_type]} {
+		paint $cap_type
+	    }
+	}
+	popbox
+
+	# Even layers connect at corners, odd layers connect at sides.
+	# Even layers cut out the sides, odd layers cut out the corners.
+	# Layer zero has no side contacts or cutout.
+
+	if {[% $i 2] == 0} {
+	    set cornercmd  paint
+	    set cornersize $cutout_spacing
+	    set sidecmd    erase
+	    set nssidelong   [+ $cutout_spacing [/ $hw 3.0]]
+	    set ewsidelong   [+ $cutout_spacing [/ $hl 3.0]]
+	    set sideshort    $cutout_spacing
+	} else {
+	    set cornercmd  erase
+	    set cornersize $cutout_spacing
+	    set sidecmd    paint
+	    set nssidelong   [/ $hw 3.0]
+	    set ewsidelong   [/ $hl 3.0]
+	    set sideshort    $cutout_spacing
+	}
+
+	if {$i > 0} {
+	    pushbox
+	    box move e ${hw}um
+	    box grow n ${ewsidelong}um
+	    box grow s ${ewsidelong}um
+	    box grow w ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move n ${hl}um
+	    box grow e ${nssidelong}um
+	    box grow w ${nssidelong}um
+	    box grow s ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box grow n ${ewsidelong}um
+	    box grow s ${ewsidelong}um
+	    box grow e ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box grow e ${nssidelong}um
+	    box grow w ${nssidelong}um
+	    box grow n ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+
+	    pushbox
+	    box move n ${hl}um
+	    box move e ${hw}um
+	    box grow s ${cornersize}um
+	    box grow w ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move n ${hl}um
+	    box move w ${hw}um
+	    box grow s ${cornersize}um
+	    box grow e ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box move e ${hw}um
+	    box grow n ${cornersize}um
+	    box grow w ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box move w ${hw}um
+	    box grow n ${cornersize}um
+	    box grow e ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	}
+    }
+
+    # Draw contacts after all layers have been drawn, so that erasing
+    # layers does not affect the contacts.
+
+    for {set i 0} {$i < 20} {incr i} {
+        if {![catch {set contact [subst \$p${i}_contact_type]}]} {
+	    set layer [subst \$p${i}_type]
+	    set j [+ $i 1]
+	    set toplayer [subst \$p${j}_type]
+
+	    # Draw corner contacts
+	    pushbox
+	    box move e ${hw}um
+	    box move n ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box move n ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move e ${hw}um
+	    box move s ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box move s ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+
+	    # Draw side contacts (except on poly)
+	    if {$i > 0} {
+		pushbox
+		box move w ${hw}um
+		sky130::draw_contact 0 ${cl} \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move e ${hw}um
+		sky130::draw_contact 0 ${cl} \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move n ${hl}um
+		sky130::draw_contact ${cw} 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move s ${hl}um
+		sky130::draw_contact ${cw} 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+	    }
+	} else {
+	    break
+	}
+    }
+
+    popbox
+    # Bounding box is the same as the device length and width
+    set cext [list -$hw -$hl $hw $hl]
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Capacitor: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::cap_draw {parameters} {
+    tech unlock *
+    set savesnap [snap]
+    snap internal
+
+    # Set defaults if they are not in parameters
+    set coverlap 0	;# overlap capacitors at contacts
+    set guard 0		;# draw a guard ring
+    set sandwich 0	;# this is not a plate sandwich capacitor
+    set cap_spacing 0	;# abutted caps if spacing is zero
+    set cap_diff_spacing 0
+    set wide_cap_spacing 0  ;# additional spacing for wide metal rule
+    set wide_cap_width 0
+    set end_spacing 0
+    set end_surround 0
+    set bot_surround 0
+    set top_metal_width 0
+    set bconnect 0	;# connect bottom plates in array
+    set tconnect 0	;# connect top plates in array
+    set top_type ""
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    if {$sandwich == 1} {
+	set bbox [sky130::sandwich_cap_device $parameters]
+    } else {
+	set bbox [sky130::cap_device $parameters]
+    }
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    set dwide 0
+    if {($fw >= $wide_cap_width) && ($fh >= $wide_cap_width)} {
+	set dwide $wide_cap_spacing
+    }
+
+    # Determine tile width and height (depends on overlap)
+    if {$coverlap == 0} {
+        set dy [+ $fh $cap_spacing $dwide]
+    } else {
+        # overlap at end contact
+        set dy [- $fh [+ $end_surround $end_surround $contact_size]]
+    }
+    # Contact is placed on right so spacing is determined by end_spacing.
+    set dx [+ $fw $end_spacing $dwide]
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $ny 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $cap_diff_spacing $diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $end_spacing $diff_surround]] $contact_size]
+
+	# Draw the guard ring first.
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    set twidth [+ ${contact_size} ${end_surround} ${end_surround}]
+    if {${twidth} < ${top_metal_width}} {
+	set twidth ${top_metal_width}
+    }
+    set hmw [/ $twidth 2.0]
+    set hdy [/ $dy 2.0]
+    set cdx [+ [/ ${w} 2.0] ${bot_surround} ${end_spacing}]
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $ny} {incr yp} {
+	    if {$sandwich == 1} {
+		sky130::sandwich_cap_device $parameters
+	    } else {
+		sky130::cap_device $parameters
+	    }
+	    if {$ny > 1} {
+		pushbox
+		box grow e ${hmw}um
+		box grow w ${hmw}um
+		box grow n ${hdy}um
+		box grow s ${hdy}um
+		if {($top_type != "") && ($tconnect == 1)} {
+		    paint ${top_type}
+		}
+		if {($top_type != "") && ($bconnect == 1)} {
+		    box move e ${cdx}um
+		    paint ${top_type}
+		}
+		popbox
+	    }
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    snap $savesnap
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+#ifdef MIM
+proc sky130::xcmimc1_draw {parameters} {
+    set newdict [dict create \
+	    top_type 		m4 \
+	    top_contact_type	via3 \
+	    cap_type 		mimcap \
+	    cap_contact_type	mimcc \
+	    bot_type 		m3 \
+	    bot_surround	0.5 \
+	    cap_spacing		0.5 \
+	    cap_surround	0.2 \
+	    top_surround	0.005 \
+	    end_surround	0.1 \
+	    end_spacing		0.60 \
+	    contact_size	0.32 \
+	    metal_surround	0.08 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::cap_draw $drawdict]
+}
+
+proc sky130::xcmimc2_draw {parameters} {
+    set newdict [dict create \
+	    top_type 		m5 \
+	    top_contact_type	via4 \
+	    cap_type 		mimcap2 \
+	    cap_contact_type	mim2cc \
+	    bot_type 		m4 \
+	    bot_surround	0.5 \
+	    cap_spacing		0.5 \
+	    cap_surround	0.2 \
+	    top_surround	0.12 \
+	    end_surround	0.1 \
+	    end_spacing		2.10 \
+	    contact_size	1.18 \
+	    metal_surround	0.21 \
+	    top_metal_width	1.6 \
+	    top_metal_space	1.7 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::cap_draw $drawdict]
+}
+
+#endif (MIM)
+
+#----------------------------------------------------------------
+# capacitor: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::cap_check {parameters} {
+    # In case wmax and/or lmax are undefined
+    set lmax 0
+    set wmax 0
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l] 
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w] 
+
+    set val   [magic::spice2float $val]
+    set carea [magic::spice2float $carea]
+    set cperi [magic::spice2float $cperi]
+    set dc    [magic::spice2float $dc]
+
+    if {$square == 1} {
+        # Calculate L and W from value
+	set a $carea
+	set b [expr $cperi * 4]
+	set c [expr -4 * $dc - $val]
+	set l [expr ((-$b + sqrt($b * $b - (4 * $a * $c))) / (2 * $a))]
+	dict set parameters l [magic::float2spice $l]
+	set w $l
+	dict set parameters w [magic::float2spice $w]
+    } elseif {$l == 0} {
+        # Calculate L from W and value
+	set l [expr (($val + 4 * $dc - 2 * $w * $cperi) / ($w * $carea + 2 * $cperi))]
+	dict set parameters l [magic::float2spice $l]
+    } elseif {$w == 0} {
+        # Calculate W from L and value
+	set w [expr (($val + 4 * $dc - 2 * $l * $cperi) / ($l * $carea + 2 * $cperi))]
+	dict set parameters w [magic::float2spice $w]
+    }
+    if {$w < $wmin} {
+	puts stderr "Capacitor width must be >= $wmin"
+	dict set parameters w $wmin
+	set w $wmin
+    } 
+    if {$l < $lmin} {
+	puts stderr "Capacitor length must be >= $lmin"
+	dict set parameters l $lmin
+	set l $lmin
+    } 
+    if {($wmax > 0) && ($w > $wmax)} {
+	puts stderr "Capacitor width must be <= $wmax"
+	dict set parameters w $wmax
+	set w $wmax
+    } 
+    if {($lmax > 0) && ($l > $lmax)} {
+	puts stderr "Capacitor length must be <= $lmax"
+	dict set parameters l $lmax
+	set l $lmax
+    } 
+    # Calculate value from L and W
+    set cval [expr ($l * $w * $carea + 2 * ($l + $w) * $cperi - 4 * $dc)]
+    dict set parameters val [magic::float2spice $cval]
+    sky130::compute_ctot $parameters
+
+    return $parameters
+}
+
+#ifdef MIM
+proc sky130::xcmimc1_check {parameters} {
+    return [sky130::cap_check $parameters]
+}
+proc sky130::xcmimc2_check {parameters} {
+    return [sky130::cap_check $parameters]
+}
+#endif (MIM)
+
+#----------------------------------------------------------------
+# Drawn resistors
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# Resistor defaults:
+#----------------------------------------------------------------
+# User editable values:
+#
+#  val   Resistor value in ohms
+#  w	 Width
+#  l	 Length
+#  t	 Number of turns
+#  m	 Number devices in Y
+#  nx	 Number devices in X
+#  snake Use snake geometry (if not present, snake geometry not allowed)
+#  dummy Flag to mark addition of dummy resistor
+#
+# Non-user editable values:
+#
+#  wmin  Minimum allowed width
+#  lmin  Minimum allowed length
+#  rho	 Resistance in ohms per square
+#  dw    Delta width
+#  term  Resistance per terminal
+#  sterm Additional resistance per terminal for snake geometry
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# xpwres: Specify all user-editable default values and those
+# needed by xpwres_check
+# NOTE:  Work in progress.  These values need to be corrected.
+#----------------------------------------------------------------
+
+proc sky130::xpwres_defaults {} {
+    return {w 2.650 l 26.50 m 1 nx 1 wmin 2.650 lmin 26.50 \
+	 	rho 975 val 4875 dummy 0 dw 0.25 term 1.0 \
+		endcov 100 full_metal 1}
+}
+
+#----------------------------------------------------------------
+# rpp1: Specify all user-editable default values and those
+# needed by rp1_check
+#----------------------------------------------------------------
+
+proc sky130::mrp1_defaults {} {
+    return {w 0.330 l 1.650 m 1 nx 1 wmin 0.330 lmin 1.650 \
+		rho 48.2 val 241 dummy 0 dw 0.0 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+# "term" is rho * 0.06, the distance between xpc edge and CONT.
+proc sky130::xhrpoly_defaults {} {
+    return {w 0.350 l 0.50 m 1 nx 1 wmin 0.350 lmin 0.50 \
+		rho 319.8 val 456.857 dummy 0 dw 0.0 term 19.188 \
+		sterm 0.0 caplen 0 glc 1 grc 1 gtc 1 gbc 1 \
+		full_metal 1}
+}
+
+# "term" is rho * 0.06, the distance between xpc edge and CONT.
+proc sky130::uhrpoly_defaults {} {
+    return {w 0.350 l 0.50 m 1 nx 1 wmin 0.350 lmin 0.50 \
+		rho 2000 val 2875.143 dummy 0 dw 0.0 term 120 \
+		sterm 0.0 caplen 0 \
+		glc 1 grc 1 gtc 1 gbc 1 full_metal 1}
+}
+
+#----------------------------------------------------------------
+# mrdn: Specify all user-editable default values and those
+# needed by rdn_check
+#----------------------------------------------------------------
+
+proc sky130::mrdn_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 120 val 600.0 dummy 0 dw 0.05 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+proc sky130::mrdn_hv_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 120 val 600.0 dummy 0 dw 0.02 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+#----------------------------------------------------------------
+# mrdp: Specify all user-editable default values and those
+# needed by rdp_check
+#----------------------------------------------------------------
+
+proc sky130::mrdp_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 197 val 985.0 dummy 0 dw 0.02 term 0.0 \
+		sterm 0.0 caplen 0.60 snake 0 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+proc sky130::mrdp_hv_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 197 val 985.0 dummy 0 dw 0.02 term 0.0 \
+		sterm 0.0 caplen 0.60 snake 0 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+#----------------------------------------------------------------
+# mrl1: Specify all user-editable default values and those needed
+# by mrl1_check
+#----------------------------------------------------------------
+
+proc sky130::mrl1_defaults {} {
+    return {w 0.170 l 0.170 m 1 nx 1 wmin 0.17 lmin 0.17 \
+		rho 12.8 val 12.8 dummy 0 dw 0.0 term 0.0 snake 0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# mrm1: Specify all user-editable default values and those needed
+# by mrm1_check
+#----------------------------------------------------------------
+
+proc sky130::mrm1_defaults {} {
+    return {w 0.140 l 0.140 m 1 nx 1 wmin 0.14 lmin 0.14 \
+		rho 0.125 val 0.125 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# mrm2: Specify all user-editable default values and those needed
+# by mrm2_check
+#----------------------------------------------------------------
+
+proc sky130::mrm2_defaults {} {
+    return {w 0.140 l 0.140 m 1 nx 1 wmin 0.14 lmin 0.14 \
+		rho 0.125 val 0.125 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# mrm3: Specify all user-editable default values and those needed
+# by mrm3_check
+#----------------------------------------------------------------
+
+proc sky130::mrm3_defaults {} {
+    return {w 0.300 l 0.300 m 1 nx 1 wmin 0.30 lmin 0.30 \
+		rho 0.047 val 0.047 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# Additional entries for mrm4 and mrm5, depending on the
+# back-end metal stack.
+#----------------------------------------------------------------
+
+#ifdef METAL5
+proc sky130::mrm4_defaults {} {
+    return {w 0.300 l 0.300 m 1 nx 1 wmin 0.30 lmin 0.30 \
+		rho 0.047 val 0.047 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+proc sky130::mrm5_defaults {} {
+    return {w 1.600 l 1.600 m 1 nx 1 wmin 1.60 lmin 1.60 \
+		rho 0.029 val 0.029 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+#endif (METAL5)
+
+#----------------------------------------------------------------
+# resistor: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::res_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w {
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc sky130::xpwres_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrp1_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::xhrpoly_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::uhrpoly_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrdn_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrdp_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrdn_hv_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrdp_hv_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrl1_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrm1_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrm2_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::mrm3_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+#ifdef METAL5
+proc sky130::mrm4_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::mrm5_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+#endif (METAL5)
+
+#----------------------------------------------------------------
+# resistor: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::res_dialog {device parameters} {
+    # Editable fields:      w, l, t, nx, m, val
+    # Checked fields:  
+
+    magic::add_entry val "Value (ohms)" $parameters
+    if {[dict exists $parameters snake]} {
+	sky130::compute_ltot $parameters
+	magic::add_message ltot "Total length (um)" $parameters
+    }
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry m "Y Repeat" $parameters
+    if {[dict exists $parameters endcov]} {
+	magic::add_entry endcov "End contact coverage (%)" $parameters
+    }
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+
+    if {[dict exists $parameters snake]} {
+	magic::add_checkbox snake "Use snake geometry" $parameters
+    }
+    if {[dict exists $parameters roverlap]} {
+	if {[dict exists $parameters endcov]} {
+            magic::add_checkbox roverlap "Overlap at end contact" $parameters
+	} else {
+            magic::add_checkbox roverlap "Overlap at ends" $parameters
+	}
+    }
+    magic::add_checkbox guard "Add guard ring" $parameters
+
+    if {[dict exists $parameters full_metal]} {
+	magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    }
+    if {[dict exists $parameters glc]} {
+	magic::add_checkbox glc "Add left guard ring contact" $parameters
+    }
+    if {[dict exists $parameters grc]} {
+	magic::add_checkbox grc "Add right guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+	magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gbc]} {
+	magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+
+    if {[dict exists $parameters snake]} {
+       magic::add_dependency sky130::res_recalc $device sky130 l w val nx snake
+    } else {
+       magic::add_dependency sky130::res_recalc $device sky130 l w val nx
+    }
+}
+
+#----------------------------------------------------------------
+
+proc sky130::xpwres_dialog {parameters} {
+    sky130::res_dialog xpwres $parameters
+}
+
+proc sky130::mrp1_dialog {parameters} {
+    sky130::res_dialog mrp1 $parameters
+}
+
+proc sky130::xhrpoly_dialog {parameters} {
+    sky130::res_dialog xhrpoly $parameters
+}
+
+proc sky130::uhrpoly_dialog {parameters} {
+    sky130::res_dialog uhrpoly $parameters
+}
+
+proc sky130::mrdn_dialog {parameters} {
+    sky130::res_dialog mrdn $parameters
+}
+
+proc sky130::mrdp_dialog {parameters} {
+    sky130::res_dialog mrdp $parameters
+}
+
+proc sky130::mrdn_hv_dialog {parameters} {
+    sky130::res_dialog mrdn_hv $parameters
+}
+
+proc sky130::mrdp_hv_dialog {parameters} {
+    sky130::res_dialog mrdp_hv $parameters
+}
+
+proc sky130::mrl1_dialog {parameters} {
+    sky130::res_dialog mrl1 $parameters
+}
+
+proc sky130::mrm1_dialog {parameters} {
+    sky130::res_dialog mrm1 $parameters
+}
+
+proc sky130::mrm2_dialog {parameters} {
+    sky130::res_dialog mrm2 $parameters
+}
+
+proc sky130::mrm3_dialog {parameters} {
+    sky130::res_dialog mrm3 $parameters
+}
+
+#ifdef METAL5
+proc sky130::mrm4_dialog {parameters} {
+    sky130::res_dialog mrm4 $parameters
+}
+proc sky130::mrm5_dialog {parameters} {
+    sky130::res_dialog mrm5 $parameters
+}
+#endif (METAL5)
+
+#----------------------------------------------------------------
+# Resistor: Draw a single device in straight geometry
+#----------------------------------------------------------------
+
+proc sky130::res_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set endcov 0	 	;# percent coverage of end contacts
+    set roverlap 0		;# overlap resistors at end contacts
+    set well_res_overlap 0 	;# not a well resistor
+    set end_contact_type ""	;# no contacts for metal resistors
+    set end_overlap_cont 0	;# additional end overlap on sides
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    if {![dict exists $parameters end_contact_size]} {
+	set end_contact_size $contact_size
+    }
+
+    # Draw the resistor and endcaps
+    pushbox
+    box size 0 0
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+
+    pushbox
+    box grow n ${res_to_endcont}um
+    box grow s ${res_to_endcont}um
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${end_contact_size} 2.0] ${end_surround}]
+	box grow n ${well_extend}um
+	box grow s ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    set cext [sky130::getbox]
+    popbox
+
+    if {$well_res_overlap > 0} {
+	erase ${well_res_type}
+    } else {
+	erase ${end_type}
+    }
+    paint ${res_type}
+    popbox
+
+    # Reduce contact sizes by (end type) surround so that
+    # the contact area edges match the device type width.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set epl [- ${w} [* ${end_surround} 2]]     	    ;# end contact width
+
+    # Reduce end material size for well resistor types
+    if {$well_res_overlap > 0} {
+	set epl [- ${epl} [* ${well_res_overlap} 2]]
+    }
+
+    # Reduce by coverage percentage unless overlapping at contacts
+    if {(${roverlap} == 0) && (${endcov} > 0)} {
+	set cpl [* ${epl} [/ ${endcov} 100.0]]
+    } else {
+	set cpl $epl
+    }
+
+    # Ensure additional overlap of diffusion contact if required
+    set dov [* ${end_overlap_cont} 2]
+    if {[- ${epl} ${cpl}] < $dov} {
+	set cpl [- ${epl} $dov]    ;# additional end contact width
+    }
+
+    set hepl [+ [/ ${epl} 2.0] ${end_surround}]
+    set hesz [/ ${end_contact_size} 2.0]
+
+    # LV substrate diffusion types have a different surround requirement
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $end_type] < 0} {
+	set hesz [+ ${hesz} ${end_surround}]
+    }
+
+    # Top end material & contact
+    pushbox
+    box move n ${hl}um
+    box move n ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]]
+    }
+    popbox
+
+    # Bottom end material & contact
+    pushbox
+    box move s ${hl}um
+    box move s ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]]
+    }
+    popbox
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Resistor: Draw a single device in snake geometry
+#----------------------------------------------------------------
+
+proc sky130::res_snake_device {nf parameters} {
+    # nf is the number of fingers of the snake geometry
+
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set endcov 100	 	;# percent coverage of end contacts
+    set well_res_overlap 0 	;# not a well resistor
+    set end_contact_type ""	;# no contacts for metal resistors
+    set mask_clearance 0	;# additional length to clear mask
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    if {![dict exists $parameters end_contact_size]} {
+	set end_contact_size $contact_size
+    }
+
+    # Compute half width and length
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    # Reduce contact sizes by (end type) surround so that
+    # the contact area edges match the device type width.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set epl [- ${w} [* ${end_surround} 2]]     	    ;# end contact width
+
+    # Reduce contact size for well resistor types
+    if {$well_res_overlap > 0} {
+	set epl [- ${epl} [* ${well_res_overlap} 2]]
+    }
+
+    # Reduce contact part of end by coverage percentage
+    if {${endcov} > 0} {
+	set cpl [* ${epl} [/ ${endcov} 100.0]]
+    } else {
+	set cpl $epl
+    }
+
+    set hepl [+ [/ ${epl} 2.0] ${end_surround}]
+    set hesz [+ [/ ${end_contact_size} 2.0] ${end_surround}]
+
+    pushbox
+    box size 0 0	;# Position is taken from caller
+
+    # Front end contact (always bottom)
+    pushbox
+    box move s ${hl}um
+    pushbox
+    box move s ${mask_clearance}um
+    box move s ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::getbox]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]
+    }
+    popbox
+
+    # Draw portion between resistor end and contact.
+    box grow e ${hw}um
+    box grow w ${hw}um
+    pushbox
+    box grow s ${mask_clearance}um
+    paint ${res_type}
+    popbox
+    box move s ${mask_clearance}um
+    box grow s ${res_to_endcont}um
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${end_contact_size} 2.0] ${end_surround}]
+	box grow s ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    # Draw the resistor and endcaps
+    pushbox
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+
+    # Capture these extents in the bounding box in case both contacts
+    # are on one side.
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+
+    set deltax [+ ${res_spacing} ${w}]
+    set deltay [- ${l} ${w}]
+    for {set i 0} {$i < [- $nf 1]} {incr i} {
+	paint ${res_type}
+ 	pushbox
+	if {[% $i 2] == 0} {
+	    box move n ${deltay}um
+	}
+	box height ${w}um
+	box width ${deltax}um
+	paint ${res_type}
+ 	popbox
+	box move e ${deltax}um
+    }
+    paint ${res_type}
+    # Capture these extents in the bounding box
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    # Move box to last finger
+    set lastf [* [- $nf 1] $deltax]
+    box move e ${lastf}um
+
+    # Back-end contact (top or bottom, depending if odd or even turns)
+    pushbox
+
+    if {[% $nf 2] == 1} {
+	set dir n
+    } else {
+	set dir s
+    }
+    box move $dir ${hl}um
+    pushbox
+    box move $dir ${mask_clearance}um
+    box move $dir ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]]
+    }
+    popbox
+    # Draw portion between resistor end and contact.
+    box grow e ${hw}um
+    box grow w ${hw}um
+    pushbox
+    box grow $dir ${mask_clearance}um
+    paint ${res_type}
+    popbox
+    box move $dir ${mask_clearance}um
+    box grow $dir ${res_to_endcont}um
+
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${end_contact_size} 2.0] ${end_surround}]
+	box grow $dir ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    popbox
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Resistor: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::res_draw {parameters} {
+    tech unlock *
+    set savesnap [snap]
+    snap internal
+
+    # Set defaults if they are not in parameters
+    set snake 0		;# some resistors don't allow snake geometry
+    set roverlap 0	;# overlap resistors at contacts
+    set guard 1		;# draw a guard ring
+    set plus_diff_type   nsd	;# guard ring diffusion type
+    set overlap_compress 0	;# special Y distance compression
+    set well_res_overlap 0	;# additional well extension behind contact
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # For devices where inter-device space is smaller than device-to-guard ring
+    if {![dict exists $parameters end_to_end_space]} {
+	set end_to_end_space $end_spacing
+    }
+
+    if {![dict exists $parameters end_contact_size]} {
+	set end_contact_size $contact_size
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set nf $nx
+    if {($snake == 1) && ($nx == 1)} {set snake 0}
+    if {$snake == 1} {
+	set bbox [sky130::res_snake_device $nf $parameters]
+	set nx 1
+    } else {
+	set bbox [sky130::res_device $parameters]
+    }
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # Determine tile width and height (depends on overlap)
+    # Snake resistors cannot overlap.
+    # However, snake resistors with an odd number of fingers can
+    # compress the space if overlap_compress is defined
+
+    if {($roverlap == 1) && ($snake == 1) && ([% $nf 2] == 1) && ($m > 1)} {
+        set dy [- $fh $overlap_compress]
+    } elseif {($roverlap == 0) || ($snake == 1)} {
+        set dy [+ $fh $end_to_end_space]
+    } else {
+        # overlap poly
+        set dy [- $fh [+ [* [+ $end_surround $well_res_overlap] 2.0] $end_contact_size]]
+    }
+    set dx [+ $fw $res_spacing]
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $m 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $plus_diff_type] >= 0} {
+	set guard_diff_surround 0
+    } else {
+	set guard_diff_surround ${diff_surround}
+    }
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $res_diff_spacing $guard_diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $end_spacing $guard_diff_surround]] $contact_size]
+
+	# Draw the guard ring first, because well resistors are on the substrate plane
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    # puts "Device position at = [sky130::getbox]"
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $m} {incr yp} {
+	    if {$snake == 1} {
+		sky130::res_snake_device $nf $parameters
+	    } else {
+		sky130::res_device $parameters
+	    }
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    snap $savesnap
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrp1_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		npres \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		nwell \
+	    end_surround	$poly_surround \
+	    end_spacing		0.48 \
+	    end_to_end_space	0.52 \
+	    res_to_endcont	$res_to_cont \
+	    res_spacing		$poly_spacing \
+	    res_diff_spacing	0.48 \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::xhrpoly_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		ppres \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    end_surround	$poly_surround \
+	    end_spacing		0.48 \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	0.48 \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::uhrpoly_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		xpres \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    end_surround	$poly_surround \
+	    end_spacing		0.48 \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	0.48 \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrdn_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rdn \
+	    end_type 		ndiff \
+	    end_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    end_surround	$diff_surround \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		0.30 \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrdn_hv_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		mvrdn \
+	    end_type 		mvndiff \
+	    end_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    sub_type		psub \
+	    end_surround	$diff_surround \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		0.30 \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrdp_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rdp \
+	    end_type 		pdiff \
+	    end_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		nwell \
+	    end_surround	$diff_surround \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		$diff_spacing \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrdp_hv_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		mvrdp \
+	    end_type 		mvpdiff \
+	    end_contact_type	mvpdc \
+	    plus_diff_type	mvnsd \
+	    plus_contact_type	mvnsc \
+	    sub_type		nwell \
+	    end_surround	$diff_surround \
+	    guard_sub_surround	0.33 \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		0.30 \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::xpwres_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    well_res_type	pwell \
+	    res_type		rpw \
+	    end_type 		psd \
+	    end_contact_type	psc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		dnwell \
+	    sub_surround	0.23 \
+	    guard_sub_type	nwell \
+	    guard_sub_surround	0.63 \
+	    end_surround	$diff_surround \
+	    end_spacing		0.63 \
+	    end_to_end_space	1.15 \
+	    end_overlap_cont	0.06 \
+	    end_contact_size	0.53 \
+	    overlap_compress	-0.17 \
+	    res_to_endcont	0.265 \
+	    res_spacing		1.4 \
+	    res_diff_spacing	0.63 \
+	    well_res_overlap	0.2 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrl1_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rli \
+	    end_type 		li \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    end_to_end_space	0.23 \
+	    res_spacing		$metal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrm1_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm1 \
+	    end_type 		m1 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrm2_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm2 \
+	    end_type 		m2 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mrm3_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm3 \
+	    end_type 		m3 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+#ifdef METAL5
+proc sky130::mrm4_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm4 \
+	    end_type 		m4 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::mrm5_draw {parameters} {
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm5 \
+	    end_type 		m5 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	1.6 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+#endif (METAL5)
+
+#----------------------------------------------------------------
+# Resistor total length computation
+#----------------------------------------------------------------
+
+proc sky130::compute_ltot {parameters} {
+    # In case snake not defined
+    set snake 0
+    set caplen 0
+
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l]
+
+    # Compute total length.  Use catch to prevent error in batch/scripted mode.
+    if {$snake == 1} {
+	catch {set magic::ltot_val [expr ($caplen * ($nx - 1)) + ($l * $nx) + ($nx - 1)]}
+    } else {
+	catch {set magic::ltot_val $l}
+    }
+}
+
+#----------------------------------------------------------------
+# resistor: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::res_check {device parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    set snake 0
+    set sterm 0.0
+    set caplen 0
+
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w]
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l]
+
+    set val  [magic::spice2float $val]
+    set rho  [magic::spice2float $rho]
+
+    # nf, m must be integer
+    if {![string is int $nx]} {
+	puts stderr "X repeat must be an integer!"
+        dict set parameters nx 1
+    }
+    if {![string is int $m]} {
+	puts stderr "Y repeat must be an integer!"
+        dict set parameters m 1
+    }
+
+    # Width always needs to be specified
+    if {$w < $wmin} {
+	puts stderr "Resistor width must be >= $wmin um"
+	dict set parameters w $wmin
+    } 
+    # Val and W specified - no L
+    if {$l == 0}  {
+   	set l [expr ($w - $dw) * $val / $rho]
+        set l [magic::3digitpastdecimal $l]
+        set stringval [magic::float2spice $val]
+	dict set parameters l [magic::float2spice [expr $l * 1e-6]]
+	# L and W specified - ignore Val if specified
+    } else {
+	if {$snake == 0} {
+	    set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+	} else {
+	    set val [expr $rho * ($nx - 1) + ((2 * ($term + $sterm)) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+	}
+	set val [magic::float2spice $val]
+        dict set parameters val $val
+    }
+    if {$l < $lmin} {
+	puts stderr "Resistor length must be >= $lmin um"
+	dict set parameters l $lmin
+    } 
+    if {$nx < 1} {
+	puts stderr "X repeat must be >= 1"
+	dict set parameters nx 1
+    } 
+    if {$m < 1} {
+	puts stderr "Y repeat must be >= 1"
+	dict set parameters m 1
+    } 
+
+    # Snake resistors cannot have width greater than length
+    if {$snake == 1} {
+	if {$w > $l} {
+	    puts stderr "Snake resistor width must be < length"
+	    dict set parameters w $l
+	}
+    }
+
+    # Diffusion resistors must satisfy diffusion-to-tap spacing of 20um.
+    # Therefore the maximum of guard ring width or height cannot exceed 40um.
+    # If in violation, reduce counts first, as these are easiest to recover
+    # by duplicating the device and overlapping the wells.
+    if {$device == "rdn" || $device == "rdp"} {
+       set origm $m
+       set orignx $nx
+       while true {
+	  set xext [expr ($w + 0.8) * $nx + 1.0]
+	  set yext [expr ($l + 1.7) * $m + 1.7]
+          if {[expr min($xext, $yext)] > 40.0} {
+              if {$yext > 40.0 && $m > 1} {
+		 incr m -1
+	      } elseif {$xext > 40.0 && $nx > 1} {
+		 incr nx -1
+	      } elseif {$yext > 40.0} {
+		 set l 36.6
+		 puts -nonewline stderr "Diffusion resistor length must be < 36.6 um"
+		 puts stderr " to avoid tap spacing violation."
+		 dict set parameters l $l
+	      } elseif {$xext > 40.0} {
+		 set w 38.2
+		 puts -nonewline stderr "Diffusion resistor width must be < 38.2 um"
+		 puts stderr " to avoid tap spacing violation."
+		 dict set parameters w $w
+	      }
+          } else {
+	      break
+	  }
+       }
+       if {$m != $origm} {
+	  puts stderr "Y repeat reduced to prevent tap distance violation"
+	  dict set parameters m $m
+       }
+       if {$nx != $orignx} {
+	  puts stderr "X repeat reduced to prevent tap distance violation"
+	  dict set parameters nx $nx
+       }
+    }
+    sky130::compute_ltot $parameters
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::xpwres_check {parameters} {
+    return [sky130::res_check xpwres $parameters]
+}
+
+proc sky130::mrp1_check {parameters} {
+    return [sky130::res_check mrp1 $parameters]
+}
+
+proc sky130::xhrpoly_check {parameters} {
+    return [sky130::res_check xhrpoly $parameters]
+}
+
+proc sky130::uhrpoly_check {parameters} {
+    return [sky130::res_check uhrpoly $parameters]
+}
+
+proc sky130::mrdn_check {parameters} {
+    return [sky130::res_check mrdn $parameters]
+}
+
+proc sky130::mrdp_check {parameters} {
+    return [sky130::res_check mrdp $parameters]
+}
+
+proc sky130::mrdn_hv_check {parameters} {
+    return [sky130::res_check mrdn_hv $parameters]
+}
+
+proc sky130::mrdp_hv_check {parameters} {
+    return [sky130::res_check mrdp_hv $parameters]
+}
+
+proc sky130::mrl1_check {parameters} {
+    return [sky130::res_check mrl1 $parameters]
+}
+
+proc sky130::mrm1_check {parameters} {
+    return [sky130::res_check mrm1 $parameters]
+}
+
+proc sky130::mrm2_check {parameters} {
+    return [sky130::res_check mrm2 $parameters]
+}
+
+proc sky130::mrm3_check {parameters} {
+    return [sky130::res_check mrm3 $parameters]
+}
+
+#ifdef METAL5
+proc sky130::mrm4_check {parameters} {
+    return [sky130::res_check mrm4 $parameters]
+}
+proc sky130::mrm5_check {parameters} {
+    return [sky130::res_check mrm5 $parameters]
+}
+#endif (METAL5)
+
+#----------------------------------------------------------------
+# MOS defaults:
+#----------------------------------------------------------------
+#    w       = Gate width
+#    l       = Gate length
+#    m	     = Multiplier
+#    nf	     = Number of fingers
+#    diffcov = Diffusion contact coverage
+#    polycov = Poly contact coverage
+#    topc    = Top gate contact
+#    botc    = Bottom gate contact
+#    guard   = Guard ring
+#
+# (not user-editable)
+#
+#    lmin    = Gate minimum length
+#    wmin    = Gate minimum width
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# pmos: Specify all user-editable default values and those
+# needed by mos_check
+#----------------------------------------------------------------
+
+proc sky130::pshort_defaults {} {
+    return {w 0.42 l 0.15 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {pshort plowvt phighvt phv} full_metal 1}
+}
+
+proc sky130::plowvt_defaults {} {
+    return {w 0.42 l 0.35 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 \
+		compatible {pshort plowvt phighvt phv} full_metal 1}
+}
+
+proc sky130::phighvt_defaults {} {
+    return {w 0.42 l 0.15 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {pshort plowvt phighvt phv} full_metal 1}
+}
+
+proc sky130::phv_defaults {} {
+    return {w 0.42 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 \
+		compatible {pshort plowvt phighvt phv} full_metal 1}
+}
+
+#----------------------------------------------------------------
+# nmos: Specify all user-editable default values and those
+# needed by mos_check
+#----------------------------------------------------------------
+
+proc sky130::nshort_defaults {} {
+    return {w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {nshort nlowvt sonos_e nhv nhvnative} full_metal 1}
+}
+
+proc sky130::nlowvt_defaults {} {
+    return {w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {nshort nlowvt sonos_e nhv nhvnative} full_metal 1}
+}
+
+proc sky130::sonos_e_defaults {} {
+    return {w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {nshort nlowvt sonos_e nhv nhvnative} full_metal 1}
+}
+
+proc sky130::nhv_defaults {} {
+    return {w 0.42 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 \
+		compatible {nshort nlowvt sonos_e nhv nhvnative} full_metal 1}
+}
+
+proc sky130::nhvnative_defaults {} {
+    return {w 0.42 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 \
+		compatible {nshort nlowvt sonos_e nhv nhvnative} full_metal 1}
+}
+
+#----------------------------------------------------------------
+# mos varactor: Specify all user-editable default values and those
+# needed by mosvc_check
+#----------------------------------------------------------------
+
+proc sky130::xcnwvc_defaults {} {
+    return {w 1.0 l 0.18 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.18 wmin 1.0 \
+		compatible {xcnwvc xcnwvc2 xchvnwc} full_metal 1}
+}
+
+proc sky130::xcnwvc2_defaults {} {
+    return {w 1.0 l 0.18 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.18 wmin 1.0 \
+		compatible {xcnwvc xcnwvc2 xchvnwc} full_metal 1}
+}
+
+proc sky130::xchvnwc_defaults {} {
+    return {w 1.0 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 1.0 \
+		compatible {xcnwvc xcnwvc2 xchvnwc} full_metal 1}
+}
+
+#----------------------------------------------------------------
+# mos: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::mos_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w {
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+		# M value in an expression like '1*1' convert to
+		# M and NF
+		if {[regexp {\'([0-9]+)\*([0-9]+)\'} $value valid m nf]} {
+		    dict set pdkparams [string tolower $key] $m
+		    dict set pdkparams nf $nf
+		} else {
+		    dict set pdkparams [string tolower $key] $value
+		}
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc sky130::nshort_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::nlowvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sonos_e_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::nhv_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::nhvnative_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::pshort_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::plowvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::phighvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::phv_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::xcnwvc_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::xcnwvc2_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::xchvnwc_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# mos: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::mos_dialog {device parameters} {
+    # Editable fields:      w, l, nf, m, diffcov, polycov
+    # Checked fields:  topc, botc
+    # For specific devices, gate type is a selection list
+
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry nf "Fingers" $parameters
+    magic::add_entry m "M" $parameters
+
+    if {[dict exists $parameters compatible]} {
+       set sellist [dict get $parameters compatible]
+       magic::add_selectlist gencell "Device type" $sellist $parameters $device
+    }
+
+    magic::add_entry diffcov "Diffusion contact coverage (%)" $parameters
+    magic::add_entry polycov "Poly contact coverage (%)" $parameters
+    magic::add_entry rlcov "Guard ring contact coverage (%)" $parameters
+    if {[dict exists $parameters gbc]} {
+	magic::add_entry tbcov "Guard ring top/bottom contact coverage (%)" $parameters
+    }
+
+    magic::add_checkbox poverlap "Overlap at poly contact" $parameters
+    magic::add_checkbox doverlap "Overlap at diffusion contact" $parameters
+    magic::add_checkbox topc "Add top gate contact" $parameters
+    magic::add_checkbox botc "Add bottom gate contact" $parameters
+
+    magic::add_checkbox guard "Add guard ring" $parameters
+    magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    magic::add_checkbox glc "Add left guard ring contact" $parameters
+    magic::add_checkbox grc "Add right guard ring contact" $parameters
+    if {[dict exists $parameters gbc]} {
+	magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+	magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+}
+
+#----------------------------------------------------------------
+
+proc sky130::nshort_dialog {parameters} {
+    sky130::mos_dialog nshort $parameters
+}
+
+proc sky130::nlowvt_dialog {parameters} {
+    sky130::mos_dialog nlowvt $parameters
+}
+
+proc sky130::sonos_e_dialog {parameters} {
+    sky130::mos_dialog sonos_e $parameters
+}
+
+proc sky130::nhv_dialog {parameters} {
+    sky130::mos_dialog nhv $parameters
+}
+
+proc sky130::nhvnative_dialog {parameters} {
+    sky130::mos_dialog nhvnative $parameters
+}
+
+proc sky130::pshort_dialog {parameters} {
+    sky130::mos_dialog pshort $parameters
+}
+
+proc sky130::plowvt_dialog {parameters} {
+    sky130::mos_dialog plowvt $parameters
+}
+
+proc sky130::phighvt_dialog {parameters} {
+    sky130::mos_dialog phighvt $parameters
+}
+
+proc sky130::phv_dialog {parameters} {
+    sky130::mos_dialog phv $parameters
+}
+
+proc sky130::xcnwvc_dialog {parameters} {
+    sky130::mos_dialog xcnwvc $parameters
+}
+
+proc sky130::xcnwvc2_dialog {parameters} {
+    sky130::mos_dialog xcnwvc2 $parameters
+}
+
+proc sky130::xchvnwc_dialog {parameters} {
+    sky130::mos_dialog xchvnwc $parameters
+}
+
+#----------------------------------------------------------------
+# getbox:  Get the current cursor box, in microns
+#----------------------------------------------------------------
+
+proc sky130::getbox {} {
+    set curbox [box values]
+    set newbox []
+    set oscale [cif scale out]
+    for {set i 0} {$i < 4} {incr i} {
+        set v [* [lindex $curbox $i] $oscale]
+        lappend newbox $v
+    }
+    return $newbox
+}
+
+#----------------------------------------------------------------
+# unionbox:  Get the union bounding box of box1 and box2
+#----------------------------------------------------------------
+
+proc sky130::unionbox {box1 box2} {
+    set newbox []
+    for {set i 0} {$i < 2} {incr i} {
+        set v [lindex $box1 $i]
+        set o [lindex $box2 $i]
+        if {$v < $o} {
+            lappend newbox $v
+        } else {
+            lappend newbox $o
+        }
+    }
+    for {set i 2} {$i < 4} {incr i} {
+        set v [lindex $box1 $i]
+        set o [lindex $box2 $i]
+        if {$v > $o} {
+            lappend newbox $v
+        } else {
+            lappend newbox $o
+        }
+    }
+    return $newbox
+}
+
+#----------------------------------------------------------------
+# Draw a contact
+#----------------------------------------------------------------
+
+proc sky130::draw_contact {w h s o x atype ctype mtype {orient vert}} {
+
+    # Draw a minimum-size diff contact centered at current position
+    # w is width, h is height.  Minimum size ensured.
+    # x is contact size
+    # s is contact diffusion (or poly) surround
+    # o is contact metal surround
+    # atype is active (e.g., ndiff) or bottom metal if a via
+    # ctype is contact (e.g., ndc)
+    # mtype is metal (e.g., m1) or top metal if a via
+    # orient is the orientation of the contact
+
+    # Set orientations for the bottom material based on material type.
+    # Substrate diffusions (tap) need not overlap the contact in all
+    # directions, but other (diff) types do.  The metal (local
+    # interconnect) layer always overlaps in two directions only.
+
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $atype] >= 0} {
+	set aorient $orient
+    } else {
+	set aorient "full"
+    }
+
+    pushbox
+    box size 0 0
+    if {$w < $x} {set w $x}
+    if {$h < $x} {set h $x}
+    set hw [/ $w 2.0]
+    set hh [/ $h 2.0]
+    box grow n ${hh}um
+    box grow s ${hh}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+    paint ${ctype}
+    pushbox
+    # Bottom layer surrounded on sides as declared by aorient
+    if {($aorient == "vert") || ($aorient == "full")} {
+	box grow n ${s}um
+	box grow s ${s}um
+    }
+    if {($aorient == "horz") || ($aorient == "full")} {
+	box grow e ${s}um
+	box grow w ${s}um
+    }
+    paint ${atype}
+    set extents [sky130::getbox]
+    popbox
+    # Top layer surrounded on sides as declared by orient
+    if {($orient == "vert") || ($orient == "full")} {
+        box grow n ${o}um
+        box grow s ${o}um
+    }
+    if {($orient == "horz") || ($orient == "full")} {
+        box grow e ${o}um
+        box grow w ${o}um
+    }
+    paint ${mtype}
+    popbox
+    return $extents
+}
+
+#----------------------------------------------------------------
+# Draw a guard ring
+#----------------------------------------------------------------
+
+proc sky130::guard_ring {gw gh parameters} {
+
+    # Set local default values if they are not in parameters
+    set rlcov 100	;# Right-left contact coverage percentage
+    set tbcov 100	;# Top-bottom contact coverage percentage
+    set grc 1		;# Draw right side contact
+    set glc 1		;# Draw left side contact
+    set gtc 1		;# Draw right side contact
+    set gbc 1		;# Draw left side contact
+    set full_metal 1	;# Draw full (continuous) metal ring
+    set guard_sub_type	 pwell	;# substrate type under guard ring
+    set guard_sub_surround  0	;# substrate type surrounds guard ring
+    set plus_diff_type   nsd	;# guard ring diffusion type
+    set plus_contact_type nsc	;# guard ring diffusion contact type
+    set sub_type	 pwell	;# substrate type
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Set guard_sub_type to sub_type if it is not defined
+    if {![dict exists $parameters guard_sub_type]} {
+	set guard_sub_type $sub_type
+    }
+
+    set hx [/ $contact_size 2.0]
+    set hw [/ $gw 2.0]
+    set hh [/ $gh 2.0]
+
+    # Watch for (LV) substrate diffusion types, which have a different
+    # contact surround amount depending on the direction
+
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $plus_diff_type] >= 0} {
+	set diff_surround 0
+    }
+
+    # Compute diffusion width
+    set difft [+ $contact_size $diff_surround $diff_surround]
+    set hdifft [/ $difft 2.0]
+    # Compute guard ring diffusion width and height
+    set hdiffw [/ [+ $gw $difft] 2.0]
+    set hdiffh [/ [+ $gh $difft] 2.0]
+
+    pushbox
+    box size 0 0
+
+    pushbox
+    box move n ${hh}um
+    box grow n ${hdifft}um
+    box grow s ${hdifft}um
+    box grow e ${hdiffw}um
+    box grow w ${hdiffw}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+    pushbox
+    box move s ${hh}um
+    box grow n ${hdifft}um
+    box grow s ${hdifft}um
+    box grow e ${hdiffw}um
+    box grow w ${hdiffw}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+    pushbox
+    box move e ${hw}um
+    box grow e ${hdifft}um
+    box grow w ${hdifft}um
+    box grow n ${hdiffh}um
+    box grow s ${hdiffh}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+    pushbox
+    box move w ${hw}um
+    box grow e ${hdifft}um
+    box grow w ${hdifft}um
+    box grow n ${hdiffh}um
+    box grow s ${hdiffh}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+
+    if {$full_metal} {
+	set hmetw [/ [+ $gw $contact_size] 2.0]
+	set hmeth [/ [+ $gh $contact_size] 2.0]
+	pushbox
+	box move n ${hh}um
+	box grow n ${hx}um
+	box grow s ${hx}um
+	box grow e ${hmetw}um
+	box grow w ${hmetw}um
+	paint li
+	popbox
+	pushbox
+	box move s ${hh}um
+	box grow n ${hx}um
+	box grow s ${hx}um
+	box grow e ${hmetw}um
+	box grow w ${hmetw}um
+	paint li
+	popbox
+	pushbox
+	box move e ${hw}um
+	box grow e ${hx}um
+	box grow w ${hx}um
+	box grow n ${hmeth}um
+	box grow s ${hmeth}um
+	paint li
+	popbox
+	pushbox
+	box move w ${hw}um
+	box grow e ${hx}um
+	box grow w ${hx}um
+	box grow n ${hmeth}um
+	box grow s ${hmeth}um
+	paint li
+	popbox
+    }
+
+    # Set guard ring height so that contact metal reaches to end, scale by $per
+    # set ch [* [+ $gh $contact_size [* $metal_surround -2.0]] [/ $rlcov 100.0]]
+    set ch [* [- $gh $contact_size [* [+ $metal_surround $metal_spacing] \
+		2.0]] [/ $rlcov 100.0]]
+    if {$ch < $contact_size} {set ch $contact_size}
+
+    # Set guard ring width so that contact metal reaches to side contacts
+    set cw [* [- $gw $contact_size [* [+ $metal_surround $metal_spacing] \
+		2.0]] [/ $tbcov 100.0]]
+    if {$cw < $contact_size} {set cw $contact_size}
+
+    if {$tbcov > 0.0} {
+        if {$gtc == 1} {
+            pushbox
+            box move n ${hh}um
+            sky130::draw_contact $cw 0 $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li horz
+            popbox
+	}
+	if {$gbc == 1} {
+	    pushbox
+	    box move s ${hh}um
+	    sky130::draw_contact $cw 0 $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li horz
+	    popbox
+	}
+    }
+    if {$rlcov > 0.0} {
+        if {$grc == 1} {
+            pushbox
+            box move e ${hw}um
+            sky130::draw_contact 0 $ch $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li vert
+            popbox
+        }
+        if {$glc == 1} {
+            pushbox
+            box move w ${hw}um
+            sky130::draw_contact 0 $ch $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li vert
+            popbox
+        }
+    }
+
+    pushbox
+    box grow e ${hw}um
+    box grow w ${hw}um
+    box grow n ${hh}um
+    box grow s ${hh}um
+    # Create boundary using properties
+    property FIXED_BBOX [box values]
+    box grow c ${hx}um  ;# to edge of contact
+    box grow c ${diff_surround}um  ;# to edge of diffusion
+    box grow c ${sub_surround}um  ;# sub/well overlap of diff (NOT guard_sub)
+    paint $sub_type
+    set cext [sky130::getbox]
+    popbox
+    popbox
+
+    return $cext
+}
+
+#----------------------------------------------------------------
+# MOSFET: Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::mos_device {parameters} {
+
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set diffcov 100	;# percent coverage of diffusion contact
+    set polycov 100	;# percent coverage of poly contact
+    set topc 1		;# draw top poly contact
+    set botc 1		;# draw bottom poly contact
+    set evenodd 1	;# even or odd numbered device finger, in X
+    set dev_sub_type ""	;# device substrate type (if different from guard ring)
+    set min_effl 0	;# gate length below which finger pitch must be stretched
+    set diff_overlap_cont 0	;# extra overlap of end contact by diffusion
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Draw the diffusion and poly
+    pushbox
+    box size 0 0
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    set he [/ $min_effl 2.0]
+    if {$nf == 1 || $he < $hl} {set he $hl}
+    box grow n ${hw}um
+    box grow s ${hw}um
+    box grow e ${hl}um
+    box grow w ${hl}um
+    pushbox
+    if {${diff_extension} > ${gate_to_diffcont}} {
+        box grow e ${diff_extension}um
+        box grow w ${diff_extension}um
+    } else {
+        box grow e ${gate_to_diffcont}um
+        box grow w ${gate_to_diffcont}um
+    }
+    paint ${diff_type}
+    popbox
+    pushbox
+    if {${gate_extension} > ${gate_to_polycont}} {
+	box grow n ${gate_extension}um
+	box grow s ${gate_extension}um
+    } else {
+	if {$topc} {
+	    box grow n ${gate_to_polycont}um
+	} else {
+	    box grow n ${gate_extension}um
+	}
+	if {$botc} {
+	    box grow s ${gate_to_polycont}um
+	} else {
+	    box grow s ${gate_extension}um
+	}
+    }
+    paint ${poly_type}
+    set cext [sky130::getbox]
+    popbox
+    # save gate area now and paint later, so that diffusion surrounding the
+    # contact does not paint over the gate area, in case the gate type is
+    # not part of a "compose" entry in the techfile.
+    set gaterect [box values]
+    popbox
+
+    # Adjust position of contacts for dogbone geometry
+    # Rule 1: Minimize diffusion length.  Contacts only move out
+    # if width <  contact diffusion height.  They move out enough
+    # that the diffusion-to-poly spacing is satisfied.
+
+    set ddover 0
+    set cdwmin [+ ${contact_size} [* ${diff_surround} 2]]
+    set cstem [- ${gate_to_diffcont} [/ ${cdwmin} 2.0]]
+    set cgrow [- ${diff_poly_space} ${cstem}]
+    if {[+ ${w} ${eps}] < ${cdwmin}} {
+        if {${cgrow} > 0} {
+            set gate_to_diffcont [+ ${gate_to_diffcont} ${cgrow}]
+        }
+	set ddover [/ [- ${cdwmin} ${w}] 2.0]
+    }
+
+    # Rule 2: Minimum poly width.  Poly contacts only move out
+    # if length < contact poly width.  They move out enough
+    # that the diffusion-to-poly spacing is satisfied.
+
+    set gporig ${gate_to_polycont}
+    set cplmin [+ ${contact_size} [* ${poly_surround} 2]]
+    set cstem [- ${gate_to_polycont} [/ ${cplmin} 2.0]]
+    set cgrow [- ${diff_poly_space} ${cstem}]
+    if {[+ ${l} ${eps}] < ${cplmin}} {
+        if {${cgrow} > 0} {
+            set gate_to_polycont [+ ${gate_to_polycont} ${cgrow}]
+        }
+    }
+
+    # Rule 3: If both poly and diffusion are dogboned, then move
+    # poly out further to clear spacing to the diffusion contact
+
+    if {[+ ${w} ${eps}] < ${cdwmin}} {
+        if {[+ ${l} ${eps}] < ${cplmin}} {
+            set cgrow [/ [- ${cplmin} ${w}] 2.0]
+            set gate_to_polycont [+ ${gate_to_polycont} ${cgrow}]
+        }
+    }
+
+    # Rule 4: If M > 1 and poly contacts overlap, then increase the
+    # transistor-to-poly-contact distance by the amount of any
+    # diffusion dogbone overhang.
+
+    if {($poverlap == 1) && ($m > 1)} {
+	if {${gate_to_polycont} - $gporig < $ddover} {
+	    set gate_to_polycont [+ ${gporig} ${ddover}]
+	}
+    }
+
+    # Reduce contact sizes by poly or diffusion surround so that
+    # the contact area edges match the device diffusion or poly.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set tsurround [+ ${diff_surround} ${diff_overlap_cont}]
+    set cdw [- ${w} [* ${tsurround} 2]]		;# diff contact height
+    set cpl [- ${l} [* ${poly_surround} 2]]     ;# poly contact width
+
+    # Reduce by coverage percentage.  NOTE:  If overlapping multiple devices,
+    # keep maximum poly contact coverage.
+
+    set cdw [* ${cdw} [/ ${diffcov} 100.0]]
+    if {($poverlap == 0) || ($m == 1)} {
+	set cpl [* ${cpl} [/ ${polycov} 100.0]]
+    }
+
+    # Right diffusion contact
+    pushbox
+    box move e ${he}um
+    box move e ${gate_to_diffcont}um
+    set cext [sky130::unionbox $cext [sky130::draw_contact 0 ${cdw} \
+		${diff_surround} ${metal_surround} ${contact_size}\
+		${diff_type} ${diff_contact_type} li vert]]
+    popbox
+    # Left diffusion contact
+    pushbox
+    box move w ${he}um
+    box move w ${gate_to_diffcont}um
+    set cext [sky130::unionbox $cext [sky130::draw_contact 0 ${cdw} \
+		${diff_surround} ${metal_surround} ${contact_size} \
+		${diff_type} ${diff_contact_type} li vert]]
+    set diffarea $cext
+    popbox
+    # Top poly contact
+    if {$topc} {
+       pushbox
+       box move n ${hw}um
+       box move n ${gate_to_polycont}um
+       set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${poly_surround} ${metal_surround} ${contact_size} \
+		${poly_type} ${poly_contact_type} li horz]]
+       popbox
+    }
+    # Bottom poly contact
+    if {$botc} {
+       pushbox
+       box move s ${hw}um
+       box move s ${gate_to_polycont}um
+       set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${poly_surround} ${metal_surround} ${contact_size} \
+		${poly_type} ${poly_contact_type} li horz]]
+       popbox
+    }
+
+    # Now draw the gate, after contacts have been drawn
+    pushbox
+    box values {*}${gaterect}
+    # gate_type need not be defined if poly over diff paints the right type.
+    catch {paint ${gate_type}}
+    # sub_surround_dev, if defined, may create a larger area around the gate
+    # than sub_surround creates around the diffusion/poly area.
+    if [dict exists $parameters sub_surround_dev] {
+	box grow n ${sub_surround_dev}um
+	box grow s ${sub_surround_dev}um
+	box grow e ${sub_surround_dev}um
+	box grow w ${sub_surround_dev}um
+	paint ${dev_sub_type}
+	set cext [sky130::unionbox $cext [sky130::getbox]]
+    }
+    popbox
+
+    if {$dev_sub_type != ""} {
+	box values [lindex $diffarea 0]um [lindex $diffarea 1]um \
+	    [lindex $diffarea 2]um [lindex $diffarea 3]um
+	box grow n ${sub_surround}um
+	box grow s ${sub_surround}um
+	box grow e ${sub_surround}um
+	box grow w ${sub_surround}um
+	paint ${dev_sub_type}
+	set cext [sky130::unionbox $cext [sky130::getbox]]
+        # puts stdout "Diagnostic:  bounding box is $cext"
+    }
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# MOSFET: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::mos_draw {parameters} {
+    tech unlock *
+    set savesnap [snap]
+    snap internal
+
+    # Set defaults if they are not in parameters
+    set poverlap 0	;# overlap poly contacts when tiling
+    set doverlap 1	;# overlap diffusion contacts when tiling
+    set dev_sub_dist 0	;# substrate to guard ring, if dev_sub_type defined
+    set dev_sub_space 0	;# distance between substrate areas for arrayed devices
+    set min_allc 0	;# gate length below which poly contacts must be interleaved
+    set id_type ""	;# additional type covering everything
+    set id_surround 0	;# amount of surround on above type
+    set id2_type ""	;# additional type covering everything
+    set id2_surround 0	;# amount of surround on above type
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Diff-to-tap spacing is by default the same as diff spacing
+    if {![dict exist $parameters diff_tap_space]} {
+	set diff_tap_space $diff_spacing
+    }
+
+    # If poverlap is 1 then both poly contacts must be present
+    if {$poverlap == 1} {
+	set topc 1
+	set botc 1
+	dict set parameters topc 1
+	dict set parameters botc 1
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # If dx < (poly contact space + poly contact width), then there is not
+    # enough room for a row of contacts, so force alternating contacts
+
+    if {$nf > 1 && $l < $min_allc} {
+	set intc 1
+	set evenodd 1
+	set topc 1
+	set botc 1
+	dict set parameters topc 1
+	dict set parameters botc 1
+	set poverlap 0
+    } else {
+	set intc 0
+    }
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set bbox [sky130::mos_device $parameters]
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # If dev_sub_dist > 0 then each device must be in its own substrate
+    # (well) area, and overlaps are disallowed.  dev_sub_space determines
+    # the distance between individual devices in an array.
+
+    if {$dev_sub_dist > 0} {
+        set poverlap 0
+        set doverlap 0
+
+	if {$dev_sub_space > $poly_spacing} {
+	    set dx [+ $fw $dev_sub_space]
+	    set dy [+ $fh $dev_sub_space]
+	} else {
+	    set dx [+ $fw $poly_spacing]
+	    set dy [+ $fh $poly_spacing]
+	}
+
+    } else {
+
+	# Determine tile width and height (depends on overlap)
+	if {$poverlap == 0} {
+	    set dy [+ $fh $poly_spacing]
+	} else {
+	    # overlap poly
+	    set dy [- $fh [+ $poly_surround $poly_surround $contact_size]]
+	}
+
+	if {$doverlap == 0} {
+	    set dx [+ $fw $diff_spacing]
+	} else {
+	    # overlap diffusions
+	    set dx [- $fw [+ $diff_surround $diff_surround $contact_size]]
+	}
+    }
+
+    # Determine core width and height
+    set corex [+ [* [- $nf 1] $dx] $fw]
+    set corey [+ [* [- $m 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    # If there is a diffusion dogbone, and no top poly contact, then
+    # increase the core height by the amount of the dogbone overhang.
+
+    if {$topc == 0} {
+	set cdwmin [+ ${contact_size} [* ${diff_surround} 2]]
+	if {${w} < ${cdwmin}} {
+	    set corey [+ $corey [/ [- ${cdwmin} ${w}] 2.0]]
+	}
+    }
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	if {($dev_sub_dist > 0) && ([+ $dev_sub_dist $sub_surround] > $diff_tap_space)} {
+	    set gx [+ $corex [* 2.0 [+ $dev_sub_dist $diff_surround]] $contact_size]
+	} else {
+	    set gx [+ $corex [* 2.0 [+ $diff_tap_space $diff_surround]] $contact_size]
+	}
+	if {($dev_sub_dist > 0) && ([+ $dev_sub_dist $sub_surround] > $diff_gate_space)} {
+	    set gy [+ $corey [* 2.0 [+ $dev_sub_dist $diff_surround]] $contact_size]
+	} else {
+	    set gy [+ $corey [* 2.0 [+ $diff_gate_space $diff_surround]] $contact_size]
+	}
+
+	# Somewhat tricky. . . if the width is small and the diffusion is 
+	# a dogbone, and the top or bottom poly contact is missing, then
+	# the spacing to the guard ring may be limited by diffusion spacing, not
+	# poly to diffusion.
+
+	set inset [/ [+ $contact_size [* 2.0 $diff_surround] -$w] 2.0]
+	set sdiff [- [+ $inset $diff_tap_space] [+ $gate_extension $diff_gate_space]]
+
+	if {$sdiff > 0} {
+	    if {$topc == 0} {
+		set gy [+ $gy $sdiff]
+		set corelly [+ $corelly [/ $sdiff 2.0]]
+	    }
+	    if {$botc == 0} {
+		set gy [+ $gy $sdiff]
+		set corelly [- $corelly [/ $sdiff 2.0]]
+	    }
+	}
+
+	# Draw the guard ring first, as MOS well may interact with guard ring substrate
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    # If any surrounding identifier type is defined, draw it
+    if {${id_type} != ""} {
+	set hw [/ $gx 2]
+	set hh [/ $gy 2]
+	box grow e ${hw}um
+	box grow w ${hw}um
+	box grow n ${hh}um
+	box grow s ${hh}um
+	box grow c ${id_surround}um
+	paint ${id_type}
+    }
+    popbox
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    for {set xp 0} {$xp < $nf} {incr xp} {
+        pushbox
+	if {$intc == 1} {
+	    set evenodd [- 1 $evenodd]
+	    if {$evenodd == 1} {
+		dict set parameters topc 1
+		dict set parameters botc 0
+	    } else {
+		dict set parameters topc 0
+		dict set parameters botc 1
+	    }
+	    set saveeo $evenodd
+	}
+        for {set yp 0} {$yp < $m} {incr yp} {
+            sky130::mos_device $parameters
+            box move n ${dy}um
+	    if {$intc == 1} {
+		set evenodd [- 1 $evenodd]
+		if {$evenodd == 1} {
+		    dict set parameters topc 1
+		    dict set parameters botc 0
+		} else {
+		    dict set parameters topc 0
+		    dict set parameters botc 1
+		}
+	    }
+        }
+	if {$intc == 1} {
+	    set evenodd $saveeo
+	}
+        popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    snap $savesnap
+    tech revert
+}
+
+#-------------------
+# nMOS 1.8V
+#-------------------
+
+proc sky130::nshort_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nfet \
+	    diff_type 		ndiff \
+	    diff_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::nlowvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nfetlvt \
+	    diff_type 		ndiff \
+	    diff_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sonos_e_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nsonos \
+	    diff_type 		ndiff \
+	    diff_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    id_type		dnwell \
+	    id_surround		1.355 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#-------------------
+# pMOS 1.8V
+#-------------------
+
+proc sky130::pshort_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		pfet \
+	    diff_type 		pdiff \
+	    diff_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    gate_to_polycont	0.32 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::plowvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		pfetlvt \
+	    diff_type 		pdiff \
+	    diff_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    gate_to_polycont	0.32 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::phighvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		pfethvt \
+	    diff_type 		pdiff \
+	    diff_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    gate_to_polycont	0.32 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#-------------------
+# pMOS 5.0V
+#-------------------
+
+proc sky130::phv_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvpfet \
+	    diff_type 		mvpdiff \
+	    diff_contact_type	mvpdc \
+	    plus_diff_type	mvnsd \
+	    plus_contact_type	mvnsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    guard_sub_surround	0.33 \
+	    gate_to_polycont	0.32 \
+	    diff_spacing	0.31 \
+	    diff_tap_space	0.38 \
+	    diff_gate_space	0.38 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#-------------------
+# nMOS 5.0V
+#-------------------
+
+proc sky130::nhv_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvnfet \
+	    diff_type 		mvndiff \
+	    diff_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    diff_spacing	0.31 \
+	    diff_tap_space	0.38 \
+	    diff_gate_space	0.38 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::nhvnative_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvnnfet \
+	    diff_type 		mvndiff \
+	    diff_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    diff_spacing	0.30 \
+	    diff_tap_space	0.38 \
+	    diff_gate_space	0.38 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#------------------------
+# MOS varactor (1.8V)
+#------------------------
+
+proc sky130::xcnwvc_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		var \
+	    diff_type 		nnd \
+	    diff_contact_type	nsc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    dev_sub_type	nwell \
+	    diff_overlap_cont	0.06 \
+	    dev_sub_dist	0.14 \
+	    dev_sub_space	1.27 \
+	    gate_to_diffcont	0.34 \
+	    diff_extension	0.485 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::xcnwvc2_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		varhvt \
+	    diff_type 		nnd \
+	    diff_contact_type	nsc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    dev_sub_type	nwell \
+	    diff_overlap_cont	0.06 \
+	    dev_sub_dist	0.14 \
+	    dev_sub_space	1.27 \
+	    gate_to_diffcont	0.34 \
+	    diff_extension	0.485 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#---------------------------------------------------------
+# MOS varactor (5.0V)
+# NOTE:  dev_sub_space set to 2.0 assuming different nets.
+# Should have option for same-net with merged wells.
+#---------------------------------------------------------
+
+proc sky130::xchvnwc_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvvar \
+	    diff_type 		mvnsd \
+	    diff_contact_type	mvnsc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    dev_sub_type	nwell \
+	    sub_surround	0.38 \
+	    sub_surround_dev	0.56 \
+	    guard_sub_surround	0.18 \
+	    diff_overlap_cont	0.06 \
+	    dev_sub_dist	0.785 \
+	    dev_sub_space	2.0 \
+	    gate_to_diffcont	0.34 \
+	    diff_extension	0.485 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# MOSFET: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::mos_check {device parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l] 
+    set l [magic::3digitpastdecimal $l]
+    set w [magic::spice2float $w] 
+    set w [magic::3digitpastdecimal $w]
+
+    # nf, m must be integer
+    if {![string is int $nf]} {
+	puts stderr "NF must be an integer!"
+        dict set parameters nf 1
+    }
+    if {![string is int $m]} {
+	puts stderr "M must be an integer!"
+        dict set parameters m 1
+    }
+    # diffcov, polycov must be numeric
+    if {[catch {expr abs($diffcov)}]} {
+	puts stderr "diffcov must be numeric!"
+	set diffcov 100
+    }
+    if {[catch {expr abs($polycov)}]} {
+	puts stderr "polycov must be numeric!"
+	set polycov 100
+    }
+
+    if {$l < $lmin} {
+	puts stderr "Mos length must be >= $lmin um"
+        dict set parameters l $lmin
+    } 
+    if {$w < $wmin} {
+	puts stderr "Mos width must be >= $wmin um"
+        dict set parameters w $wmin
+    } 
+    if {$nf < 1} {
+	puts stderr "NF must be >= 1"
+        dict set parameters nf 1
+    } 
+    if {$m < 1} {
+	puts stderr "M must be >= 1"
+        dict set parameters m 1
+    } 
+    if {$diffcov < 20 } {
+	puts stderr "Diffusion contact coverage must be at least 20%"
+        dict set parameters diffcov 20
+    } elseif {$diffcov > 100 } {
+	puts stderr "Diffusion contact coverage can't be more than 100%"
+        dict set parameters diffcov 100
+    }
+    if {$polycov < 20 } {
+	puts stderr "Poly contact coverage must be at least 20%"
+        dict set parameters polycov 20
+    } elseif {$polycov > 100 } {
+	puts stderr "Poly contact coverage can't be more than 100%"
+        dict set parameters polycov 100
+    }
+
+    # Values must satisfy diffusion-to-tap spacing of 20um.
+    # Therefore the maximum of guard ring width or height cannot exceed 40um.
+    # If in violation, reduce counts first, as these are easiest to recover
+    # by duplicating the device and overlapping the wells.
+    set origm $m
+    set orignf $nf
+    while true {
+       set yext [expr ($w + 3.0) * $m]
+       set xext [expr ($l + 1.0) * $nf + 1.1]
+       if {[expr min($xext, $yext)] > 40.0} {
+          if {$yext > 40.0 && $m > 1} {
+	     incr m -1
+	  } elseif {$xext > 40.0 && $nf > 1} {
+	     incr nf -1
+	  } elseif {$yext > 40.0} {
+	     set w 37
+	     puts -nonewline stderr "Transistor width must be < 37 um"
+	     puts stderr " to avoid tap spacing violation."
+	     dict set parameters w $w
+	  } elseif {$xext > 40.0} {
+	     set l 37.9
+	     puts -nonewline stderr "Transistor length must be < 37.9 um"
+	     puts stderr " to avoid tap spacing violation."
+	     dict set parameters l $l
+	  }
+       } else {
+	  break
+       }
+    }
+    if {$m != $origm} {
+       puts stderr "Y repeat reduced to prevent tap distance violation"
+       dict set parameters m $m
+    }
+    if {$nf != $orignf} {
+       puts stderr "X repeat reduced to prevent tap distance violation"
+       dict set parameters nf $nf
+    }
+
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::nshort_check {parameters} {
+   return [sky130::mos_check nshort $parameters]
+}
+
+proc sky130::nlowvt_check {parameters} {
+   return [sky130::mos_check nlowvt $parameters]
+}
+
+proc sky130::sonos_e_check {parameters} {
+   return [sky130::mos_check sonos_e $parameters]
+}
+
+proc sky130::nhv_check {parameters} {
+   return [sky130::mos_check nhv $parameters]
+}
+
+proc sky130::nhvnative_check {parameters} {
+   return [sky130::mos_check nhvnative $parameters]
+}
+
+proc sky130::pshort_check {parameters} {
+   return [sky130::mos_check pshort $parameters]
+}
+
+proc sky130::plowvt_check {parameters} {
+   return [sky130::mos_check plowvt $parameters]
+}
+
+proc sky130::phighvt_check {parameters} {
+   return [sky130::mos_check phighvt $parameters]
+}
+
+proc sky130::phv_check {parameters} {
+   return [sky130::mos_check phv $parameters]
+}
+
+proc sky130::xcnwvc_check {parameters} {
+   return [sky130::mos_check xcnwvc $parameters]
+}
+
+proc sky130::xcnwvc2_check {parameters} {
+   return [sky130::mos_check xcnwvc2 $parameters]
+}
+
+proc sky130::xchvnwc_check {parameters} {
+   return [sky130::mos_check xchvnwc $parameters]
+}
+
+#----------------------------------------------------------------
+# Fixed device: Specify all user-editable default values
+#
+# deltax --- Additional horizontal space between devices
+# deltay --- Additional vertical space between devices
+# nx     --- Number of arrayed devices in X
+# ny     --- Number of arrayed devices in Y
+#
+# Note that these values, specifically nx, ny, deltax,
+# and deltay, are properties of the instance, not the cell.
+# They translate to the instance array x and y counts;  while
+# deltax is the x pitch less the cell width, and deltay is the
+# y pitch less the cell height.
+#
+# non-user-editable
+#
+# nocell --- Indicates that this cell has a predefined layout
+#	     and therefore there is no cell to draw.
+# xstep  --- Width of the cell (nominal array pitch in X)
+# ystep  --- Height of the cell (nominal array pitch in Y)
+#----------------------------------------------------------------
+
+# Fixed-layout devices (from sky130_fd_pr_base, _rf, and _rf2 libraries)
+#
+# Bipolar transistors:
+#
+# sky130_fd_pr_rf_npn_1x1
+# sky130_fd_pr_rf_npn_1x2
+# sky130_fd_pr_rf_pnp5x
+#
+# Parallel Plate Capacitors:
+#
+# sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield
+# sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield
+# sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield
+# sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield
+# sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield
+# sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield
+# sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield
+# sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield
+# sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield
+# sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4
+# sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield
+# sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield
+# sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield
+# sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield
+# sky130_fd_pr_rf_xcmvpp2
+# sky130_fd_pr_rf_xcmvpp2_nwell
+# sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield
+# sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield
+# sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield
+# sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield
+#
+# Inductors:
+#
+# balun
+# xind4_011
+# xind4_02
+
+proc sky130::sky130_fd_pr_rf_npn_1x1_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 7.03 ystep 7.03}
+}
+
+proc sky130::sky130_fd_pr_rf_npn_1x2_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 7.03 ystep 8.03}
+}
+
+proc sky130::sky130_fd_pr_rf_pnp5x_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 6.44 ystep 6.44}
+}
+
+proc sky130::balun_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 292 ystep 292}
+}
+
+proc sky130::xind4_02_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 258 ystep 258}
+}
+
+proc sky130::xind4_011_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 290 ystep 404}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 4.05 ystep 4.26}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 6.47 ystep 5.76}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 6.47 ystep 5.76}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 8.25 ystep 7.51}
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 10.41 ystep 11.54}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 1.77 ystep 1.77}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 3.88 ystep 3.88}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 4.55 ystep 4.76}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_nwell_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 4.55 ystep 4.76}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 4.05 ystep 4.26}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 4.05 ystep 4.26}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 8.25 ystep 7.51}
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 8.25 ystep 7.51}
+}
+
+#----------------------------------------------------------------
+# Fixed device: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::fixed_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    m {
+		 dict set pdkparams nx $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr_rf_npn_1x1_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_npn_1x2_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_pnp5x_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::balun_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::xind4_011_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::xind4_02_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_nwell_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# Fixed device: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::fixed_dialog {parameters} {
+    # Instance fields:	    nx, ny, pitchx, pitchy
+    # Editable fields:	    nx, ny, deltax, deltay
+    # Non-editable fields:  nocell, xstep, ystep
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # "nocell" field causes nx and ny to be dropped in from
+    # "array count".  Also "pitchx" and "pitchy" are passed
+    # in internal units.  Convert these to microns and generate
+    # If there is no pitchx and pitchy, then the device has not
+    # yet been created, so keep the deltax and deltay defaults.
+
+    if [dict exists $parameters pitchx] {
+	set pitchux [magic::i2u $pitchx]
+	set stepux [magic::spice2float $xstep]
+        set deltax [magic::3digitpastdecimal [expr $pitchux - $stepux]] 
+        # An array size 1 should not cause deltax to go negative
+	if {$deltax < 0.0} {set deltax 0.0}
+	dict set parameters deltax $deltax
+    }
+    if [dict exists $parameters pitchy] {
+	set pitchuy [magic::i2u $pitchy]
+	set stepuy [magic::spice2float $ystep]
+        set deltay [magic::3digitpastdecimal [expr $pitchuy - $stepuy]] 
+        # An array size 1 should not cause deltay to go negative
+	if {$deltay < 0.0} {set deltay 0.0}
+	dict set parameters deltay $deltay
+    }
+
+    magic::add_entry nx "NX" $parameters
+    magic::add_entry ny "NY" $parameters
+    magic::add_entry deltax "X step (um)" $parameters
+    magic::add_entry deltay "Y step (um)" $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_npn_1x1_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_npn_1x2_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_pnp5x_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::balun_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::xind4_011_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::xind4_02_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_nwell_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+#----------------------------------------------------------------
+# Fixed device: Draw the device
+#----------------------------------------------------------------
+
+proc sky130::fixed_draw {devname parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # This cell declares "nocell" in parameters, so it needs to
+    # instance the cell and set properties.
+
+    # Instantiate the cell.  The name corresponds to the cell in the sky130_fd_pr_* directory.
+    set instname [getcell ${devname}]
+
+    set deltax [magic::spice2float $deltax] 
+    set deltay [magic::spice2float $deltay] 
+    set xstep [magic::spice2float $xstep] 
+    set ystep [magic::spice2float $ystep] 
+
+    # Array stepping
+    if {$nx > 1 || $ny > 1} {
+        set xstep [expr $xstep + $deltax]
+        set ystep [expr $ystep + $deltay]
+        box size ${xstep}um ${ystep}um
+	array $nx $ny
+    }
+    select cell $instname
+    expand
+    return $instname
+}
+
+#----------------------------------------------------------------
+# No additional parameters declared for drawing
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr_rf_npn_1x1_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_npn_1x1 $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_npn_1x2_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_npn_1x2 $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_pnp5x_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_pnp5x $parameters]
+}
+
+proc sky130::balun_draw {parameters} {
+    return [sky130::fixed_draw balun $parameters]
+}
+
+proc sky130::xind4_011_draw {parameters} {
+    return [sky130::fixed_draw xind4_011 $parameters]
+}
+
+proc sky130::xind4_02_draw {parameters} {
+    return [sky130::fixed_draw xind4_02 $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4 $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp2 $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_nwell_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp2_nwell $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield $parameters]
+}
+
+#----------------------------------------------------------------
+# Fixed device: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::fixed_check {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set deltax [magic::spice2float $deltax -1] 
+    set deltax [magic::3digitpastdecimal $deltax]
+    set deltay [magic::spice2float $deltay -1] 
+    set deltay [magic::3digitpastdecimal $deltay]
+
+    # nx, ny must be integer
+    if {![string is int $nx]} {
+	puts stderr "NX must be an integer!"
+        dict set parameters nx 1
+    }
+    if {![string is int $ny]} {
+	puts stderr "NY must be an integer!"
+        dict set parameters nx 1
+    }
+
+    # Number of devices in X and Y must be at least 1
+    if {$nx < 1} {
+	puts stderr "NX must be >= 1"
+        dict set parameters nx 1
+    }
+    if {$ny < 1} {
+	puts stderr "NY must be >= 1"
+        dict set parameters nx 1
+    }
+    # Step less than zero violates DRC
+    if {$deltax < 0} {
+	puts stderr "X step must be >= 0"
+        dict set parameters deltax 0
+    }
+    if {$deltay < 0} {
+	puts stderr "Y step must be >= 0"
+        dict set parameters deltay 0
+    }
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr_rf_npn_1x1_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_npn_1x2_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_pnp5x_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::balun_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::xind4_011_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::xind4_02_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp2_nwell_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
diff --git a/sky130/sky130.tech b/sky130/sky130.tech
new file mode 100644
index 0000000..881eee2
--- /dev/null
+++ b/sky130/sky130.tech
@@ -0,0 +1,4004 @@
+###
+###	Source file sky130.tech
+###	Process this file with the preproc.py macro processor
+###	Note that the tech name is always TECHNAME for
+###	magic;  this keeps compatibility between layouts
+###	for all process variants.
+###
+#----------------------------------------------------------
+# Copyright (c) 2020 R. Timothy Edwards
+# Revisions:  See below
+#
+# This file is an Open Source foundry process describing
+# the SkyWater S8 hybrid 0.18um / 0.13um fabrication
+# process.  The file may be distributed under the terms
+# of the (Apache 2.0(?)) license agreement.
+#
+#----------------------------------------------------------
+# This file is designed to be used with magic versions
+# 8.3.24 or newer.
+#----------------------------------------------------------
+tech
+  format 35
+  TECHNAME
+end
+
+version
+ version REVISION
+ description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
+end
+
+#----------------------------------------------------------
+# Status: 3/17/19: s8.tech created from xh018.tech
+#
+# Status: 3/20/19: Rev 0 (pre-alpha):
+# Work in progress.  Converted from original techfile to S8
+# with all sections updated with as much information as could
+# be immediately gleaned from the documentation.  Cifinput and
+# DRC sections have been checked against one standard cell
+# library.
+#
+# Status 5/5/20: Rev 1 (alpha):
+# Changed name from s8 to sky130
+#--------------------------------------------------------------
+
+#--------------------------------------------------------------
+# Supported device types
+#--------------------------------------------------------------
+# device name   magic ID layer  description
+#-------------------------------------------------------------
+# nshort	nfet		standard nFET
+# nshort	scnfet		standard nFET in standard cell**
+# nlowvt	nfetlvt		low Vt nFET
+# sonos_p/e	nsonos		SONOS nFET
+# pshort	pfet		standard pFET
+# pshort	scpfet		standard pFET in standard cell**
+# plowvt	pfetlvt		low Vt pFET
+# phighvt	pfethvt		high Vt pFET
+# ntvnative	---		native nFET
+# phv		mvpfet		thickox pFET
+# nhv		mvnfet		thickox nFET
+# nhvnative	mvnnfet		thickox native nFET
+# ndiode	ndiode		n+ diff diode
+# ndiode_h	mvndiode	thickox n+ diff diode
+# pdiode	pdiode		p+ diff diode
+# pdiode_h	mvpdiode	thickox p+ diff diode
+# ndiode_native	nndiode		diode with nndiff
+# ndiode_lvt	ndiodelvt	low Vt n+ diff diode
+# pdiode_lvt	pdiodelvt	low Vt p+ diff diode
+# pdiode_hvt	pdiodehvt	high Vt p+ diff diode
+# nwdiode	---		nwell diode
+# dnwdiode_psub	---		deep nwell diode to substrate
+# dnwdiode_pw	---		deep nwell diode to pwell
+# xcmimc1	mimcap		MiM cap 1st plate
+# xcmimc2	mimcap2		MiM cap 2nd plate
+# mrdn		rdn		n+ diff resistor
+# mrdn_hv	mvrdn		thickox n+ diff resistor
+# mrdp		rdp		p+ diff resistor
+# mrdp_hv	mvrdp		thickox p+ diff resistor
+# mrl1		rli		local interconnect resistor
+# mrp1		npres		n+ poly resistor
+# xhrpoly_*	ppres (*)	p+ poly resistor (300 Ohms/sq)
+# uhrpoly_*	xres (*)	p+ poly resistor (2k Ohms/sq)
+# xcnwvc	varactor	varactor (low Vt?)
+# xcnwvc2	varactorhvt	high Vt varactor
+# xchvnwc	mvvaractor	thickox varactor
+# xpwres	rpw		pwell resistor (in deep nwell)
+#
+# (*) Note that ppres may extract into some generic type
+# called "xhrpoly", but only specific sizes of xhrpoly are
+# allowed, and these are created from fixed layouts like the
+# types below.
+#
+# (**) nFET and pFET in standard cells are the same as devices
+# outside of the standard cell except for the DRC rule for
+# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
+#
+# To avoid creating a large number of types, a few ID layers are
+# used in conjunction with standard devices types:  "lvt" for
+# low threshold voltage, and "hvt" for high threshold voltage.
+# "dnwell" is used as an identifier layer where appropriate.
+# Layer HVI (thick oxide) is treated differently, and types
+# "mv*" are defined where thick oxide is required.
+#
+#-------------------------------------------------------------
+# The following devices are not extracted but are represented
+# only by script-generated subcells in the PDK.
+#-------------------------------------------------------------
+# nshortesd			ESD nFET
+# nhvesd			ESD thickox nFET
+# nhvnativeesd			ESD native nFET
+# phvesd			ESD thickox pFET
+# fnpass			flash nFET device
+# npnpar1x*			parasitic NPN
+# npn_1x1_2p0_hv		thickox gated parasitic NPN
+# pnppar			parasitic PNP
+# pnppar5x			parasitic PNP
+# xesd_ndiode_h_***		ESD n+ diode
+# xesd_pdiode_h_***		ESD p+ diode
+# reslocsub			local substrate island indicator
+# xcmvpp			Vpp cap
+# xcmvpp_2			Vpp cap
+# xcmvpp_*			Vpp cap
+# xcmvpp*			Vpp cap
+# balun				balun inductor
+# ind4				inductor
+# fuse				metal fuse device
+#--------------------------------------------------------------
+
+#-----------------------------------------------------
+# Tile planes
+#-----------------------------------------------------
+
+planes
+  dwell,dw
+  well,w
+  active,a
+  locali,li1,li
+  metal1,m1
+  metal2,m2
+  metal3,m3
+#ifdef METAL5
+#ifdef MIM
+  cap1,c1
+#endif (MIM)
+  metal4,m4
+#ifdef MIM
+  cap2,c2
+#endif (MIM)
+  metal5,m5
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+  metali,mi
+#endif
+  block,b
+  comment,c
+end
+
+#-----------------------------------------------------
+# Tile types
+#-----------------------------------------------------
+
+types
+# Deep nwell
+  dwell dnwell,dnw
+
+# Wells
+  well nwell,nw
+ -well pwell,pw
+ -well rpw,rpwell
+ -well obswell
+
+# Transistors
+  active nmos,ntransistor,nfet
+ -active scnmos,scntransistor,scnfet
+  active pmos,ptransistor,pfet
+ -active scpmos,scptransistor,scpfet
+ -active nnmos,nntransistor
+  active mvnmos,mvntransistor,mvnfet
+  active mvpmos,mvptransistor,mvpfet
+ -active mvnnmos,mvnntransistor,mvnnfet,nnfet
+ -active varactor,varact,var
+ -active mvvaractor,mvvaract,mvvar
+
+ -active pmoslvt,pfetlvt
+ -active pmoshvt,pfethvt
+ -active nmoslvt,nfetlvt
+ -active varactorhvt,varacthvt,varhvt
+ -active nsonos,sonos
+
+# Diffusions
+  active ndiff,ndiffusion,ndif
+  active pdiff,pdiffusion,pdif
+ -active mvndiff,mvndiffusion,mvndif
+ -active mvpdiff,mvpdiffusion,mvpdif
+  active ndiffc,ndcontact,ndc
+  active pdiffc,pdcontact,pdc
+ -active mvndiffc,mvndcontact,mvndc
+ -active mvpdiffc,mvpdcontact,mvpdc
+  active psubdiff,psubstratepdiff,ppdiff,ppd,psd
+  active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
+ -active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
+ -active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
+  active psubdiffcont,psubstratepcontact,psc
+  active nsubdiffcont,nsubstratencontact,nsc
+ -active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
+ -active mvnsubdiffcont,mvnsubstratencontact,mvnsc
+ -active obsactive
+ -active mvobsactive
+
+# Poly
+  active poly,p,polysilicon
+  active polycont,pc,pcontact,polycut,polyc
+  active xpolycontact,xpolyc,xpc
+
+# Resistors
+ -active npolyres,npres,mrp1
+ -active ppolyres,ppres,xhrpoly
+ -active xpolyres,xpres,xres,uhrpoly
+ -active ndiffres,rnd,rdn,rndiff
+ -active pdiffres,rpd,rdp,rpdiff
+ -active mvndiffres,mvrnd,mvrdn,mvrndiff
+ -active mvpdiffres,mvrpd,mvrdp,mvrpdiff
+ -active rmp
+
+# Diodes
+ -active pdiode,pdi
+ -active ndiode,ndi
+ -active nndiode,nndi
+ -active pdiodec,pdic
+ -active ndiodec,ndic
+ -active nndiodec,nndic
+ -active mvpdiode,mvpdi
+ -active mvndiode,mvndi
+ -active mvpdiodec,mvpdic
+ -active mvndiodec,mvndic
+ -active pdiodelvt,pdilvt
+ -active pdiodehvt,pdihvt
+ -active ndiodelvt,ndilvt
+ -active pdiodelvtc,pdilvtc
+ -active pdiodehvtc,pdihvtc
+ -active ndiodelvtc,ndilvtc
+
+# Local Interconnect 
+  locali locali,li1,li
+ -locali corelocali,coreli1,coreli
+ -locali rlocali,rli1,rli
+  locali viali,vial,lic,licon,m1c,v0
+ -locali obsli1,obsli
+ -locali obsli1c,obslic,obslicon
+
+# Metal 1
+  metal1 metal1,m1,met1
+ -metal1 rmetal1,rm1,rmet1
+  metal1 via1,m2contact,m2cut,m2c,via,v,v1
+ -metal1 obsm1
+ -metal1 padl
+
+# Metal 2
+  metal2 metal2,m2,met2
+ -metal2 rmetal2,rm2,rmet2
+  metal2 via2,m3contact,m3cut,m3c,v2
+ -metal2 obsm2
+
+# Metal 3
+  metal3 metal3,m3,met3
+ -metal3 rmetal3,rm3,rmet3
+ -metal3 obsm3
+#ifdef METAL5
+  metal3 via3,v3
+
+#ifdef MIM
+ -cap1 mimcap,mim,capm
+ -cap1 mimcapcontact,mimcapc,mimcc,capmc
+#endif
+
+# Metal 4
+  metal4 metal4,m4,met4
+ -metal4 rmetal4,rm4,rmet4
+ -metal4 obsm4
+  metal4 via4,v4
+
+#ifdef MIM
+ -cap2 mimcap2,mim2,capm2
+ -cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
+#endif
+
+# Metal 5
+  metal5 metal5,m5,met5
+ -metal5 rm5,rmetal5,rmet5
+ -metal5 obsm5
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+ -metal5 mrdlcontact,mrdlc
+ -metali metalrdl,mrdl,metrdl
+ -metali obsmrdl
+#endif (REDISTRIBUTION)
+
+# Miscellaneous
+ -block  glass
+ -block  fillblock
+ -comment comment
+ -comment obscomment
+
+end
+
+#-----------------------------------------------------
+# Magic contact types
+#-----------------------------------------------------
+
+contact
+  pc       poly       locali
+  ndc      ndiff      locali
+  pdc      pdiff      locali
+  nsc      nsd        locali
+  psc      psd        locali
+  ndic     ndiode     locali
+  ndilvtc  ndiodelvt  locali
+  nndic    nndiode    locali
+  pdic     pdiode     locali
+  pdilvtc  pdiodelvt  locali
+  pdihvtc  pdiodehvt  locali
+  xpc      xpc        locali
+
+  mvndc   mvndiff   locali
+  mvpdc   mvpdiff   locali
+  mvnsc   mvnsd     locali
+  mvpsc   mvpsd     locali
+  mvndic  mvndiode  locali
+  mvpdic  mvpdiode  locali
+
+  lic locali metal1
+  obslic obsli obsm1
+
+  via1   metal1 metal2
+  via2   metal2 metal3
+#ifdef METAL5
+  via3   metal3 metal4
+  via4   metal4 metal5
+#endif (METAL5)
+  stackable
+
+#ifdef METAL5
+#ifdef MIM
+  # MiM cap contacts are not stackable!
+  mimcc  mimcap metal4
+  mim2cc mimcap2 metal5
+#endif (MIM)
+
+  padl m1 m2 m3 m4 m5 glass
+#else
+  padl m1 m2 m3 glass
+#endif  (!METAL5)
+
+#ifdef REDISTRIBUTION
+  mrdlc metal5 mrdl
+#endif (REDISTRIBUTION)
+end
+
+#-----------------------------------------------------
+# Layer aliases
+#-----------------------------------------------------
+
+aliases
+
+  allwellplane     nwell
+  allnwell	   nwell,obswell
+
+  allnfets	   nfet,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
+  allpfets	   pfet,scpfet,mvpfet,pfethvt,pfetlvt
+  allfets	   allnfets,allpfets,varactor,mvvaractor,varhvt
+
+  allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
+  allnactive	   allnactivenonfet,allnfets
+  allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
+  allnactivetap	   *nsd,*mvnsd,var,varhvt,mvvar
+
+  allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
+  allpactive	   allpactivenonfet,allpfets
+  allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
+  allpactivetap    *psd,*mvpsd
+
+  allactivenonfet  allnactivenonfet,allpactivenonfet
+  allactive	   allactivenonfet,allfets
+
+  allactiveres	   ndiffres,pdiffres,mvndiffres,mvpdiffres
+
+  allndifflv       *ndif,*nsd,*ndiode,ndiffres,nfet,scnfet,nfetlvt,nsonos
+  allpdifflv       *pdif,*psd,*pdiode,pdiffres,pfet,scpfet,pfetlvt,pfethvt
+  alldifflv        allndifflv,allpdifflv
+  allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
+  allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
+  alldifflvnonfet  allndifflvnonfet,allpdifflvnonfet
+
+  allndiffmv       *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+  allpdiffmv       *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
+  alldiffmv        allndiffmv,allpdiffmv
+  allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+  allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
+  alldiffmvnontap  allndiffmvnontap,allpdiffmvnontap
+  allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
+  allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
+  alldiffmvnonfet  allndiffmvnonfet,allpdiffmvnonfet
+
+  alldiffnonfet	   alldifflvnonfet,alldiffmvnonfet
+  alldiff	   alldifflv,alldiffmv
+
+  allpolyres	   mrp1,xhrpoly,uhrpoly,rmp
+  allpolynonfet	   *poly,allpolyres,xpc
+  allpolynonres	   *poly,allfets,xpc
+
+  allpoly	   allpolynonfet,allfets
+  allpolynoncap	   *poly,xpc,allfets,allpolyres
+
+  allndiffcontlv   ndc,nsc,ndic,nndic,ndilvtc
+  allpdiffcontlv   pdc,psc,pdic,pdilvtc,pdihvtc
+  allndiffcontmv   mvndc,mvnsc,mvndic
+  allpdiffcontmv   mvpdc,mvpsc,mvpdic
+  allndiffcont	   allndiffcontlv,allndiffcontmv
+  allpdiffcont	   allpdiffcontlv,allpdiffcontmv
+  alldiffcontlv	   allndiffcontlv,allpdiffcontlv
+  alldiffcontmv	   allndiffcontmv,allpdiffcontmv
+  alldiffcont	   alldiffcontlv,alldiffcontmv
+
+  allcont	alldiffcont,pc
+
+  allres	allpolyres,allactiveres
+
+  allli		*locali,coreli,rli
+  allm1		*m1,rm1
+  allm2		*m2,rm2
+  allm3		*m3,rm3
+#ifdef METAL5
+  allm4	   	*m4,rm4
+  allm5	   	*m5,rm5
+#endif (METAL5)
+
+  allpad	padl
+
+  psub		pwell
+  
+end
+
+#-----------------------------------------------------
+# Layer drawing styles
+#-----------------------------------------------------
+
+styles
+ styletype mos
+  dnwell    cwell
+  nwell     nwell
+  pwell	    pwell
+  rpwell    pwell 	ptransistor_stripes
+  ndiff     ndiffusion
+  pdiff     pdiffusion
+  nsd       ndiff_in_nwell
+  psd       pdiff_in_pwell
+  nfet      ntransistor    ntransistor_stripes
+  scnfet    ntransistor    ntransistor_stripes
+  pfet      ptransistor    ptransistor_stripes
+  scpfet    ptransistor    ptransistor_stripes
+  var       polysilicon    ndiff_in_nwell
+  ndc       ndiffusion     metal1  contact_X'es
+  pdc       pdiffusion     metal1  contact_X'es
+  nsc       ndiff_in_nwell metal1  contact_X'es
+  psc       pdiff_in_pwell metal1  contact_X'es
+
+  pfetlvt   ptransistor	ptransistor_stripes implant1
+  pfethvt   ptransistor ptransistor_stripes implant2
+  nfetlvt   ntransistor ntransistor_stripes implant1
+  nsonos    ntransistor implant3
+  varhvt    polysilicon ndiff_in_nwell implant2
+
+  mvndiff   ndiffusion     hvndiff_mask
+  mvpdiff   pdiffusion     hvpdiff_mask
+  mvnsd     ndiff_in_nwell hvndiff_mask
+  mvpsd     pdiff_in_pwell hvpdiff_mask
+  mvnfet    ntransistor    ntransistor_stripes hvndiff_mask
+  mvnnfet   ntransistor    ndiff_in_nwell hvndiff_mask
+  mvpfet    ptransistor    ptransistor_stripes
+  mvvar     polysilicon    ndiff_in_nwell hvndiff_mask
+  mvndc     ndiffusion     metal1  contact_X'es hvndiff_mask
+  mvpdc     pdiffusion     metal1  contact_X'es hvpdiff_mask
+  mvnsc     ndiff_in_nwell metal1  contact_X'es hvndiff_mask
+  mvpsc     pdiff_in_pwell metal1  contact_X'es hvpdiff_mask
+
+  poly      polysilicon 
+  pc        polysilicon    metal1  contact_X'es
+  npolyres  polysilicon    silicide_block nselect2
+  ppolyres  polysilicon    silicide_block pselect2
+  xpc	    polysilicon	   pselect2  metal1  contact_X'es
+  rmp	    polysilicon	   poly_resist_stripes
+
+  pdiode    pdiffusion     pselect2
+  ndiode    ndiffusion     nselect2
+  pdiodec   pdiffusion     pselect2 metal1 contact_X'es
+  ndiodec   ndiffusion     nselect2 metal1 contact_X'es
+
+  nndiode   ndiffusion  nselect2 implant3
+  ndiodelvt ndiffusion	nselect2 implant1
+  pdiodelvt pdiffusion  pselect2 implant1
+  pdiodehvt pdiffusion  pselect2 implant2
+  pdilvtc   pdiffusion  pselect2 implant1 metal1 contact_X'es
+  pdihvtc   pdiffusion  pselect2 implant2 metal1 contact_X'es
+  ndilvtc   ndiffusion  nselect2 implant1 metal1 contact_X'es
+
+  mvpdiode    pdiffusion     pselect2 hvpdiff_mask
+  mvndiode    ndiffusion     nselect2 hvndiff_mask
+  mvpdiodec   pdiffusion     pselect2 metal1 contact_X'es hvpdiff_mask
+  mvndiodec   ndiffusion     nselect2 metal1 contact_X'es hvndiff_mask
+  nndiodec    ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
+
+  locali    metal1
+  coreli    metal1
+  rli       metal1         poly_resist_stripes
+  lic	    metal1	   metal2 via1arrow
+  obsli     metal1
+  obslic    metal1	   metal2 via1arrow
+
+  metal1    metal2
+  rm1       metal2         poly_resist_stripes
+  obsm1     metal2
+  m2c       metal2         metal3  via2arrow
+  metal2    metal3
+  rm2       metal3         poly_resist_stripes
+  obsm2     metal3
+  m3c       metal3         metal4  via3alt
+  metal3    metal4
+  rm3       metal4         poly_resist_stripes
+  obsm3     metal4
+#ifdef METAL5
+#ifdef MIM
+  mimcap    metal3         mems
+  mimcc     metal3         contact_X'es mems
+  mimcap2   metal4         mems
+  mim2cc    metal4         contact_X'es mems
+#endif (MIM)
+  via3      metal4         metal5  via4
+  metal4    metal5
+  rm4       metal5         poly_resist_stripes
+  obsm4     metal5
+  via4      metal5         metal6  via5
+  metal5    metal6
+  rm5       metal6         poly_resist_stripes
+  obsm5     metal6
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+  mrdlc	    metal6  metal7  via6
+  metalrdl  metal7
+  obsmrdl   metal7
+#endif (REDISTRIBUTION)
+
+  glass	    overglass
+  mrp1      poly_resist    poly_resist_stripes
+  xhrpoly   poly_resist    silicide_block
+  uhrpoly   poly_resist
+  ndiffres  ndiffusion	   ndop_stripes
+  pdiffres  pdiffusion	   pdop_stripes
+  mvndiffres  ndiffusion hvndiff_mask   ndop_stripes
+  mvpdiffres  pdiffusion hvpdiff_mask   pdop_stripes
+  comment   comment
+  error_p   error_waffle
+  error_s   error_waffle
+  error_ps  error_waffle
+  fillblock cwell
+
+  obswell   cwell
+  obsactive implant4
+
+#ifndef METAL5
+  padl      metal4 via4 overglass
+#else
+  padl      metal6 via6 overglass
+#endif
+
+  magnet    substrate_field_implant
+  rotate    via3alt
+  fence     via5
+end
+
+#-----------------------------------------------------
+# Special paint/erase rules
+#-----------------------------------------------------
+
+compose
+  compose  nfet  poly  ndiff
+  compose  pfet  poly  pdiff
+  compose  var   poly  nsd
+
+  compose  mvnfet  poly  mvndiff
+  compose  mvpfet  poly  mvpdiff
+  compose  mvvar   poly  mvnsd
+  
+  paint  ndc     nwell  pdc
+  paint  nfet    nwell  pfet
+  paint  scnfet  nwell  scpfet
+  paint  ndiff   nwell  pdiff
+  paint  psd     nwell  nsd
+  paint  psc     nwell  nsc
+
+  paint  pdc     pwell  ndc
+  paint  pfet    pwell  nfet
+  paint  scpfet  pwell  scnfet
+  paint  pdiff   pwell  ndiff
+  paint  nsd     pwell  psd
+  paint  nsc     pwell  psc
+
+  paint  pdc	 coreli pdc
+  paint  ndc	 coreli ndc
+  paint  pc	 coreli pc
+  paint  nsc 	 coreli pc
+  paint  psc 	 coreli pc
+  paint  viali 	 coreli viali
+
+  paint  coreli  pdc    pdc
+  paint  coreli  ndc    ndc
+  paint  coreli  pc     pc
+  paint  coreli  nsc    nsc
+  paint  coreli  psc    psc
+  paint  coreli  viali  viali
+
+#ifdef METAL5
+  paint  m4      obsm4  m4
+  paint  m5      obsm5  m5
+#endif (METAL5)
+end
+
+#-----------------------------------------------------
+# Electrical connectivity
+#-----------------------------------------------------
+
+connect
+  *nwell,*nsd,*mvnsd,dnwell *nwell,*nsd,*mvnsd,dnwell
+  pwell,*psd,*mvpsd  pwell,*psd,*mvpsd
+  *li,coreli	*li,coreli
+  *m1	*m1
+  *m2	*m2
+  *m3	*m3
+#ifdef METAL5
+  *m4	*m4
+  *m5	*m5
+#ifdef MIM
+  *mimcap     *mimcap
+  *mimcap2    *mimcap2
+#endif (MIM)
+#endif (METAL5)
+   allnactivenonfet	allnactivenonfet
+   allpactivenonfet	allpactivenonfet
+  *poly,xpc,allfets	*poly,xpc,allfets
+#ifdef REDISTRIBUTION
+  # RDL connects to m5 (i.e., padl) through glass cut
+  *mrdl			*mrdl
+  glass			metrdl
+#endif (REDISTRIBUTION)
+end
+
+#-----------------------------------------------------
+# CIF/GDS output layer definitions
+#-----------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+
+cifoutput
+
+#----------------------------------------------------------------
+style gdsii
+# NOTE: This section is used for actual GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Create a temp layer from the cell bounding box for use in
+# generating ID layers.  Note that "boundary", unlike "bbox",
+# requires the FIXED_BBOX property (abutment box) in the cell.
+#----------------------------------------------------------------
+ templayer CELLBOUND
+	boundary
+
+#----------------------------------------------------------------
+# BOUND
+#----------------------------------------------------------------
+ layer 	BOUND CELLBOUND
+	calma 235 4
+
+# Create a boundary outside of an abutment box, so that layers
+# can be made to stretch to the abutment box edges.  First strink
+# so that any box that would be so small as to interact with
+# itself will be removed.
+
+ templayer CELLRING CELLBOUND
+	shrink 345
+	grow 545
+	and-not CELLBOUND
+
+#----------------------------------------------------------------
+# DNWELL
+#----------------------------------------------------------------
+
+ layer DNWELL	dnwell
+	calma	64 18
+
+ layer PWRES    rpw
+	and	dnwell
+	calma	64 13
+
+#----------------------------------------------------------------
+# NWELL
+#----------------------------------------------------------------
+
+ layer NWELL 	allnwell
+	bloat-all rpw dnwell
+	and-not rpw,pwell
+ 	calma 	64 20
+
+ layer WELLTXT
+ 	labels allnwell noport
+	calma 64 16
+
+ layer WELLPIN
+ 	labels allnwell port
+	calma 64 5
+
+#----------------------------------------------------------------
+# SUB (text/port only)
+#----------------------------------------------------------------
+
+ layer SUBTXT
+ 	labels pwell noport
+	calma 122 16
+
+ layer SUBPIN
+ 	labels pwell port
+	calma 64 59
+
+#----------------------------------------------------------------
+# DIFF
+#----------------------------------------------------------------
+
+ layer DIFF 	allnactivenontap,allpactivenontap,allactiveres
+ 	labels 	allnactivenontap,allpactivenontap
+ 	calma 	65 20
+
+#----------------------------------------------------------------
+# TAP
+#----------------------------------------------------------------
+
+ layer TAP 	allnactivetap,allpactivetap
+ 	labels 	allnactivetap,allpactivetap
+ 	calma 	65 44
+
+#----------------------------------------------------------------
+# PPLUS, NPLUS (PSDM, NSDM)
+#----------------------------------------------------------------
+
+ templayer basePPLUS pdiffres,mvpdiffres
+	grow	15
+	or	xhrpoly,uhrpoly,xpc
+	grow	110
+	bloat-or allpactivetap * 125 allnactivenontap 0
+	bloat-or allpactivenontap * 125 allnactivetap 0
+	bridge	380 380
+
+ templayer extendPPLUS  basePPLUS,CELLRING
+	grow	185
+	shrink	185
+	and-not	CELLRING
+
+ layer PPLUS basePPLUS,extendPPLUS 
+	close   265000
+	calma	94 20
+
+ templayer baseNPLUS ndiffres,mvndiffres
+ 	grow	125
+	bloat-or allnactivetap * 125 allpactivenontap 0
+	bloat-or allnactivenontap * 125 allpactivetap 0
+	bridge	380 380
+
+ templayer extendNPLUS  baseNPLUS,CELLRING
+ 	grow	185
+ 	shrink	185
+	and-not	CELLRING
+
+ layer NPLUS baseNPLUS,extendNPLUS
+ 	close   265000
+ 	calma	93 44
+
+#----------------------------------------------------------------
+# LVTN
+#----------------------------------------------------------------
+
+ layer LVTN  pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
+        grow 180
+	bridge	380 380
+	grow	185
+	shrink	185
+	close  265000
+	calma 125 44
+
+#----------------------------------------------------------------
+# HVTP
+#----------------------------------------------------------------
+
+ layer HVTP pfethvt,varhvt,*pdiodehvt
+        grow 180
+	bridge	380 380
+	grow	185
+	shrink	185
+	close 265000
+	calma 78 44
+
+#----------------------------------------------------------------
+# SONOS
+#----------------------------------------------------------------
+
+ layer SONOS nsonos
+	grow 100
+	grow-min 410
+	bridge 500 410
+	grow 250
+	shrink 250
+	calma 80 20
+
+#----------------------------------------------------------------
+# SONOS requires COREID around area (areaid.ce).  Also, the
+# coreli layer indicates a cell needing COREID.
+#----------------------------------------------------------------
+
+ layer COREID
+	bloat-all nsonos,coreli CELLBOUND
+	calma 81 2
+
+#----------------------------------------------------------------
+# STDCELL applies to all cells containing scnfet or scpfet.
+#----------------------------------------------------------------
+
+ layer STDCELL scnfet
+	bloat-all scpfet,scnfet CELLBOUND
+	calma 81 4
+
+#----------------------------------------------------------------
+# RPM
+#----------------------------------------------------------------
+
+ layer RPM
+	bloat-all xhrpoly xpc
+	grow 200
+	grow-min 1270
+	grow 420
+	shrink 420
+	calma 86 20
+
+#----------------------------------------------------------------
+# URPM (2kOhms/sq. poly implant)
+#----------------------------------------------------------------
+
+ layer URPM
+	bloat-all uhrpoly xpc
+	grow 200
+	grow-min 1270
+	grow 420
+	shrink 420
+	calma 79 20
+
+#----------------------------------------------------------------
+# LDNTM (Tip implant for SONOS FETs)
+#----------------------------------------------------------------
+
+ layer LDNTM
+	bloat-all nsonos *ndiff
+	grow 185
+ 	grow 	345
+ 	shrink 	345
+	calma 11 44
+
+#----------------------------------------------------------------
+# HVNTM (Tip implant for MV ndiff devices)
+#----------------------------------------------------------------
+
+ templayer hvntm_block *mvpsd
+	grow 185
+
+ layer HVNTM
+	bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+	bloat-all mvvaractor *mvnsd
+	and-not hvntm_block
+        grow 185
+ 	grow 	345
+ 	shrink 	345
+	calma 125 20
+
+#----------------------------------------------------------------
+# POLY
+#----------------------------------------------------------------
+
+ layer POLY 	allpoly
+ 	calma 	66 20
+
+ layer POLYTXT
+	labels  allpoly noport
+	calma	66 16
+
+ layer POLYPIN
+	labels  allpoly port
+	calma	66 5
+
+#----------------------------------------------------------------
+# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
+#----------------------------------------------------------------
+
+ templayer baseTHKOX 	*mvpsd
+	grow-min 470
+	or alldiffmv,mvvar
+	grow	185
+        bloat-all alldiffmv nwell
+	grow-min 600
+	bridge	700 600
+
+ templayer extendTHKOX	baseTHKOX,CELLRING
+ 	grow 	345
+ 	shrink 	345
+	and-not	CELLRING
+
+ layer THKOX	baseTHKOX,extendTHKOX
+ 	calma 	75 20
+
+#----------------------------------------------------------------
+# CONT (LICON)
+#----------------------------------------------------------------
+
+ layer CONT allcont
+ 	squares-grid 0 170 170
+ 	calma	66 44
+
+ # Contact for pres is different than other LICON contacts
+ # See rules LICON 1b, 1c (width/length) and 2b (spacing)
+ templayer xpc_horiz xpc
+	shrink 1007
+	grow 1007
+
+ layer CONT xpc
+	and-not xpc_horiz
+	# Force long edge vertical for contacts narrower than 2um
+	# Minimum space is 350 but 520 satisfies no. of contacts rule
+ 	slots 80 190 520 80 2000 350
+ 	calma	66 44
+
+ layer CONT xpc
+	and xpc_horiz
+	# Force long edge vertical for contacts wider than 2um
+	# Minimum space is 350 but 520 satisfies no. of contacts rule
+ 	slots 80 2000 350 80 190 520
+ 	calma	66 44
+
+#----------------------------------------------------------------
+# NPC (Nitride poly cut)
+# surrounds CONT (LICON) on poly only (i.e., pc)
+#----------------------------------------------------------------
+
+ layer NPC pc
+ 	squares-grid 0 170 170
+	grow 100
+	bridge 270 270
+	grow 130
+	shrink 130
+	calma  95 20
+
+ # NPC is also generated on xhrpoly and uhrpoly resistors
+
+ layer NPC xpc,xhrpoly,uhrpoly
+        # xpc surrounds precision_resistor by 0.095um
+	grow 95
+	grow 130
+	shrink 130
+	calma  95 20
+
+#----------------------------------------------------------------
+# Device markers
+#----------------------------------------------------------------
+
+ layer DIFFRES rdn,mvrdn,rdp,mvrdp
+	calma 65 13
+
+ layer POLYRES mrp1
+	calma 66 13
+
+ # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
+ layer POLYSHORT rmp
+	calma 66 15
+
+ # POLYRES extends to edge of contact cut
+ layer POLYRES xhrpoly,uhrpoly
+	grow 60
+	and xpc
+	or xhrpoly,uhrpoly
+	calma 66 13
+
+ layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
+        # To be done:  Expand to include anode, cathode, and guard ring
+	calma 81 23
+
+#----------------------------------------------------------------
+# LI
+#----------------------------------------------------------------
+ layer LI allli
+	calma 67 20
+
+ layer LITXT
+ 	labels *locali,coreli noport
+	calma 67 16
+
+ layer LIPIN
+ 	labels *locali,coreli port
+	calma 67 5
+
+ layer LIRES rli
+	labels rli
+	calma 67 13
+
+#----------------------------------------------------------------
+# MCON
+#----------------------------------------------------------------
+ layer MCON lic
+ 	squares-grid 0 170 190
+ 	calma 	67 44
+
+#----------------------------------------------------------------
+# MET1
+#----------------------------------------------------------------
+ layer MET1 	allm1
+ 	calma 	68 20
+
+ layer MET1TXT
+	labels	allm1 noport
+	calma 	68 16
+
+ layer MET1PIN
+	labels	allm1 port
+	calma 	68 5
+
+ layer MET1RES rm1
+	labels rm1
+	calma 68 13
+
+#----------------------------------------------------------------
+# VIA1
+#----------------------------------------------------------------
+ layer VIA1 	via1
+ 	squares-grid 55 150 170
+ 	calma 	68 44
+
+#----------------------------------------------------------------
+# MET2
+#----------------------------------------------------------------
+ layer MET2 	allm2
+ 	calma 	69 20
+
+ layer MET2TXT
+	labels	allm2 noport
+	calma	69 16
+
+ layer MET2PIN
+	labels	allm2 port
+	calma	69 5
+
+ layer MET2RES rm2
+	labels rm2
+	calma 69 13
+
+#----------------------------------------------------------------
+# VIA2
+#----------------------------------------------------------------
+ layer VIA2 	via2
+ 	squares-grid 40 200 200
+ 	calma 	69 44
+
+#----------------------------------------------------------------
+# MET3
+#----------------------------------------------------------------
+ layer MET3 	allm3
+ 	calma 	70 20
+
+ layer MET3TXT
+ 	labels 	allm3 noport
+	calma	70 16 
+
+ layer MET3PIN
+	labels	allm3 port
+	calma	70 5
+
+ layer MET3RES rm3
+	labels rm3
+	calma 70 13
+
+#ifdef METAL5
+#----------------------------------------------------------------
+# VIA3
+#----------------------------------------------------------------
+ layer VIA3	via3
+#ifdef MIM
+	or mimcc
+#endif (MIM)
+ 	squares-grid 60 200 200
+ 	calma 	70 44
+
+#----------------------------------------------------------------
+# MET4
+#----------------------------------------------------------------
+ layer MET4 	allm4
+ 	calma 	71 20
+
+ layer MET4TXT
+	labels	allm4 noport
+	calma	71 16
+
+ layer MET4PIN
+	labels	allm4 port
+	calma	71 5
+
+ layer MET4RES rm4
+	labels rm4
+	calma 71 13
+
+#----------------------------------------------------------------
+# VIA4
+#----------------------------------------------------------------
+ layer VIA4	via4
+#ifdef MIM
+	or mim2cc
+#endif (MIM)
+ 	squares-grid 190 800 800
+ 	calma 	71 44
+
+#----------------------------------------------------------------
+# MET5
+#----------------------------------------------------------------
+ layer MET5 	allm5
+ 	calma 	72 20
+
+ layer MET5TXT
+	labels	allm5 noport
+	calma	72 16
+
+ layer MET5PIN
+	labels	allm5 port
+	calma	72 5
+
+ layer MET5RES rm5
+	labels rm5
+	calma 72 13
+
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+#----------------------------------------------------------------
+# RDL
+#----------------------------------------------------------------
+  layer RDL	*metrdl
+	calma   74 20
+
+  layer RDLTXT
+	labels	*metrdl noport
+	calma	74 16
+
+  layer RDLPIN
+	labels  *metrdl port
+	calma	74 5
+
+#endif REDISTRIBUTION
+
+#----------------------------------------------------------------
+# GLASS
+#----------------------------------------------------------------
+ layer GLASS 	glass
+ 	calma 	76 20
+
+#ifdef MIM
+#----------------------------------------------------------------
+# CAPM
+#----------------------------------------------------------------
+ layer CAPM 	*mimcap
+ 	labels 	mimcap
+ 	calma 	89 44
+
+ layer CAPM2 	*mimcap2
+ 	labels 	mimcap2
+ 	calma 	97 44
+#endif (MIM)
+
+#----------------------------------------------------------------
+# Chip top level marker for DRC latchup rules to check 15um
+# distance to taps (otherwise 6um is used)
+#----------------------------------------------------------------
+
+ layer LOWTAPDENSITY
+	bbox top
+	# Clear 200um for pads + 50um for required high tap density
+	# in critical area.
+	shrink 250000
+	calma	81 14
+
+#----------------------------------------------------------------
+# FILLBLOCK
+#----------------------------------------------------------------
+ layer FILLOBSM1 fillblock
+ 	calma 	62 24
+
+ layer FILLOBSM2 fillblock
+ 	calma 	105 52
+
+ layer FILLOBSM3 fillblock
+ 	calma 	107 24
+
+ layer FILLOBSM4 fillblock
+ 	calma 	112 4
+
+ render	DNWELL 	cwell       -0.1    0.1
+ render	NWELL	nwell        0.0    0.2062
+ render DIFF	ndiffusion   0.2062 0.12
+ render TAP	pdiffusion   0.2062 0.12
+ render POLY	polysilicon  0.3262 0.18
+ render CONT	via          0.5062 0.43
+ render LI	metal1       0.9361 0.10
+ render MCON	via          1.0361 0.34
+ render MET1	metal2       1.3761 0.36
+ render VIA1	via          1.7361 0.27
+ render MET2	metal3       2.0061 0.36
+ render VIA2	via          2.3661 0.42
+ render MET3	metal4       2.7861 0.845
+#ifdef METAL5
+ render VIA3	via          3.6311 0.39
+ render MET4	metal5       4.0211 0.845
+ render VIA4	via          4.8661 0.505
+ render MET5	metal6       5.3711 1.26
+ render CAPM	metal8       2.4661 0.2
+ render CAPM2	metal9       3.7311 0.2
+#ifdef REDISTRIBUTION
+ render RDL	metal7      11.8834 4.0
+#endif (!REDISTRIBUTION)
+#endif (!METAL5)
+
+#----------------------------------------------------------------
+style drc
+#----------------------------------------------------------------
+# NOTE:  This style is used for DRC only, not for GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+
+ # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
+ templayer dnwell_shrink dnwell
+ shrink 1030
+
+ templayer nwell_missing dnwell
+ grow 400
+ and-not dnwell_shrink
+ and-not nwell
+
+ # SONOS nFET devices must be in deep nwell
+ templayer dnwell_missing nsonos
+ and-not dnwell
+
+ # Define MiM cap bottom plate for spacing rule
+ templayer mim_bottom
+ bloat-all *mimcap *metal3
+
+ # Define MiM2 cap bottom plate for spacing rule
+ templayer mim2_bottom
+ bloat-all *mimcap2 *metal4
+
+ # Note that metal fill is performed by the foundry and so is not
+ # an option for a cifoutput style.
+
+ # Check latchup rule (15um minimum from tap LICON center to any
+ # non-tap diffusion.  Note that to count as a tap, the diffusion
+ # must be contacted to LI
+
+ templayer ptap_reach psc,mvpsc
+ and-not dnwell
+ # grow total is 15um.  grow in 0.84um increments to ensure that
+ # no nwell ring is crossed
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 635
+ and-not nwell,dnwell
+
+ templayer ptap_missing *ndiff,*mvndiff
+ and-not dnwell
+ and-not ptap_reach
+
+ templayer ntap_reach nsc,mvnsc
+ # grow total is 15um.  grow in 1.27um increments to ensure that
+ # no nwell ring is crossed.  There is no difference between
+ # ntaps in and out of deep nwell.
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 945
+ and nwell
+ 
+ templayer ntap_missing *pdiff,*mvpdiff
+ and-not dnwell
+ and-not ntap_reach
+
+ templayer dptap_reach psc,mvpsc
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 635
+ and-not nwell
+ and dnwell
+
+ templayer dptap_missing *ndiff,*mvndiff
+ and dnwell
+ and-not dptap_reach
+
+ templayer m1_small_hole *m1
+ close   140000
+
+ templayer m1_hole_empty m1_small_hole
+ and-not *m1
+
+ templayer m2_small_hole *m2
+ close   140000
+
+ templayer m2_hole_empty m2_small_hole
+ and-not *m2
+
+#ifdef EXPERIMENTAL
+#----------------------------------------------------------------
+style paint
+#----------------------------------------------------------------
+# NOTE:  This style is used for database manipulations only via
+# the "cif paint" command.
+#----------------------------------------------------------------
+
+ scalefactor 10  nanometers
+
+ templayer m1grow *m1
+    grow 290
+
+ # layer listrap:  Use the following set of commands to strap local
+ # interconnect wires with metal1 (inside the cursor box) to satisfy
+ # the maximum aspect ratio rule for local interconnect:
+ #
+ #    tech unlock *
+ #    cif ostyle paint
+ #    cif paint m1strap comment
+ #    cif paint m1strap m1
+ #    cif paint listrap licon
+ #    erase comment
+
+ templayer m1strap *li
+    and-not m1grow
+    grow 30
+
+ templayer listrap comment
+    slots 30 170 170 60
+
+#endif (EXPERIMENTAL)
+
+end
+
+#-----------------------------------------------------------------------
+cifinput
+#-----------------------------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+#-----------------------------------------------------------------------
+
+style  vendorimport
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+#ifndef MIM
+ ignore CAPM
+ ignore CAPM2
+#endif (!MIM)
+#ifndef METAL5
+ ignore MET4,VIA3
+ ignore MET5,VIA4
+#endif
+ ignore NPC
+ ignore SEALID
+ ignore NPNID
+ ignore PNPID
+ ignore CAPID
+ ignore LDNTM
+ ignore HVNTM
+ ignore POLYMOD
+ ignore LOWTAPDENSITY
+
+ layer nwell NWELL,WELLTXT,WELLPIN
+ labels NWELL
+ labels WELLTXT text
+ labels WELLPIN port
+
+ layer pwell SUBTXT,SUBPIN
+ labels SUBTXT text
+ labels SUBPIN port
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ layer rpw PWRES
+ and DNWELL
+ labels PWRES
+
+ templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and-not THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+ labels TAPPIN port
+
+ layer ndiff ndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvndiff mvndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+ labels DIFF
+
+ layer ndiodelvt DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NPLUS
+ and-not THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer ndiffres DIFFRES
+ and NPLUS
+ and-not THKOX
+ labels DIFF
+
+ templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and-not DIODE
+ and-not THKOX
+ and PPLUS
+ copyup pdifcheck
+ labels DIFF 
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiff pdiffarea
+
+ layer mvndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ labels DIFF
+
+ layer nndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NPLUS
+ and THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer mvndiffres DIFFRES
+ and NPLUS
+ and THKOX
+ labels DIFF
+
+ templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and THKOX
+ and-not DIODE
+ and-not DIFFRES
+ and PPLUS
+ copyup mvpdifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiff mvpdiffarea
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodelvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodehvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PPLUS
+ and-not THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff, regardless of the presence of a well.
+
+ templayer pfetarea DIFF
+ and-not NPLUS
+ and-not THKOX
+ and POLY
+
+ layer pfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and-not STDCELL
+ labels DIFF
+
+ layer scpfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and STDCELL
+ labels DIFF
+
+ layer pfetlvt pfetarea
+ and LVTN
+ labels DIFF
+
+ layer pfethvt pfetarea
+ and HVTP
+ labels DIFF
+
+ # Always force nwell under pfet (nwell encloses pdiff by 0.18)
+ layer nwell pfetarea
+ grow 180
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PPLUS
+ and THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF
+ and-not NPLUS
+ and THKOX
+ and POLY
+
+ layer mvpfet mvpfetarea
+ labels DIFF
+
+ layer pdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not DIODE
+ and-not DIFFRES
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and-not THKOX
+ labels DIFF
+
+ layer nfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and-not STDCELL
+ labels DIFF
+
+ layer scnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and STDCELL
+ labels DIFF
+
+ layer nfetlvt DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and-not SONOS
+ labels DIFF
+
+ layer nsonos DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and SONOS
+ labels DIFF
+
+ templayer nsdarea DIFF
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ copyup nsubcheck
+
+ layer nsd nsdarea
+ labels DIFF
+
+ layer nsd TAP,TAPPIN
+ and NPLUS
+ labels TAP
+ labels TAPPIN port
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels DIFF
+
+ layer psd TAP,TAPPIN
+ and PPLUS
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvpfetexpand
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and THKOX
+ and-not mvrdpioedge
+ labels DIFF
+
+ layer mvnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not LVTN
+ and THKOX
+ labels DIFF
+
+ layer mvnnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and LVTN
+ and THKOX
+ labels DIFF
+
+ templayer mvnsdarea DIFF
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and THKOX
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels DIFF
+
+ layer mvnsd TAP,TAPPIN
+ and NPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ layer mvpsd TAP,TAPPIN
+ and PPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and nsdexpand
+
+ layer mvpsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvnsdexpand
+
+ templayer hresarea POLY
+ and RPM
+ grow 3000
+
+ templayer uresarea POLY
+ and URPM
+ grow 3000
+
+ templayer diffresarea DIFFRES
+ and-not THKOX
+ grow 3000
+
+ templayer mvdiffresarea DIFFRES
+ and THKOX
+ grow 3000
+
+ templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
+
+ layer pfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and-not STDCELL
+
+ layer scpfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and STDCELL
+
+ templayer xpolyterm RPM,URPM
+ and POLY
+ and-not POLYRES
+ # add back the 0.06um contact surround in the direction of the resistor
+ grow 60
+ and POLY
+
+ layer xpc xpolyterm
+
+ templayer polyarea POLY
+ and-not POLYRES
+ and-not POLYSHORT
+ and-not DIFF
+ and-not RPM
+ and-not URPM
+ copyup polycheck
+
+ layer poly polyarea,POLYTXT,POLYPIN
+ labels POLY
+ labels POLYTXT text
+ labels POLYPIN port
+
+ # Copy (non-resistor) poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer mrp1 POLY
+ and POLYRES
+ and-not RPM
+ and-not URPM
+ labels POLY
+
+ layer rmp POLY
+ and POLYSHORT
+ labels POLY
+
+ layer xhrpoly POLY
+ and POLYRES
+ and RPM
+ and-not URPM
+ and PPLUS
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ layer uhrpoly POLY
+ and POLYRES
+ and URPM
+ and-not RPM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ templayer ndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and-not THKOX
+
+ layer ndc ndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndcbase
+ labels CONT
+
+ templayer nscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer nsc nscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nscbase
+ labels CONT
+
+ templayer pdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer pdc pdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcbase
+ labels CONT
+
+ templayer pdcnowell CONT
+ and DIFF
+ and PPLUS
+ and pfetexpand
+ and LI
+ and-not THKOX
+
+ layer pdc pdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcnowell
+ labels CONT
+
+ templayer pscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not pfetexpand
+ and LI
+ and-not THKOX
+
+ layer psc pscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pscbase
+ labels CONT
+
+ templayer pcbase CONT
+ and POLY
+ and-not DIFF
+ and-not RPM,URPM
+ and LI
+
+ layer pc pcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pcbase
+ labels CONT
+
+ templayer ndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+
+ layer ndic ndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndicbase
+ labels CONT
+
+ templayer ndilvtcbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+
+ layer ndilvtc ndilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndilvtcbase
+ labels CONT
+
+ templayer pdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+
+ layer pdic pdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdicbase
+ labels CONT
+
+ templayer pdilvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+
+ layer pdilvtc pdilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdilvtcbase
+ labels CONT
+
+ templayer pdihvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+
+ layer pdihvtc pdihvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdihvtcbase
+ labels CONT
+
+ templayer mvndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and THKOX
+
+ layer mvndc mvndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndcbase
+ labels CONT
+
+ templayer mvnscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvnsc mvnscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnscbase
+ labels CONT
+
+ templayer mvpdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvpdc mvpdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcbase
+ labels CONT
+
+ templayer mvpdcnowell CONT
+ and DIFF
+ and PPLUS
+ and mvpfetexpand
+ and MET1
+ and THKOX
+
+ layer mvpdc mvpdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcnowell
+ labels CONT
+
+ templayer mvpscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not mvpfetexpand
+ and LI
+ and THKOX
+
+ layer mvpsc mvpscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpscbase
+ labels CONT
+
+ templayer mvndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ and THKOX
+
+ layer mvndic mvndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndicbase
+ labels CONT
+
+ templayer nndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ and THKOX
+
+ layer nndic nndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nndicbase
+ labels CONT
+
+ templayer mvpdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+
+ layer mvpdic mvpdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdicbase
+ labels CONT
+
+ layer locali LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and-not COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer coreli LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer rli LI
+ and LIRES,LISHORT
+ labels LIRES,LISHORT
+
+ layer lic MCON
+ grow 95
+ shrink 95
+ shrink 85
+ grow 85
+ or MCON
+ labels MCON
+
+ layer m1 MET1,MET1TXT,MET1PIN
+ and-not MET1RES,MET1SHORT
+ labels MET1
+ labels MET1TXT text
+ labels MET1PIN port
+
+ layer rm1 MET1
+ and MET1RES,MET1SHORT
+ labels MET1RES,MET1SHORT
+
+#ifdef MIM
+ layer mimcap MET3
+ and CAPM
+ labels CAPM
+
+ layer mimcc VIA3
+ and CAPM
+ grow 60
+ grow 40
+ shrink 40
+ labels CAPM
+
+ layer mimcap2 MET4
+ and CAPM2
+ labels CAPM2
+
+ layer mim2cc VIA4
+ and CAPM2
+ grow 190
+ grow 210
+ shrink 210
+ labels CAPM2
+
+#endif (MIM)
+
+ templayer m2cbase VIA1
+ grow 55
+
+ layer m2c m2cbase
+ grow 30
+ shrink 30
+ shrink 130
+ grow 130
+ or m2cbase
+
+ layer m2 MET2,MET2TXT,MET2PIN
+ and-not MET2RES,MET2SHORT
+ labels MET2
+ labels MET2TXT text
+ labels MET2PIN port
+
+ layer rm2 MET2
+ and MET2RES,MET2SHORT
+ labels MET2RES,MET2SHORT
+
+ templayer m3cbase VIA2
+ grow 40
+
+ layer m3c m3cbase
+ grow 60
+ shrink 60
+ shrink 140 
+ grow 140
+ or m3cbase
+
+ layer m3 MET3,MET3TXT,MET3PIN
+ and-not MET3RES,MET3SHORT
+#ifdef MIM
+ and-not CAPM
+#endif (MIM)
+ labels MET3
+ labels MET3TXT text
+ labels MET3PIN port
+
+ layer rm3 MET3
+ and MET3RES,MET3SHORT
+ labels MET3RES,MET3SHORT
+
+#ifdef (METAL5)
+
+ templayer via3base VIA3
+#ifdef MIM
+ and-not CAPM
+#endif (MIM)
+ grow 60
+
+ layer via3 via3base
+ grow 40
+ shrink 40
+ shrink 160
+ grow 160
+ or via3base
+
+ layer m4 MET4,MET4TXT,MET4PIN
+ and-not MET4RES,MET4SHORT
+#ifdef MIM
+ and-not CAPM2
+#endif (MIM)
+ labels MET4
+ labels MET4TXT text
+ labels MET4PIN port
+
+ layer rm4 MET4
+ and MET4RES,MET4SHORT
+ labels MET4RES,MET4SHORT
+
+ layer m5 MET5,MET5TXT,MET5PIN
+ and-not MET5RES,MET5SHORT
+ labels MET5
+ labels MET5TXT text
+ labels MET5PIN port
+
+ layer rm5 MET5
+ and MET5RES,MET5SHORT
+ labels MET5RES,MET5SHORT
+
+ templayer via4base VIA4
+#ifdef MIM
+ and-not CAPM2
+#endif (MIM)
+ grow 190
+
+ layer via4 via4base
+ grow 210
+ shrink 210
+ shrink 590
+ grow 590
+ or via4base
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+ layer metrdl RDL,RDLTXT,RDLPIN
+ labels RDL
+ labels RDLTXT text
+ labels RDLPIN port
+#endif
+
+ # Find diffusion not covered in
+ # NPLUS or PPLUS and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and POLY
+ copyup DIFF,POLY
+
+ templayer gendiff DIFF,TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ copyup DIFF
+
+ # Handle contacts found by copyup
+
+ templayer ndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and-not THKOX
+
+ layer ndic ndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndiccopy
+ labels CONT
+
+ templayer mvndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and THKOX
+
+ layer mvndic mvndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndiccopy
+ labels CONT
+
+ templayer pdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and-not THKOX
+
+ layer pdic pdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdiccopy
+ labels CONT
+
+ templayer mvpdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and THKOX
+
+ layer mvpdic mvpdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdiccopy
+ labels CONT
+
+ templayer ndccopy CONT
+ and ndifcheck
+
+ layer ndc ndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndccopy
+ labels CONT
+
+ templayer mvndccopy CONT
+ and mvndifcheck
+
+ layer mvndc mvndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndccopy
+ labels CONT
+
+ templayer pdccopy CONT
+ and pdifcheck
+
+ layer pdc pdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdccopy
+ labels CONT
+
+ templayer mvpdccopy CONT
+ and mvpdifcheck
+
+ layer mvpdc mvpdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdccopy
+ labels CONT
+
+ templayer pccopy CONT
+ and polycheck
+
+ layer pc pccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pccopy
+ labels CONT
+
+ templayer nsccopy CONT
+ and nsubcheck
+
+ layer nsc nsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nsccopy
+ labels CONT
+
+ templayer mvnsccopy CONT
+ and mvnsubcheck
+
+ layer mvnsc mvnsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnsccopy
+ labels CONT
+
+ templayer psccopy CONT
+ and psubcheck
+
+ layer psc psccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or psccopy
+ labels CONT
+
+ templayer mvpsccopy CONT
+ and mvpsubcheck
+
+ layer mvpsc mvpsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpsccopy
+ labels CONT
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+ 
+ templayer gencont CONT
+ and LI
+ and-not DIFF,TAP
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT,LI
+
+ templayer barecont CONT
+ and-not LI
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT
+
+ layer glass GLASS,PADTXT,PADPIN
+ labels GLASS
+ labels PADTXT text
+ labels PADPIN port
+
+ templayer boundary BOUND,STDCELL,PADCELL
+ boundary
+
+ layer comment LVSTEXT
+ labels LVSTEXT text
+
+ layer comment TTEXT
+ labels TTEXT text
+
+ layer fillblock  FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+ labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+
+# MOS Varactor
+
+ layer var POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and-not HVTP
+ grow 25
+ labels POLY
+
+ layer varhvt POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and HVTP
+ grow 25
+ labels POLY
+
+ layer mvvar POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and THKOX
+ grow 25
+ labels POLY
+
+ calma NWELL 64 20
+ calma DIFF 65 20
+ calma DNWELL 64 18
+ calma PWRES 64 13
+ calma TAP  65 44
+ # LVTN
+ calma LVTN 125 44
+ # HVTP
+ calma HVTP 78 44
+ # SONOS (TUNM)
+ calma SONOS 80 20
+ # NPLUS = NSDM
+ calma NPLUS 93 44
+ # PPLUS = PSDM
+ calma PPLUS 94 20
+ # HVI
+ calma THKOX 75 20
+ # NPC
+ calma NPC 95 20
+ # P+ POLY MASK
+ calma RPM 86 20
+ calma URPM 79 20
+ calma LDNTM 11 44
+ calma HVNTM 125 20
+ # Poly resistor ID mark
+ calma POLYRES 66 13
+ # Diffusion resistor ID mark
+ calma DIFFRES 65 13
+ calma POLY 66 20
+ calma POLYMOD 66 83
+ # Diode ID mark
+ calma DIODE 81 23
+ # Bipolar NPN mark
+ calma NPNID 82 20
+ # Bipolar PNP mark
+ calma PNPID 82 20
+ # Capacitor ID
+ calma CAPID 82 64
+ # Core area ID mark
+ calma COREID 81 2
+ # Standard cell ID mark
+ calma STDCELL 81 4
+ # Padframe cell ID mark
+ calma PADCELL 81 3
+ # Seal ring ID mark
+ calma SEALID 81 1
+ # Low tap density ID mark
+ calma LOWTAPDENSITY 81 14
+ 
+ # LICON
+ calma CONT 66 44
+ calma LI   67 20
+ calma MCON 67 44
+
+ calma MET1 68 20
+ calma VIA1 68 44
+ calma MET2 69 20
+ calma VIA2 69 44
+ calma MET3 70 20
+#ifdef METAL5
+ calma VIA3 70 44
+ calma MET4 71 20
+ calma VIA4 71 44
+ calma MET5 72 20
+#endif
+#ifdef REDISTRIBUTION
+ calma RDL 74 20
+#endif
+ calma GLASS 76 20
+
+ calma SUBPIN  64 59
+ calma PADPIN  76 5
+ calma DIFFPIN 65 6
+ calma TAPPIN  65 5
+ calma WELLPIN  64 5
+ calma LIPIN 67 5
+ calma POLYPIN 66 5
+ calma MET1PIN 68 5
+ calma MET2PIN 69 5
+ calma MET3PIN 70 5
+#ifdef METAL5
+ calma MET4PIN 71 5
+ calma MET5PIN 72 5
+#endif
+#ifdef REDISTRIBUTION
+ calma RDLPIN 74 5
+#endif
+
+ calma LIRES 67 13
+ calma MET1RES 68 13
+ calma MET2RES 69 13
+ calma MET3RES 70 13
+#ifdef METAL5
+ calma MET4RES 71 13
+ calma MET5RES 72 13
+#endif
+
+ calma POLYSHORT 66 15
+ calma LISHORT 67 15
+ calma MET1SHORT 68 15
+ calma MET2SHORT 69 15
+ calma MET3SHORT 70 15
+#ifdef METAL5
+ calma MET4SHORT 71 15
+ calma MET5SHORT 72 15
+#endif
+
+ calma SUBTXT 122 16
+ calma PADTXT 76 16
+ calma DIFFTXT 65 16
+ calma POLYTXT 66 16
+ calma WELLTXT 64 16
+ calma LITXT 67 16
+ calma MET1TXT 68 16
+ calma MET2TXT 69 16
+ calma MET3TXT 70 16
+#ifdef METAL5
+ calma MET4TXT 71 16
+ calma MET5TXT 72 16
+#endif
+#ifdef REDISTRIBUTION
+ calma RDLPIN 74 16
+#endif
+
+ calma BOUND 235 4
+
+ calma LVSTEXT 83 44
+
+#ifdef (MIM)
+ calma CAPM 89 44
+ calma CAPM2 97 44
+#endif (MIM)
+
+ calma FILLOBSM1  62  24
+ calma FILLOBSM2  105 52
+ calma FILLOBSM3  107 24
+ calma FILLOBSM4  112 4
+
+end
+
+#-----------------------------------------------------
+# Digital flow maze router cost parameters
+#-----------------------------------------------------
+
+mzrouter
+end
+
+#-----------------------------------------------------
+# Vendor DRC rules
+#-----------------------------------------------------
+
+drc
+
+ style drc variants (fast),(full),(routing)
+
+ scalefactor 10 
+
+ cifstyle drc
+
+ variants (fast),(full)
+
+#-----------------------------
+# DNWELL
+#-----------------------------
+
+ width dnwell 3000 "Deep N-well width < %d (Dnwell 2)"
+ spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (Dnwell 3)"
+ spacing dnwell allnwell 4500 surround_ok \
+	"Deep N-well spacing to N-well < %d (Nwell 7)"
+ cifmaxwidth nwell_missing 0 bend_illegal \
+	"N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (Nwell 5a, 7)"
+ cifmaxwidth dnwell_missing 0 bend_illegal \
+	"SONOS nFET must be in Deep N-well (Tunm 6a)"
+
+#-----------------------------
+# NWELL
+#-----------------------------
+
+ width allnwell 840 "N-well width < %d (Nwell 1)"
+ spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (Nwell 2a)"
+
+#-----------------------------
+# DIFF
+#-----------------------------
+
+ width *ndiff,nfet,scnfet,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,*psd,*pdiode,pdiffres \
+	150 "Diffusion width < %d (Diff/tap 1)"
+ width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \
+	"MV Diffusion width < %d (Diff/tap 14)"
+ width *mvnsd,*mvpsd 150 "MV Tap width < %d (Diff/tap 1)"
+ extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (Diff/tap 16)"
+ extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (Diff/tap 16)"
+ extend *psd *ndiff 290 "Butting tap length < %d (Diff/tap 4)"
+ extend *nsd *pdiff 290 "Butting tap length < %d (Diff/tap 4)"
+ width mvpdiffres 150 "MV P-Diffusion resistor width < %d (Diff/tap 14a)"
+ spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
+	"Diffusion spacing < %d (Diff/tap 3)"
+ spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
+	"MV Diffusion spacing < %d (Diff/tap 15a)"
+ spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
+	"MV Diffusion to MV tap spacing < %d (Diff/tap 3)"
+ spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
+	touching_ok "MV P-Diffusion to MV N-tap spacing < %d (Diff/tap 15b)"
+ spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
+	"MV Diffusion in N-well to P-tap spacing < %d (Diff/tap 20 + Diff/tap 17,19)"
+ spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (Diff/tap 9)"
+ spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (Diff/tap 9)"
+ spacing *psd allnwell 130 touching_illegal \
+	"P-tap spacing to N-well < %d (Diff/tap 11)"
+ spacing *mvpsd allnwell 130 touching_illegal \
+	"P-tap spacing to N-well < %d (Diff/tap 11)"
+ surround *nsd allnwell 180 absence_illegal \
+	"N-well overlap of N-tap < %d (Diff/tap 10)"
+ surround *mvnsd allnwell 330 absence_illegal \
+	"N-well overlap of MV N-tap < %d (Diff/tap 19)"
+ surround *pdiff,*pdiode,pfet,scpfet allnwell 180 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (Diff/tap 8)"
+ surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (Diff/tap 17)"
+ surround mvvar allnwell 560 absence_illegal \
+	"N-well overlap of MV varactor < %d (LVTN 10 + LVTN 4b)"
+ spacing *mvndiode *mvndiode 1070 touching_ok \
+	"MV N-diode spacing < %d (HVNTM.2 + 2 * HVNTM.3)"
+
+ # Butting junction rules
+ edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
+	"N-Diffusion to P-tap spacing < %d across butted junction"
+ edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
+	"N-Diffusion to P-tap spacing < %d across butted junction"
+ edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
+	"P-Diffusion to N-tap spacing < %d across butted junction"
+ edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
+	"P-Diffusion to N-tap spacing < %d across butted junction"
+
+ edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
+	"MV N-Diffusion to MV P-tap spacing < %d across butted junction"
+ edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
+	"MV N-Diffusion to MV P-tap spacing < %d across butted junction"
+ edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
+	"MV P-Diffusion to MV N-tap spacing < %d across butted junction"
+ edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
+	"MV P-Diffusion to MV N-tap spacing < %d across butted junction"
+
+ variants (full)
+
+ # Latchup rules
+ cifmaxwidth ptap_missing 0 bend_illegal \
+	"N-diff distance to P-tap must be < 15.0um (LU 2)"
+ cifmaxwidth dptap_missing 0 bend_illegal \
+	"N-diff distance to P-tap in deep Nwell must be < 15.0um (LU 2.1)"
+ cifmaxwidth ntap_missing 0 bend_illegal \
+	"P-diff distance to N-tap must be < 15.0um (LU 3)"
+
+ variants *
+
+#-----------------------------
+# POLY
+#-----------------------------
+
+ width allpoly 150 "Poly width < %d (Poly 1a)"
+ spacing allpoly allpoly 210 touching_ok "Poly spacing < %d (Poly 2)"
+ spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \
+	"Poly spacing to Diffusion < %d (Poly 4a)"
+ spacing npres *nsd 480 touching_illegal \
+	"Poly resistor spacing to N-tap < %d (Poly 9)"
+ overhang *ndiff,rndiff nfet,scnfet 250 "N-Diffusion overhang of nmos < %d (Poly 7)"
+ overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
+	"N-Diffusion overhang of nmos < %d (Poly 7)"
+ overhang *pdiff,rpdiff pfet,scpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
+ overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
+ overhang *poly allfets 130 "Poly overhang of transistor < %d (Poly 8)"
+ rect_only allfets "No bends in transistors (Poly 11)"
+ rect_only xhrpoly,uhrpoly "No bends in poly resistors (Poly 11)"
+ extend  xpc/a xhrpoly,uhrpoly 2160 \
+ 	"Poly contact extends poly resistor by < %d (LIcon 1c + LI 5)"
+ spacing xhrpoly,uhrpoly xhrpoly,uhrpoly 1240 touching_illegal \
+	"Distance between precision resistors < %d (RPM 2 + 2 * RPM 3)"
+
+#--------------------------------------------------------------------
+# NPC (Nitride Poly Cut)
+#--------------------------------------------------------------------
+
+# Layer NPC is defined automatically around poly contacts (grow 0.1um)
+
+#--------------------------------------------------------------------
+# CONT (LICON, contact between poly/diff and LI)
+#--------------------------------------------------------------------
+
+ width ndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
+ width nsc/li 170 "N-tap contact width     < %d (LIcon 1)"
+ width pdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
+ width psc/li 170 "P-tap contact width     < %d (LIcon 1)"
+ width ndic/li 170 "N-diode contact width < %d (LIcon 1)"
+ width pdic/li 170 "P-diode contact width < %d (LIcon 1)"
+ width pc/li  170 "Poly contact width        < %d (LIcon 1)"
+
+ width xpc/li  350 "Poly resistor contact width < %d (LIcon 1b + 2 * LI 5)"
+
+ width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
+ width mvnsc/li 170 "N-tap contact width     < %d (LIcon 1)"
+ width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
+ width mvpsc/li 170 "P-tap contact width     < %d (LIcon 1)"
+ width mvndic/li 170 "N-diode contact width < %d (LIcon 1)"
+ width mvpdic/li 170 "P-diode contact width < %d (LIcon 1)"
+
+ spacing allpdiffcont allndiffcont 170 touching_illegal \
+	"Diffusion contact spacing < %d (LIcon 2)"
+ spacing allndiffcont allndiffcont 170 touching_ok \
+	"Diffusion contact spacing < %d (LIcon 2)"
+ spacing allpdiffcont allpdiffcont 170 touching_ok \
+	"Diffusion contact spacing < %d (LIcon 2)"
+ spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (LIcon 2)"
+
+ spacing pc alldiff 190 touching_illegal \
+	"Poly contact spacing to diffusion < %d (LIcon 14)"
+ spacing pc allpfets 235 touching_illegal \
+	"Poly contact spacing to pFET < %d (LIcon 9 + PSDM 5a)"
+
+ spacing ndc,pdc nfet,pfet 55 touching_illegal \
+	"Diffusion contact to gate < %d (LIcon 11)"
+ spacing ndc,pdc scnfet,scpfet 50 touching_illegal \
+	"Diffusion contact to standard cell gate < %d (LIcon 11)"
+ spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
+	"Diffusion contact to gate < %d (LIcon 11)"
+ spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d ()"
+ spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d ()"
+ spacing nsc varactor,varhvt 250 touching_illegal \
+	"Diffusion contact to varactor gate < %d (LIcon 10)"
+ spacing mvnsc mvvar 250 touching_illegal \
+	"Diffusion contact to varactor gate < %d (LIcon 10)"
+
+ surround ndc/a *ndiff,nfet,scnfet,nfetlvt 40 absence_illegal \
+	"N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
+ surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 40 absence_illegal \
+	"P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
+ surround ndic/a *ndi 40 absence_illegal \
+	"N-diode overlap of N-diode contact < %d (LIcon 5a)"
+ surround pdic/a *pdi 40 absence_illegal \
+	"P-diode overlap of N-diode contact < %d (LIcon 5a)"
+
+ surround ndc/a *ndiff,nfet,scnfet,nfetlvt 60 directional \
+	"N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
+ surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 60 directional \
+	"P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
+ surround ndic/a *ndi 60 directional \
+	"N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+ surround pdic/a *pdi 60 directional \
+	"P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+
+ surround nsc/a *nsd 120 directional \
+	"N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
+ surround psc/a *psd 120 directional \
+	"P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
+
+ surround mvndc/a *mvndiff,mvnfet 40 absence_illegal \
+	"N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
+ surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal \
+	"P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
+ surround mvndic/a *mvndi 40 absence_illegal \
+	"N-diode overlap of N-diode contact < %d (LIcon 5a)"
+ surround mvpdic/a *mvpdi 40 absence_illegal \
+	"P-diode overlap of N-diode contact < %d (LIcon 5a)"
+
+ surround mvndc/a *mvndiff,mvnfet 60 directional \
+	"N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
+ surround mvpdc/a *mvpdiff,mvpfet 60 directional \
+	"P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
+ surround mvndic/a *mvndi 60 directional \
+	"N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+ surround mvpdic/a *mvpdi 60 directional \
+	"P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+
+ surround mvnsc/a *mvnsd 120 directional \
+	"N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
+ surround mvpsc/a *mvpsd 120 directional \
+	"P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
+
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
+	"Poly overlap of poly contact < %d (LIcon 8)"
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
+	"Poly overlap of poly contact < %d in one direction (LIcon 8a)"
+
+ exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a
+ exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a
+
+#-------------------------------------------------------------
+# LI - Local interconnect layer
+#-------------------------------------------------------------
+
+ width *li,rli 170 "Local interconnect width < %d (LI 1)"
+ width coreli 140 "Core local interconnect width < %d (LI c1)"
+ spacing allli allli,*obsli 170 touching_ok  "Local interconnect spacing < %d (LI 3)"
+ spacing coreli allli,*obsli 140 touching_ok  "Core local interconnect spacing < %d (LI c2)"
+
+ surround pc/li *li 80 directional \
+	"Local interconnect overlap of poly contact < %d in one direction (LI 5)"
+
+ surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
+	*li,rli 80 directional \
+	"Local interconnect overlap of diffusion contact < %d in one direction (LI 5)"
+
+ area allli,*obsli 56100 170 "Local interconnect minimum area < %a (LI 6)"
+
+#-------------------------------------------------------------
+# MCON - Contact between local interconnect and metal1
+#-------------------------------------------------------------
+
+ width lic/m1 170 "Mcon width < %d (Mcon 1)"
+ spacing lic/m1 lic/m1,obslic/m1 170 touching_ok "Mcon spacing < %d (Mcon 2)"
+
+ exact_overlap lic/m1
+
+#-------------------------------------------------------------
+# METAL1 -
+#-------------------------------------------------------------
+
+ width *m1,rm1 140 "Metal1 width < %d (Met1 1)"
+ spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (Met1 2)"
+ area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (Met1 6)"
+
+ surround lic/m1 *met1 30 absence_illegal \
+	"Metal1 overlap of local interconnect contact < %d (Met1 4)"
+ surround lic/m1 *met1 60 directional \
+	"Metal1 overlap of local interconnect contact < %d in one direction (Met1 5)"
+
+variants (fast),(full)
+ widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
+	"Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
+ widespacing *obsm1 3000 allm1 280 touching_ok \
+	"Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
+
+variants (full)
+ cifmaxwidth m1_hole_empty 0 bend_illegal \
+	"Min area of metal1 holes > 0.14um^2 (Met1 7)"
+variants *
+
+#--------------------------------------------------
+# VIA1
+#--------------------------------------------------
+
+ width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a)"
+ spacing v1 v1 60 touching_ok "Via1 spacing < %d (Via 2 - 2 * Via 4a)"
+ surround v1/m1 *m1 30 directional \
+	"Metal1 overlap of Via1 < %d in one direction (Via 5a - Via 4a)"
+ surround v1/m2 *m2 30 directional \
+	"Metal2 overlap of Via1 < %d in one direction (Met2 5 - Met2 4)"
+
+ exact_overlap v1/m2
+
+#--------------------------------------------------
+# METAL2 - 
+#--------------------------------------------------
+
+ width allm2 140 "Metal2 width < %d (Met2 1)"
+ spacing allm2  allm2,obsm2 140 touching_ok       "Metal2 spacing < %d (Met2 2)"
+ area allm2,obsm2 67600 140 "Metal2 minimum area < %a (Met2 6)"
+
+variants (fast),(full)
+ widespacing allm2 3000 allm2,obsm2  280 touching_ok \
+	"Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
+ widespacing obsm2 3000 allm2  280 touching_ok \
+	"Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
+
+variants (full)
+ cifmaxwidth m2_hole_empty 0 bend_illegal \
+	"Min area of metal2 holes > 0.14um^2 (Met2 7)"
+variants *
+
+#--------------------------------------------------
+# VIA2
+#--------------------------------------------------
+
+ width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4)"
+
+ spacing v2 v2 120 touching_ok "Via2 spacing < 0.24um (Via2 2 - 2 * Via2 4)"
+
+ surround v2/m2 *m2 45 directional \
+	"Metal2 overlap of Via2 < %d in one direction (Via2 4a - Via2 4)"
+ surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of Via2 < %d (Met3 4)"
+
+ exact_overlap v2/m2
+
+#--------------------------------------------------
+# METAL3 - 
+#--------------------------------------------------
+
+ width allm3 300 "Metal3 width < %d (Met3 1)"
+ spacing allm3 allm3,obsm3  300 touching_ok "Metal3 spacing < %d (Met3 2)"
+ area allm3,obsm3 240000 300 "Metal3 minimum area < %a (Met3 6)"
+
+variants (fast),(full)
+ widespacing allm3 3000 allm3,obsm3  400 touching_ok \
+	"Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
+ widespacing obsm3 3000 allm3  400 touching_ok \
+	"Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
+variants *
+
+
+#ifdef METAL5
+#--------------------------------------------------
+# VIA3 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4)"
+ spacing v3 v3 80 touching_ok "Via3 spacing < %d (Via3 2 - 2 * Via3 4)"
+ surround v3/m3 *m3 30 directional \
+	"Metal3 overlap of Via3 in one direction < %d (Via3 5 - Via3 4)"
+ surround v3/m4 *m4 5 directional \
+	"Metal4 overlap of Via3 in one direction < %d (Met4 3 - Via3 4)"
+
+ exact_overlap v3/m3
+
+#-----------------------------
+# METAL4 - METAL4 Module
+#-----------------------------
+
+variants *
+
+ width allm4 300 "Metal4 width < %d (Met4 1)"
+ spacing allm4  allm4,obsm4 300 touching_ok      "Metal4 spacing < %d (Met4 2)"
+ area allm4,obsm4 240000 300 "Metal4 minimum area < %a (Met4 4a)"
+
+variants (fast),(full)
+ widespacing allm4 3000 allm4,obsm4  400 touching_ok \
+	"Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
+ widespacing obsm4 3000 allm4  400 touching_ok \
+	"Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
+variants *
+
+#--------------------------------------------------
+# VIA4 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4)"
+ spacing v4 v4 420 touching_ok "Via4 spacing < %d (Via4 2 - 2 * Via4 4)"
+ surround v4/m5 *m5 120 absence_illegal \
+	"Metal5 overlap of Via4 < %d (Met5 3 - Via4 4)"
+
+ exact_overlap v4/m4
+
+#-----------------------------
+# METAL5 - METAL5 Module
+#-----------------------------
+
+ width allm5 1600 "Metal5 width < %d (Met5 1)"
+ spacing allm5  allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (Met5 2)"
+ area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (Met5 4)"
+
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+
+variants (full)
+
+ width metrdl 10000 "RDL width < %d (Rdl 1)"
+ spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (Rdl 2)"
+ surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (Rdl 3)"
+ spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (Rdl 6)"
+
+variants *
+
+#endif (REDISTRIBUTION)
+
+#--------------------------------------------------
+# NMOS, PMOS
+#--------------------------------------------------
+
+ extend allfets *poly 420 "Transistor width < %d (Diff/tap 2)"
+ # Except:  Note that standard cells allow transistor width minimum 0.36um
+ width pfetlvt 350 "LVT PMOS gate length < %d (Poly 1b)"
+
+ spacing *nsd,*mvnsd allpolynonfet 55 touching_illegal \
+	"N-tap spacing to field poly < %d (Poly 5)"
+ spacing *psd,*mvpsd allpolynonfet 55 touching_illegal \
+	"P-tap spacing to field poly < %d (Poly 5)"
+
+ # Full edge rule required to describe FET to butted tap distance
+ edge4way *psd *ndiff 300 *ndiff *psd 300 \
+	"Butting P-tap spacing to NMOS gate < %d (Poly 6)"
+ edge4way *nsd *pdiff 300 *pdiff *nsd 300 \
+	"Butting N-tap spacing to PMOS gate < %d (Poly 6)"
+ edge4way *mvpsd *mvndiff 300 *mvndiff *mvpsd 300 \
+	"Butting MV P-tap spacing to MV NMOS gate < %d (Poly 6)"
+ edge4way *mvnsd *mvpdiff 300 *mvpdiff *mvnsd 300 \
+	"Butting MV N-tap spacing to MV PMOS gate < %d (Poly 6)"
+
+ # No LV FETs in HV diff
+ spacing pfet,scpfet,pfetlvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
+	"LV P-diffusion to MV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ spacing nfet,scnfet,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
+	"LV N-diffusion to MV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ # No HV FETs in LV diff
+ spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
+	"MV P-diffusion to LV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
+	"MV N-diffusion to LV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ # Minimum length of MV FETs.  Note that this is larger than the minimum
+ # width (0.29um), so an edge rule is required
+
+ edge4way mvndiff mvnfet 500 mvnfet 0 0 \
+	"MV NMOS minimum length < %d (Poly 13)"
+
+ edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
+	"MV Varactor minimum length < %d (Poly 13)"
+
+ edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
+	"MV PMOS minimum length < %d (Poly 13)"
+
+#--------------------------------------------------
+# mrp1 (N+ poly resistor)
+#--------------------------------------------------
+
+  width mrp1 330 "mrp1 resistor width < %d (Poly 3)"
+
+#--------------------------------------------------
+# xhrpoly (P+ poly resistor)
+#--------------------------------------------------
+
+  width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a)"
+  # NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27.
+
+#--------------------------------------------------
+# uhrpoly (P+ poly resistor, 2kOhm/sq)
+#--------------------------------------------------
+
+  width uhrpoly 350 "uhrpoly resistor width < %d"
+  spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+	"xhrpoly/uhrpoly resistor spacing to diffusion < %d (Poly 9)"
+
+#------------------------------------
+# MOS Varactor device rules
+#------------------------------------
+
+ overhang *nsd var,varhvt 250 \
+ "N-Tap overhang of Varactor < %d (Var 4)"
+
+ overhang *mvnsd mvvar 250 \
+ "N-Tap overhang of Varactor < %d (Var 4)"
+
+ width var,varhvt,mvvar 180 "Varactor length < %d (Var 1)"
+ extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (Var 2)"
+
+#ifdef MIM
+#-----------------------------------------------------------
+# MiM CAP (CAPM) - 
+#-----------------------------------------------------------
+
+ width *mimcap 2000 "MiM cap width < %d (Capm 1)"
+ spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (Capm 2a)"
+ spacing *mimcap via2/m3 1270 touching_illegal \
+	"MiM cap spacing to via2 < %d (Capm 5)"
+ surround *mimcc *mimcap 200 absence_illegal \
+	"MiM cap must surround MiM cap contact by %d (Capm 4)"
+ rect_only *mimcap "MiM cap must be rectangular (Capm 7)
+
+ surround *mimcap *metal3/m3 140 absence_illegal \
+	"Metal3 must surround MiM cap by %d (Capm 3)"
+ spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 (Capm 8)"
+ spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (Capm 8)"
+ # (resolve scaling issue!)
+ # cifspacing mim_bottom mim_bottom 1200 touching_ok \
+ #	"MiM cap bottom plate spacing < %d (Capm 2b)"
+
+ # MiM cap contact rules (VIA3)
+
+ width mimcc/m3 320 "MiM cap contact width < %d (Via3 1 + 2 * Via3 4)"
+ spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (Via3 2 - 2 * Via3 4)"
+ surround mimcc/m4 *m4 5 directional \
+	"Metal4 overlap of MiM cap contact in one direction < %d (Met4 3 - Via3 4)"
+ exact_overlap mimcc/m3
+
+ width *mimcap2 2000 "MiM cap width < %d (Cap2m 1)"
+ spacing *mimcap2 *mimcap2 840 touching_ok "MiM cap spacing < %d (Cap2m 2a)"
+ spacing *mimcap2 via3/m4 1270 touching_illegal \
+	"MiM cap spacing to via3 < %d (Cap2m 5)"
+ surround *mim2cc *mimcap2 200 absence_illegal \
+	"MiM cap must surround MiM cap contact by %d (Cap2m 4)"
+ rect_only *mimcap2 "MiM cap must be rectangular (Cap2m 7)
+
+ surround *mimcap2 *metal4/m4 140 absence_illegal \
+	"Metal4 must surround MiM cap by %d (Cap2m 3)"
+ spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 (Cap2m 8)"
+ spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 (Cap2m 8)"
+ # (resolve scaling issue!)
+ # cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
+ #	"MiM2 cap bottom plate spacing < %d (Cap2m 2b)"
+
+ # MiM cap contact rules (VIA4)
+
+ width mim2cc/m4 1180 "MiM2 cap contact width < %d (Via4 1 + 2 * Via4 4)"
+ spacing mim2cc mim2cc 420 touching_ok \
+	"MiM2 cap contact spacing < %d (Via4 2 - 2 * Via4 4)"
+ surround mim2cc/m5 *m5 120 absence_illegal \
+	"Metal5 overlap of MiM2 cap contact < %d (Met5 3 - Via4 4)"
+ exact_overlap mim2cc/m4
+
+#endif (MIM)
+
+#----------------------------
+# End DRC style
+#----------------------------
+
+end
+
+#----------------------------
+# LEF format definitions
+#----------------------------
+
+lef
+
+ routing li	li1 LI1 LI li
+
+ routing m1	met1 MET1 m1
+ routing m2	met2 MET2 m2
+ routing m3	met3 MET3 m3
+#ifdef METAL5
+ routing m4	met4 MET4 m4
+ routing m5	met5 MET5 m5
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ routing mrdl	met6 MET6 m6 MRDL METRDL
+#endif
+
+ cut lic  mcon MCON Mcon
+ cut m2c  via via1 VIA VIA1 cont2 via12
+ cut m3c  via2 VIA2 cont3 via23
+#ifdef METAL5
+ cut via3 via3 VIA3 cont4 via34
+ cut via4 via4 VIA4 cont5 via45
+#endif (METAL5)
+
+ obs obsli   li1
+ obs obsm1   met1
+ obs obsm2   met2
+ obs obsm3   met3
+
+#ifdef METAL5
+ obs obsm4   met4
+ obs obsm5   met5
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ obs obsmrdl met6
+#endif
+
+ obs obslic mcon
+
+end
+
+#-----------------------------------------------------
+# Device and Parasitic extraction
+#-----------------------------------------------------
+
+
+extract
+ style ngspice variants (lvs),(sim),(si)
+ cscale 1
+ # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
+ # dimensions must be in units of microns in the extract file.
+ # Use extract style "ngspice(si)" to override this and produce
+ # a file with SI units for length/area.
+
+ variants (lvs),(sim)
+ lambda  1E6
+ variants (si)
+ lambda 1.0
+ variants *
+
+ units	microns
+ step   7
+ sidehalo 2
+
+ # NOTE:  MiM cap layers have been purposely put out of order,
+ # may want to reconsider.
+
+ planeorder dwell 	0
+ planeorder well 	1
+ planeorder active 	2
+ planeorder locali 	3
+ planeorder metal1 	4
+ planeorder metal2 	5
+ planeorder metal3 	6
+#ifdef METAL5
+ planeorder metal4 	7
+ planeorder metal5 	8
+#ifdef REDISTRIBUTION
+ planeorder metali	9
+ planeorder block      10
+ planeorder comment    11
+ planeorder cap1       12
+ planeorder cap2       13
+#else (!REDISTRIBUTION)
+ planeorder block       9	
+ planeorder comment    10
+ planeorder cap1       11
+ planeorder cap2       12
+#endif (!REDISTRIBUTION)
+#else (!METAL5)
+#ifdef REDISTRIBUTION
+ planeorder metali     7
+ planeorder block      8
+ planeorder comment    9
+ planeorder cap1       10
+ planeorder cap2       11
+#else (!REDISTRIBUTION)
+ planeorder block      7
+ planeorder comment    8
+ planeorder cap1       9
+ planeorder cap2       10
+#endif (!REDISTRIBUTION)
+#endif (!METAL5)
+
+ height	dnwell 	    -0.1    0.1
+ height	nwell,pwell  0.0    0.2062
+ height alldiff	     0.2062 0.12
+ height allpoly	     0.3262 0.18
+ height alldiffcont  0.3262 0.61
+ height pc	     0.5062 0.43
+ height allli	     0.9361 0.10
+ height lic	     1.0361 0.34
+ height allm1	     1.3761 0.36
+ height v1	     1.7361 0.27
+ height allm2	     2.0061 0.36
+ height v2	     2.3661 0.42
+ height allm3	     2.7861 0.845
+#ifdef METAL5
+ height v3	     3.6311 0.39
+ height allm4	     4.0211 0.845
+ height v4	     4.8661 0.505
+ height allm5	     5.3711 1.26
+ height mimcap	     2.4661 0.2
+ height mimcap2	     3.7311 0.2
+ height mimcc	     2.6661 0.12
+ height mim2cc	     3.9311 0.09
+#ifdef REDISTRIBUTION
+ height mrdlc	     6.6311 5.2523
+ height mrdl	    11.8834 4.0
+#endif (!REDISTRIBUTION)
+#endif (!METAL5)
+
+ # Antenna check parameters
+ # Note that checks w/diode diffusion are not modeled
+ model partial
+ antenna poly sidewall 50 none
+ antenna allcont surface 3 none
+ antenna li sidewall 75 0 450
+ antenna lic surface 3 0 18
+ antenna m1,m2,m3 sidewall 400 2600 400
+ antenna v1 surface 3 0 18
+ antenna v2 surface 6 0 36
+#ifdef METAL5
+ antenna m4,m5 sidewall 400 2600 400
+ antenna v3,v4 surface 6 0 36
+#endif (METAL5)
+
+ tiedown alldiffnonfet
+
+ substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
+
+# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
+
+# Resistances are in milliohms per square
+# Optional 3rd argument is the corner adjustment fraction
+# Device values come from trtc.cor (typical corner)
+ resist (dnwell)/dwell          2200000
+ resist (pwell)/well            3050000
+ resist (nwell)/well            1700000
+ resist (rpw)/well              3050000 0.5
+ resist (*ndiff,nsd)/active 	 120000
+ resist (*pdiff,*psd)/active	 197000
+ resist (*mvndiff,mvnsd)/active  114000
+ resist (*mvpdiff,*mvpsd)/active 191000
+
+ resist ndiffres/active 	120000 0.5
+ resist pdiffres/active 	197000 0.5
+ resist mvndiffres/active 	114000 0.5
+ resist mvpdiffres/active 	191000 0.5
+ resist mrp1/active		 48200 0.5
+ resist xhrpoly/active	        319800 0.5
+ resist uhrpoly/active	       2000000 0.5
+
+ resist (allpolynonres)/active   48200
+ resist rmp/active   		 48200
+
+ resist (allli)/locali		 12200
+ resist (allm1)/metal1		   125
+ resist (allm2)/metal2		   125
+ resist (allm3)/metal3	            47
+#ifdef METAL5
+ resist (allm4)/metal4  	    47
+ resist (allm5)/metal5  	    29
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ resist mrdl/metali		     5
+#endif (REDISTRIBUTION)
+
+ contact ndc,nsc		 15000
+ contact pdc,psc		 15000
+ contact mvndc,mvnsc		 15000
+ contact mvpdc,mvpsc	  	 15000
+ contact pc			 15000
+ contact lic			152000
+ contact m2c			  4500
+ contact m3c			  3410
+#ifdef METAL5
+#ifdef MIM
+ contact mimcc			  4500
+ contact mim2cc			  3410
+#endif (MIM)
+ contact via3			  3410
+ contact via4			   380
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ contact mrdlc			     6
+#endif (REDISTRIBUTION)
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values:  Use document (...)
+#-------------------------------------------------------------------------
+# This uses the new "default" definitions that determine the intervening
+# planes from the planeorder stack, take care of the reflexive sideoverlap
+# definitions, and generally clean up the section and make it more readable.
+#
+# Also uses "units microns" statement, so all parasitic capacitance values
+# are taken directly from the source document PDS_035_03, in units of
+# aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
+#-------------------------------------------------------------------------
+# Remember that device capacitances to substrate are taken care of by the
+# models.  Thus, active and poly definitions ignore all "fet" types.
+# fet types are excluded when computing parasitic capacitance to
+# active from layers above them because poly is a shield; fet types are
+# included for parasitics from layers above to poly.  Resistor types
+# should be removed from all parasitic capacitance calculations, or else
+# they just create floating caps.  Technically, the capacitance probably
+# should be split between the two terminals.  Unsure of the correct model.
+#-------------------------------------------------------------------------
+
+#n-well
+# NOTE:  This value not found in PEX files
+defaultareacap     nwell well 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  105
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active  63
+ defaultareacap     *poly active nwell,obswell,pwell well  63
+ defaultperimeter   *poly active nwell,obswell,pwell well  16
+
+#locali
+ defaultsidewall    allm1 metal1       113
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  37
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  8
+ defaultoverlap     allm1 metal1 nwell well 37
+
+#locali->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 36
+ defaultsideoverlap allm1 metal1 allactivenonfet active 9
+
+#locali->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 46
+ defaultsideoverlap allm1 metal1 allpolynonres active 10
+
+#metal1
+ defaultsidewall    allm1 metal1       113
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  17
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  8
+ defaultoverlap     allm1 metal1 nwell well 26
+
+#metal1->locali
+ defaultoverlap     allm1 metal1 allactivenonfet active 36
+ defaultsideoverlap allm1 metal1 allactivenonfet active 9
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 36
+ defaultsideoverlap allm1 metal1 allactivenonfet active 9
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 46
+ defaultsideoverlap allm1 metal1 allpolynonres active 10
+
+#metal2
+ defaultsidewall    allm2 metal2      101
+ defaultareacap     allm2 metal2 nwell,obswell,pwell well 12
+ defaultperimeter   allm2 metal2 nwell,obswell,pwell well 6
+ defaultoverlap     allm2 metal2 nwell well 13
+
+#metal2->diff
+ defaultoverlap     allm2 metal2 allactivenonfet active 14
+ defaultsideoverlap allm2 metal2 allactivenonfet active 7
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 16
+ defaultsideoverlap allm2 metal2 allpolynonres active 7
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 39
+ defaultsideoverlap allm2 metal2 allm1 metal1 10
+
+#metal3
+ defaultsidewall    allm3 metal3     102
+ defaultoverlap     allm3 metal3 nwell well 8
+ defaultareacap     allm3 metal3 nwell,obswell,pwell well 8
+ defaultperimeter   allm3 metal3 nwell,obswell,pwell well 5
+
+#metal3->diff
+ defaultoverlap     allm3 metal3 allactive active 9
+ defaultsideoverlap allm3 metal3 allactive active 6
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 10
+ defaultsideoverlap allm3 metal3 allpolynonres active 6
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 15
+ defaultsideoverlap allm3 metal3 allm1 metal1 7
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 39
+ defaultsideoverlap allm3 metal3 allm2 metal2 10
+
+#ifdef METAL5
+#metal4
+ defaultsidewall    allm4 metal4       102
+# defaultareacap     alltopm metal4 well  6
+ areacap     	    allm4/m4 8
+ defaultoverlap     allm4 metal4 nwell well 8
+ defaultperimeter   allm4 metal4 well  5
+
+#metal4->diff
+ defaultoverlap     allm4 metal4 allactivenonfet active 7
+ defaultsideoverlap allm4 metal4 allactivenonfet active 7
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 7
+ defaultsideoverlap allm4 metal4 allpolynonres active 5
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 9
+ defaultsideoverlap allm4 metal4 allm1 metal1 6
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 15
+ defaultsideoverlap allm4 metal4 allm2 metal2 7
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 39
+ defaultsideoverlap allm4 metal4 allm3 metal3 10
+
+#metal5
+ defaultsidewall    allm5 metal5       103
+# defaultareacap     allm5 metal5 well  6
+ areacap     	    allm5/m5 6
+ defaultoverlap     allm5 metal5 nwell well 6
+ defaultperimeter   allm5 metal5 well  5
+
+#metal5->diff
+ defaultoverlap     allm5 metal5 allactivenonfet active 5
+ defaultsideoverlap allm5 metal5 allactivenonfet active 5
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 5
+ defaultsideoverlap allm5 metal5 allpolynonres active 5
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 7
+ defaultsideoverlap allm5 metal5 allm1 metal1 5
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 9
+ defaultsideoverlap allm5 metal5 allm2 metal2 6
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 15
+ defaultsideoverlap allm5 metal5 allm3 metal3 7
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 39
+ defaultsideoverlap allm5 metal5 allm4 metal4 10
+#endif (METAL5)
+
+# Devices:  Use document (...)
+
+variants (sim)
+
+ device msubcircuit pshort pfet,scpfet *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit plowvt pfetlvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit phighvt pfethvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+
+ device msubcircuit nshort nfet,scnfet *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit nlowvt nfetlvt *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit sonos_e nsonos *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w
+ device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w
+ device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w
+
+ device msubcircuit phv mvpfet *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
+ device msubcircuit nhv mvnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+ device msubcircuit nhvnative mvnnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+
+ device rsubcircuit short rmp     *poly	 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rli1    *li,coreli space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal1 *metal1 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal2 *metal2 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal3 *metal3 space/w,pwell,nwell error l=l w=w
+#ifdef METAL5
+ device rsubcircuit short rm4 *m4 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rm5 *m5 space/w,pwell,nwell error l=l w=w
+#endif (METAL5)
+
+ device rsubcircuit xhrpoly  xhrpoly xpc pwell,space/w error l=l w=w
+ device rsubcircuit uhrpoly  uhrpoly xpc pwell,space/w error l=l w=w
+ device rsubcircuit mrp1     mrp1    *poly pwell,space/w error 	l=l w=w
+
+ device rsubcircuit mrdn     ndiffres *ndiff pwell,space/w  error l=l w=w
+ device rsubcircuit mrdp     pdiffres *pdiff nwell    error l=l w=w
+ device rsubcircuit xpwres   rpw       pwell dnwell error l=l w=w
+
+ device rsubcircuit mrdn_hv  mvndiffres *mvndiff pwell,space/w error l=l w=w
+ device rsubcircuit mrdp_hv  mvpdiffres *mvpdiff nwell   error l=l w=w
+
+ device subcircuit  pdiode *pdiode nwell a=a p=p
+ device msubcircuit ndiode *ndiode pwell,space/w a=a p=p
+ device subcircuit  pdiode_h *mvpdiode nwell a=a p=p
+ device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p
+
+ # These are parasitic devices
+ device msubcircuit ndiode_lvt *ndiodelvt pwell,space/w a=a p=p
+ device subcircuit  pdiode_lvt *pdiodelvt nwell a=a p=p
+ device subcircuit  pdiode_hvt *pdiodehvt nwell a=a p=p
+ device msubcircuit ndiode_native *nndiode pwell,space/w a=a p=p
+
+#ifdef MIM
+ device subcircuit xcmimc1 *mimcap  m3 nwell,pwell,space/w error a=a p=p s=subs
+ device subcircuit xcmimc2 *mimcap2 m4,mimcc/m4 nwell,pwell,space/w error a=a p=p s=subs
+#endif (MIM)
+
+ variants (lvs),(si)
+
+ device mosfet pshort scpfet,pfet pdiff,pdiffres,pdc nwell 
+ device mosfet plowvt pfetlvt pdiff,pdiffres,pdc nwell 
+ device mosfet phighvt pfethvt pdiff,pdiffres,pdc nwell 
+ device mosfet nshort scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
+ device mosfet nlowvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sonos_e nsonos ndiff,ndiffres,ndc pwell,space/w
+ device mosfet phv mvpfet mvpdiff,mvpdiffres,mvpdc nwell 
+ device mosfet nhv mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet nhvnative mvnnfet *mvndiff,mvndiffres pwell,space/w
+
+ # These devices always extract as subcircuits
+ device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w
+ device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w
+ device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w
+
+ device resistor short rmp     *poly
+ device resistor short rli1    *li,coreli
+ device resistor short rmetal1 *metal1
+ device resistor short rmetal2 *metal2
+ device resistor short rmetal3 *metal3
+#ifdef METAL5
+ device resistor short rm4 *m4
+ device resistor short rm5 *m5
+#endif (METAL5)
+
+ device resistor xhrpoly xhrpoly xpc 
+ device resistor uhrpoly uhrpoly xpc 
+ device resistor mrp1 mrp1       *poly 
+ device resistor mrdn  ndiffres *ndiff 
+ device resistor mrdp  pdiffres *pdiff 
+ device resistor mrdn_hv   mvndiffres *mvndiff 
+ device resistor mrdp_hv   mvpdiffres *mvpdiff 
+ device resistor xpwres   rpw    pwell
+
+ device pdiode pdiode *pdiode nwell a=a p=p
+ device ndiode ndiode *ndiode pwell,space/w a=a p=p
+ device pdiode pdiode_h *mvpdiode nwell a=a p=p
+ device ndiode ndiode_h *mvndiode pwell,space/w a=a p=p
+
+ # These are parasitic devices
+ device ndiode ndiode_lvt *ndiodelvt pwell,space/w a=a p=p
+ device pdiode pdiode_lvt *pdiodelvt nwell a=a p=p
+ device pdiode pdiode_hvt *pdiodehvt nwell a=a p=p
+ device ndiode ndiode_native *nndiode pwell,space/w a=a p=p
+
+ device subcircuit  pdiode_h *mvpdiode nwell a=a p=p
+ device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p
+
+
+#ifdef MIM
+ device capacitor xcmimc1 *mimcap  *m3 1
+ device capacitor xcmimc2 *mimcap2 *m4 1
+#endif (MIM)
+
+end
+
+#-----------------------------------------------------
+# Wiring tool definitions
+#-----------------------------------------------------
+
+wiring
+ # All wiring values are in nanometers
+ scalefactor 10
+
+ contact lic 170 li 0  0 m1 30 60
+ contact v1  260 m1 0 30 m2  0 30  
+ contact v2  280 m2 0 45 m3 25  0
+#ifdef METAL5
+ contact v3  320 m3 0 30 m4  0  5
+ contact v4 1180 m4 0    m5 120 
+#endif (METAL5)
+
+ contact pc  170  poly 50 80 li 0 80
+ contact pdc 170 pdiff 40 60 li 0 80
+ contact ndc 170 ndiff 40 60 li 0 80
+ contact psc 170   psd 40 60 li 0 80
+ contact nsc 170   nsd 40 60 li 0 80
+
+end
+
+#-----------------------------------------------------
+# Plain old router. . . 
+#-----------------------------------------------------
+
+router
+end
+
+#------------------------------------------------------------
+# Plowing (restored in magic 8.2, need to fill this section)
+#------------------------------------------------------------
+
+plowing
+end
+
+#-----------------------------------------------------------------
+# No special plot layers defined (use default PNM color choices)
+#-----------------------------------------------------------------
+
+plot
+  style pnm
+     default
+     draw fillblock no_color_at_all
+     draw nwell cwell
+end
+
diff --git a/sky130/sky130_fd_sc_hd_config.tcl b/sky130/sky130_fd_sc_hd_config.tcl
new file mode 100644
index 0000000..4d9393a
--- /dev/null
+++ b/sky130/sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,41 @@
+set current_folder [file dirname [file normalize [info script]]]
+# Technology lib
+
+set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(PDK_VARIANT)/sky130_fd_sc_hd_tt_1.80v_25C.lib"
+set ::env(LIB_MAX) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(PDK_VARIANT)/sky130_fd_sc_hd_ff_1.95v_-40C.lib"
+set ::env(LIB_MIN) "$::env(PDK_ROOT)$::env(PDK)/libs.ref/lib/$::env(PDK_VARIANT)/sky130_fd_sc_hd_ss_1.60v_100C.lib"
+
+
+set ::env(LIB_TYPICAL) $::env(LIB_SYNTH)
+
+# welltap and endcap cells
+set ::env(FP_WELLTAP_CELL) "sky130_fd_sc_hd_tapvpwrvgnd_1"
+set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hd_decap_3"
+
+# defaults (can be overridden by designs):
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd_inv_8"
+#capacitance : 0.017653;
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+# update these
+set ::env(SYNTH_CAP_LOAD) "17.65" ; # femtofarad _inv_8 pin A cap
+set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd_buf_2 A X"
+set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd_conb_1 HI"
+set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd_conb_1 LO"
+
+# cts defaults
+set ::env(CTS_ROOT_BUFFER) sky130_fd_sc_hd_clkbuf_16
+set ::env(CELL_CLK_PORT) CLK
+
+# Placement defaults
+set ::env(PL_LIB) $::env(LIB_TYPICAL)
+
+# Fillcell insertion
+set ::env(FILL_CELL) "sky130_fd_sc_hd_decap_ sky130_fd_sc_hd_fill_"
+
+set ::env(CELL_PAD) 2
+set ::env(CELL_PAD_EXECLUDE) "$::env(PDK_VARIANT)_tap* $::env(PDK_VARIANT)_decap* $::env(PDK_VARIANT)_fill*"
+
+set ::env(ROOT_CLK_BUFFER) $::env(PDK_VARIANT)_clkbuf_16
+set ::env(CLK_BUFFER) $::env(PDK_VARIANT)_clkbuf_4
+set ::env(CLK_BUFFER_INPUT) A
+set ::env(CLK_BUFFER_OUTPUT) X
diff --git a/sky130/sky130_make_torture.tcl b/sky130/sky130_make_torture.tcl
new file mode 100644
index 0000000..580dc0f
--- /dev/null
+++ b/sky130/sky130_make_torture.tcl
@@ -0,0 +1,313 @@
+#---------------------------------------
+# Torture test generator for EFS8
+# (Specifically for EFS8B)
+# (work in progress)
+#---------------------------------------
+
+namespace path {::tcl::mathop ::tcl::mathfunc}
+
+# Set random seed so that torture test is not random from run to run.
+srand 1234567
+
+# NxN array MOSFET devices
+
+proc mos_array {n devname startx starty {deltax 12700} {deltay 254}} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 20]]
+         set w [+ 0.22 [* 0.5 $r]]
+         set r [int [* [rand] 20]]
+         set l [+ 0.18 [* 0.3 $r]]
+         set m [int [+ 1 [* [rand] 8]]]
+         set nf [int [+ 1 [* [rand] 8]]]
+
+         set r [int [* [rand] 8]]
+         set dcov [+ 20 [* 10 $r]]
+         set r [int [* [rand] 8]]
+         set pcov [+ 20 [* 10 $r]]
+         set r [int [* [rand] 8]]
+         set rlcov [+ 20 [* 10 $r]]
+
+         if {[rand] > 0.5} {set pov 1} else {set pov 0}
+         if {[rand] > 0.5} {set dov 1} else {set dov 0}
+         if {[rand] > 0.5} {set tc 1} else {set tc 0}
+         if {[rand] > 0.5} {set bc 1} else {set bc 0}
+         if {[rand] > 0.5} {set fm 1} else {set fm 0}
+         if {[rand] > 0.5} {set gl 1} else {set gl 0}
+         if {[rand] > 0.5} {set gr 1} else {set gr 0}
+         if {[rand] > 0.5} {set gt 1} else {set gt 0}
+         if {[rand] > 0.5} {set gb 1} else {set gb 0}
+
+         magic::gencell sky130::${devname} ${devname}_$i \
+		w $w l $l m $m nf $nf diffcov $dcov polycov $pcov \
+		rlcov $rlcov poverlap $pov doverlap $dov topc $tc \
+		botc $bc full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh $deltay]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e $deltax
+   }
+   resumeall
+}
+
+# NxN array resistor devices
+
+proc res_array {n devname startx starty {deltax 12700} {deltay 254}} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 10]]
+         set w [+ 0.42 [* 0.5 $r]]
+         set r [int [* [rand] 50]]
+         set l [+ 2.10 [* 2.0 $r]]
+         set m [int [+ 1 [* [rand] 2]]]
+         set nx [int [+ 1 [* [rand] 10]]]
+
+         set r [int [* [rand] 8]]
+         set ecov [+ 20 [* 10 $r]]
+
+         if {[rand] > 0.5} {set rov 1} else {set rov 0}
+	 if {[rand] > 0.5} {set sn 1} else {set sn 0}
+         if {[rand] > 0.5} {set fm 1} else {set fm 0}
+         if {[rand] > 0.5} {set gl 1} else {set gl 0}
+         if {[rand] > 0.5} {set gr 1} else {set gr 0}
+         if {[rand] > 0.5} {set gt 1} else {set gt 0}
+         if {[rand] > 0.5} {set gb 1} else {set gb 0}
+
+	 # Snake geometry does not apply to xhrpoly, uhrpoly, and xpwres, and
+	 # roverlap and endcov are prohibited.
+	 if {$devname == "xhrpoly" || $devname == "uhrpoly" || $devname == "xpwres"} {
+	    magic::gencell sky130::${devname} ${devname}_$i \
+		w $w l $l m $m nx $nx full_metal $fm \
+		glc $gl grc $gr gbc $gb gtc $gt
+	 } else {
+	    magic::gencell sky130::${devname} ${devname}_$i \
+		w $w l $l m $m nx $nx endcov $ecov roverlap $rov \
+		snake $sn full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
+	 }
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh $deltay]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e $deltax
+   }
+   resumeall
+}
+
+# NxN array diode devices
+
+proc diode_array {n devname startx starty} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 10]]
+         set w [+ 0.42 [* 0.5 $r]]
+         set r [int [* [rand] 10]]
+         set l [+ 0.42 [* 0.5 $r]]
+         set nx [int [+ 1 [* [rand] 4]]]
+         set ny [int [+ 1 [* [rand] 4]]]
+
+         if {[rand] > 0.5} {set dov 1} else {set dov 0}
+         if {[rand] > 0.5} {set el 1} else {set el 0}
+         if {[rand] > 0.5} {set er 1} else {set er 0}
+         if {[rand] > 0.5} {set et 1} else {set et 0}
+         if {[rand] > 0.5} {set eb 1} else {set eb 0}
+         if {[rand] > 0.5} {set fm 1} else {set fm 0}
+         if {[rand] > 0.5} {set gl 1} else {set gl 0}
+         if {[rand] > 0.5} {set gr 1} else {set gr 0}
+         if {[rand] > 0.5} {set gt 1} else {set gt 0}
+         if {[rand] > 0.5} {set gb 1} else {set gb 0}
+
+         magic::gencell sky130::${devname} ${devname}_$i \
+		w $w l $l nx $nx ny $ny doverlap $dov \
+		full_metal $fm elc $el erc $er etc $et \
+		ebc $eb glc $gl grc $gr gbc $gb gtc $gt
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh 254]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e 12700
+   }
+   resumeall
+}
+
+# NxN array cap devices
+
+proc cap_array {n devname startx starty {deltax 12700} {deltay 160}} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 10]]
+         set w [+ 2.00 [* 1.0 $r]]
+         set r [int [* [rand] 10]]
+         set l [+ 2.00 [* 1.0 $r]]
+         set nx [int [+ 1 [* [rand] 4]]]
+         set ny [int [+ 1 [* [rand] 4]]]
+
+         if {[rand] > 0.5} {set bc 1} else {set bc 0}
+         if {[rand] > 0.5} {set tc 1} else {set tc 0}
+
+         magic::gencell sky130::${devname} ${devname}_$i \
+		w $w l $l nx $nx ny $ny bconnect $bc tconnect $tc
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh $deltay]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e $deltax
+   }
+   resumeall
+}
+
+# NxN fixed devices
+
+proc fixed_array {n devname startx starty} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set nx [int [+ 1 [* [rand] 4]]]
+         set ny [int [+ 1 [* [rand] 4]]]
+
+         # Do not change the deltas---this will cause DRC problems
+         set r 0
+         # set r [int [* [rand] 10]]
+         set deltax [/ $r 10.0]
+         # set r [int [* [rand] 10]]
+         set deltay [/ $r 10.0]
+
+         magic::gencell sky130::${devname} ${devname}_$i \
+		nx $nx ny $ny deltax $deltax deltay $deltay
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [* $bh [+ $ny 1]]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e 20000
+   }
+   resumeall
+}
+
+snap int
+box size 0 0
+ 
+# Layout:
+#  phv
+#        mrl1     mrp1   mrdp   mrdp_hv  
+#  nhv                                  pdiode_h
+#                                       ndiode_h
+#  pshort                               nndiode
+#        xhrpoly  xpwres mrdn   mrdn_hv  pdiode
+#  nshort                               ndiode
+#
+
+mos_array 6 nshort 0 0
+mos_array 6 pshort 0 75000
+mos_array 6 nhv 0 150000 
+mos_array 6 phv 0 225000
+mos_array 6 nlowvt 0 300000
+mos_array 6 sonos_e 0 375000 12700 1650
+mos_array 6 plowvt 0 450000
+mos_array 6 phighvt 0 525000
+mos_array 6 nhvnative 0 600000 
+
+res_array 6 xhrpoly 100000 0
+res_array 6 mrl1 100000 180000
+res_array 6 uhrpoly 100000 360000
+
+res_array 6 xpwres 200000 0 13500 1100
+res_array 6 mrp1 200000 200000
+
+res_array 6 mrdn 300000 0
+res_array 6 mrdp 300000 180000
+
+res_array 6 mrdn_hv 400000 0
+res_array 6 mrdp_hv 400000 180000
+ 
+diode_array 6 ndiode 500000 0
+diode_array 6 pdiode 500000 30000 
+diode_array 6 ndiode_h 500000 60000
+diode_array 6 pdiode_h 500000 90000 
+
+cap_array 6 xcmimc1 600000 0
+cap_array 6 xcmimc2 600000 70000 18000 650
+
+mos_array 6 xcnwvc 700000 0 15000 254
+mos_array 6 xchvnwc 700000 70000 18000 254
+mos_array 6 xcnwvc2 700000 140000 15000 254
+
+fixed_array 2 sky130_fd_pr_rf_npn_1x1 850000 0
+fixed_array 2 sky130_fd_pr_rf_npn_1x2 850000 30000
+fixed_array 2 sky130_fd_pr_rf_pnp5x 850000 60000
+
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp11p5x11p7_lim5shield 900000 0
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp11p5x11p7_m3_lim5shield 900000 30000
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp11p5x11p7_m4shield 900000 60000
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym4shield 900000 90000
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp4p4x4p6_m3_lim5shield 900000 120000
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp6p8x6p1_lim4shield 900000 150000
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp6p8x6p1_polym4shield 900000 180000
+fixed_array 2 sky130_fd_pr_rf2_xcmvpp8p6x7p9_m3_lim5shield 900000 210000
+fixed_array 2 sky130_fd_pr_rf2_xcmvppx4_2xnhvnative10x4 900000 240000
+# fixed_array 2 sky130_fd_pr_rf2_xcmvpp11p5x11p7_polym50p4shield 900000 270000
+
+fixed_array 2 sky130_fd_pr_rf_xcmvpp11p5x11p7_m3_lishield 950000 0
+fixed_array 2 sky130_fd_pr_rf_xcmvpp11p5x11p7_m3shield 950000 30000
+fixed_array 2 sky130_fd_pr_rf_xcmvpp2 950000 60000
+fixed_array 2 sky130_fd_pr_rf_xcmvpp2_nwell 950000 90000
+fixed_array 2 sky130_fd_pr_rf_xcmvpp4p4x4p6_m3_lishield 950000 120000
+fixed_array 2 sky130_fd_pr_rf_xcmvpp4p4x4p6_m3shield 950000 150000
+fixed_array 2 sky130_fd_pr_rf_xcmvpp8p6x7p9_m3_lishield 950000 180000
+fixed_array 2 sky130_fd_pr_rf_xcmvpp8p6x7p9_m3shield 950000 210000
+# fixed_array 2 sky130_fd_pr_rf_xcmvpp1p8x1p8_lishield 950000 240000
+# fixed_array 2 sky130_fd_pr_rf_xcmvpp1p8x1p8_m3shield 950000 270000
+
+fixed_array 1 balun 1000000 0
+fixed_array 1 xind4_02 1000000 200000
+fixed_array 1 xind4_011 1250000 0
+
+# Draw a deep nwell region around the sonos transistor block
+box values -5200i 369500i 76800i 427500i
+sky130::deep_nwell_draw
+
+save torture_test_sky130
+gds write torture_test_sky130
diff --git a/sky130/sky130_setup.tcl b/sky130/sky130_setup.tcl
new file mode 100644
index 0000000..af90784
--- /dev/null
+++ b/sky130/sky130_setup.tcl
@@ -0,0 +1,296 @@
+###
+###     Source file sky130_setup.tcl
+###     Process this file with the preproc.py processor
+###
+#---------------------------------------------------------------
+# Setup file for netgen LVS
+# SkyWater TECHNAME
+#---------------------------------------------------------------
+permute default
+property default
+property parallel none
+
+#---------------------------------------------------------------
+# For the following, get the cell lists from
+# circuit1 and circuit2.
+#---------------------------------------------------------------
+
+set cells1 [cells list -all -circuit1]
+set cells2 [cells list -all -circuit2]
+
+# NOTE:  In accordance with the LVS manager GUI, the schematic is
+# always circuit2, so some items like property "par1" only need to
+# be specified for circuit2.
+
+#-------------------------------------------
+# Resistors (except metal)
+#-------------------------------------------
+
+set devices {xpwres mrp1 xhrpoly uhrpoly mrdn mrdp mrdn_hv mrdp_hv}
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	permute "-circuit1 $dev" 1 2
+	property "-circuit1 $dev" series enable
+	property "-circuit1 $dev" series {w critical}
+	property "-circuit1 $dev" series {l add}
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" parallel {value par}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	permute "-circuit2 $dev" 1 2
+	property "-circuit1 $dev" series enable
+	property "-circuit1 $dev" series {w critical}
+	property "-circuit1 $dev" series {l add}
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" parallel {value par}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+}
+
+#-------------------------------------------
+# MRM (metal) resistors
+#-------------------------------------------
+
+set devices {mrl1 mrm1 mrm2 mrm3}
+#ifdef METAL5
+lappend devices mrm4
+lappend devices mrm5
+#endif (METAL5)
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	permute "-circuit1 $dev" 1 2
+	property "-circuit1 $dev" series enable
+	property "-circuit1 $dev" series {w critical}
+	property "-circuit1 $dev" series {l add}
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" parallel {value par}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	permute "-circuit2 $dev" 1 2
+	property "-circuit1 $dev" series enable
+	property "-circuit1 $dev" series {w critical}
+	property "-circuit1 $dev" series {l add}
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" parallel {value par}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+}
+
+#-------------------------------------------
+# (MOS) transistors
+#-------------------------------------------
+
+set devices {nshort nlowvt sonos_e nhvnative nhv pshort plowvt phighvt phv}
+lappend devices xcnwvc
+lappend devices xcnwvc2
+lappend devices xchvnwc
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	permute "-circuit1 $dev" 1 3
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" tolerance {w 0.01} {l 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 NRD NRS
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	permute "-circuit2 $dev" 1 3
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit2 $dev" tolerance {w 0.01} {l 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 NRD NRS
+    }
+}
+
+#-------------------------------------------
+# diodes
+#-------------------------------------------
+
+set devices {ndiode ndiode_lvt pdiode pdiode_lvt pdiode_hvt ndiode_h pdiode_h}
+lappend devices ndiode_native
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {area add}
+	property "-circuit1 $dev" parallel {value add}
+	property "-circuit1 $dev" tolerance {area 0.02}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 peri
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	property "-circuit1 $dev" parallel {area add}
+	property "-circuit1 $dev" parallel {value add}
+	property "-circuit2 $dev" tolerance {area 0.02}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 peri
+    }
+}
+
+#-------------------------------------------
+# capacitors
+# MiM capacitors
+#-------------------------------------------
+
+set devices {xcmimc1 xcmimc2}
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {area add}
+	property "-circuit1 $dev" parallel {value add}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {area add}
+	property "-circuit1 $dev" parallel {value add}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+}
+
+#-------------------------------------------
+# Fixed-layout devices
+# bipolar transistors,
+# VPP capacitors
+#-------------------------------------------
+
+set devices {sky130rf_npn_1x1 sky130rf_npn_1x2 sky130rf_pnp5x}
+#ifdef METAL5
+lappend devices balun xint4_011 xind4_02
+lappend devices sky130rf2_xcmvpp11p5x11p7_lim5shield
+lappend devices sky130rf2_xcmvpp11p5x11p7_m3_lim5shield
+lappend devices sky130rf2_xcmvpp11p5x11p7_m4shield
+lappend devices sky130rf2_xcmvpp11p5x11p7_polym4shield
+lappend devices sky130rf2_xcmvpp11p5x11p7_polym50p4shield
+lappend devices sky130rf2_xcmvpp4p4x4p6_m3_lim5shield
+lappend devices sky130rf2_xcmvpp6p8x6p1_lim4shield
+lappend devices sky130rf2_xcmvpp6p8x6p1_polym4shield
+#endif (METAL5)
+lappend devices sky130rf2_xcmvpp8p6x7p9_m3_lim5shield
+lappend devices sky130rf2_xcmvppx4_2xnhvnative10x4
+lappend devices sky130rf_xcmvpp11p5x11p7_m3_lishield
+lappend devices sky130rf_xcmvpp11p5x11p7_m3shield
+lappend devices sky130rf_xcmvpp1p8x1p8_lishield
+lappend devices sky130rf_xcmvpp1p8x1p8_m3shield
+lappend devices sky130rf_xcmvpp2
+lappend devices sky130rf_xcmvpp2_nwell
+lappend devices sky130rf_xcmvpp4p4x4p6_m3_lishield
+lappend devices sky130rf_xcmvpp4p4x4p6_m3shield
+lappend devices sky130rf_xcmvpp8p6x7p9_m3_lishield
+lappend devices sky130rf_xcmvpp8p6x7p9_m3shield
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1
+    }
+}
+
+#---------------------------------------------------------------
+# Digital cells (ignore decap, fill, and tap cells)
+# Make a separate list for each supported library
+#---------------------------------------------------------------
+# e.g., ignore class "-circuit2 sky130_fc_sc_hd_decap_3"
+#---------------------------------------------------------------
+
+foreach cell $cells1 {
+    if {[regexp "sky130_fc_sc_hd_decap_\[0-9\]+" $cell match]} {
+        ignore class "-circuit1 $cell"
+    }
+    if {[regexp "sky130_fc_sc_hd_fill_\[0-9\]+" $cell match]} {
+        ignore class "-circuit1 $cell"
+    }
+}
+foreach cell $cells2 {
+    if {[regexp "sky130_fc_sc_hd_decap_\[0-9\]+" $cell match]} {
+        ignore class "-circuit2 $cell"
+    }
+    if {[regexp "sky130_fc_sc_hd_fill_\[0-9\]+" $cell match]} {
+        ignore class "-circuit2 $cell"
+    }
+}
+
+#---------------------------------------------------------------
+# Handle cells captured from Electric
+#
+# Find cells of the form "<library>__<cellname>" in the netlist
+# from Electric where the extracted layout netlist has only
+# "<cellname>".  Cross-check by ensuring that the full name
+# "<library>__<cellname>" does not exist in both cells, and that
+# the truncated name "<cellname>" does not exist in both cells.
+#---------------------------------------------------------------
+# e.g., hydra_spi_controller__hydra_spi_controller
+#---------------------------------------------------------------
+foreach cell $cells1 {
+    if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+        if {([lsearch $cells2 $cell] < 0) && \
+                ([lsearch $cells2 $cellname] >= 0) && \
+                ([lsearch $cells1 $cellname] < 0)} {
+            equate classes "-circuit1 $cell" "-circuit2 $cellname"
+	    puts stdout "Matching pins of $cell in circuit 1 and $cellname in circuit 2"
+	    equate pins "-circuit1 $cell" "-circuit2 $cellname"
+        }
+    }
+}
+
+foreach cell $cells2 {
+    if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+        if {([lsearch $cells1 $cell] < 0) && \
+                ([lsearch $cells1 $cellname] >= 0) && \
+                ([lsearch $cells2 $cellname] < 0)} {
+            equate classes "-circuit1 $cellname" "-circuit2 $cell"
+	    puts stdout "Matching pins of $cellname in circuit 1 and $cell in circuit 2"
+	    equate pins "-circuit1 $cellname" "-circuit2 $cell"
+        }
+    }
+}
+
+# Match pins on black-box cells if LVS is called with "-blackbox"
+if {[model blackbox]} {
+    foreach cell $cells1 {
+	if {[model "-circuit1 $cell"] == "blackbox"} {
+	    if {[lsearch $cells2 $cell] >= 0} {
+		puts stdout "Matching pins of $cell in circuits 1 and 2"
+		equate pins "-circuit1 $cell" "-circuit2 $cell"
+	    }
+	}
+    }
+}
+
+#---------------------------------------------------------------
diff --git a/sky130/sky130gds.tech b/sky130/sky130gds.tech
new file mode 100644
index 0000000..8beebdc
--- /dev/null
+++ b/sky130/sky130gds.tech
@@ -0,0 +1,689 @@
+tech
+    format 32
+    TECHNAME-GDS
+end
+
+version
+    version REVISION
+    description "SkyWater S8: Vendor GDS layers"
+end
+
+planes
+ p1
+ p2
+ p3
+ p4
+ p5
+ p6
+ p7
+ p8
+ p9
+ p10
+ p11
+ p12
+ p13
+ p14
+ p15
+ p16
+ p17
+ p18
+ p19
+ p20
+ p21
+ p22
+ p23
+ p24
+ p25
+ p26
+ p27
+ p28
+ p29
+ p30
+ p31
+ p32
+ p33
+ p34
+ p35
+ p36
+ p37
+ p38
+ p39
+ p40
+ p41
+ p42
+end
+
+types
+ p1  NWELL,l1
+ p1  NWELLT,l60
+ p1  NWELLP,l62
+ p2  DNWELL,l2
+ p3  DIFF,l3
+ p3  TAP,l4
+ p4  LVTN,l5
+ p4  HVTP,l6
+ p5  HVI,l7
+ p6  TUNM,l8
+ p7  POLY,l9
+ p7  POLYP,l63
+ p7  POLYT,l70
+ p8  NPC,l10
+ p9  PSDM,l11
+ p9  NSDM,l12
+ p10 LICON1,l13
+ p11 LI1,l14
+ p11 LI1T,l15
+ p11 LI1P,l16
+ p12 MCON,l17
+ p12 MET1,l18
+ p12 MET1T,l19
+ p12 MET1P,l20
+ p13 VIA1,l21
+ p13 MET2,l22
+ p13 MET2T,l23
+ p13 MET2P,l24
+ p14 VIA2,l25
+ p14 MET3,l26
+ p14 MET3T,l27
+ p14 MET3P,l28
+ p15 VIA3,l29
+ p15 MET4,l30
+ p15 MET4T,l31
+ p15 MET4P,l32
+ p16 VIA4,l33
+ p16 MET5,l34
+ p16 MET5T,l35
+ p16 MET5P,l36
+ p17 PAD,l37
+ p17 PADT,l38
+ p17 PADP,l39
+ p18 AREAID,l40
+ p19 TEXT,l41
+ p20 HVTR,l42
+ p21 NCM,l43
+ p22 RPM,l44
+ p23 NSM,l45
+ p24 RDL,l46
+ p25 VHVI,l47
+ p26 LDNTM,l48
+ p26 HVNTM,l49
+ p27 PMM,l50
+ p28 PNP,l51
+ p29 CAP,l52
+ p30 IND,l53
+ p31 PWRES,l54
+ p32 POLYRES,l55
+ p33 DIFFRES,l56
+ p34 DIODE,l57
+ p35 POLYM,l58
+ p36 COREID,l59
+ p37 PWELLT,l61
+ p37 PWELLP,l64
+ p38 CFOMDROP,l65
+ p39 CLI1MADD,l66
+ p40 CNTMADD,l67
+ p41 CP1MADD,l68
+ p42 BOUND,l69
+end
+
+contact
+end
+
+styles
+    styletype	mos
+ l1   nwell
+ l2   cwell
+ l3   ndiffusion
+ l4   pdiffusion
+ l5   implant1
+ l6   implant2
+ l7   implant3
+ l8   subcircuit
+ l9    polysilicon
+ l10   implant4
+ l11   pdop_stripes
+ l12   ndop_stripes
+ l13   obsmetal1 contact_X'es
+ l14   metal1
+ l15   metal1
+ l16   metal1
+ l17   metal1 metal2 via1
+ l18   metal2
+ l19   metal2
+ l20   metal2
+ l21   metal2 metal3 via2
+ l22   metal3
+ l23   metal3
+ l24   metal3
+ l25   metal3 metal4 via3
+ l26   metal4
+ l27   metal4
+ l28   metal4
+ l29   metal4 metal5 via4
+ l30   metal5
+ l31   metal5
+ l32   metal5
+ l33   metal5 metal6 via5
+ l34   metal6
+ l35   metal6
+ l36   metal6
+ l37   overglass
+ l38   overglass
+ l39   overglass
+ l40   subcircuit
+ l41   comment
+ l42   implant1
+ l43   mim_top
+ l44   mim_bottom
+ l45   ntransistor_stripes
+ l46   metal7
+ l47   electrode
+ l48   nwell_field_implant
+ l49   hvndiff_mask
+ l50   poly_light
+ l51   mvpdiff
+ l52   mvndiff
+ l53   hvpdiff
+ l54   cwellnsc
+ l55   poly_resist poly_resist_stripes
+ l56   ptransistor_stripes
+ l57   hvpdiff_mask
+ l58   poly_resist
+ l59   subcircuit
+ l60   nwell
+ l61   pwell
+ l62   nwell
+ l63   polysilicon
+ l64   pwell
+ l65   implant1
+ l66   implant2
+ l67   implant3
+ l68   implant4
+ l69   subcircuit
+ l70   polysilicon
+end
+
+compose
+   paint  MCON    MET1  MCON
+   paint  VIA1    MET2  VIA1
+   paint  VIA2    MET3  VIA2
+   paint  VIA3    MET4  VIA3
+   paint  VIA4    MET5  VIA4
+end
+
+connect
+end
+
+cifoutput
+style gdsii
+  scalefactor 50 nanometers
+  options calma-permissive-labels
+ layer  NWELL NWELL,NWELLT,NWELLP
+ calma 64 20
+
+ layer NWELLT
+ labels NWELLT noport
+ calma 64 16
+
+ layer NWELLP
+ labels NWELLP port
+ calma 64 5
+
+ layer  DNWELL DNWELL
+ labels DNWELL 
+ calma 64 18
+
+ layer  DIFF DIFF
+ labels DIFF 
+ calma 65 20
+
+ layer  TAP TAP
+ labels TAP 
+ calma 65 44
+
+ layer  POLY POLY,POLYP,POLYT
+ calma 66 20
+
+ layer POLYT
+ labels POLYT noport
+ calma 66 16
+
+ layer POLYP
+ labels POLYP port
+ calma 66 5
+
+ layer  LVTN LVTN
+ labels LVTN 
+ calma 125 44
+
+ layer  HVTP HVTP
+ labels HVTP 
+ calma 78 44
+
+ layer  HVI HVI
+ labels HVI 
+ calma 75 20
+
+ layer  TUNM TUNM
+ labels TUNM 
+ calma 80 20
+
+ layer  NPC NPC
+ labels NPC 
+ calma 95 20
+
+ layer  PSDM PSDM
+ labels PSDM 
+ calma 94 20
+
+ layer  NSDM NSDM
+ labels NSDM 
+ calma 93 44
+
+ layer  LICON1 LICON1
+ labels LICON1 
+ calma 66 44
+
+ # Note: LICON1 not on LI1 plane, may not be coincident with LI1.
+ layer  LI1 LI1,LI1T,LI1P
+ calma 67 20
+
+ layer  LI1T
+ labels LI1T noport
+ calma 67 16
+
+ layer  LI1P
+ labels LI1P port
+ calma 67 5
+
+ layer  MET1 MET1,MET1T,MET1P,MCON
+ calma 68 20
+
+ layer  MET1T
+ labels MET1T noport
+ calma 68 16
+
+ layer  MET1P
+ labels MET1P port
+ calma 68 5
+
+ layer  MCON MCON
+ labels MCON 
+ calma 67 44
+
+ layer  MET2 MET2,MET2T,MET2P,VIA1
+ calma 69 20
+
+ layer  MET2T
+ labels MET2T noport
+ calma 69 16
+
+ layer  MET2P
+ labels MET2P port
+ calma 69 5
+
+ layer  VIA1 VIA1
+ labels VIA1 
+ calma 68 44
+
+ layer  MET3 MET3,MET3T,MET3P,VIA2
+ calma 70 20
+
+ layer  MET3T
+ labels MET3T noport
+ calma 70 16
+
+ layer  MET3P
+ labels MET3P port
+ calma 70 5
+
+ layer  VIA2 VIA2
+ labels VIA2 
+ calma 69 44
+
+ layer  MET4 MET4,MET4T,MET4P,VIA3
+ calma 71 20
+
+ layer  MET4T
+ labels MET4T noport
+ calma 71 16
+
+ layer  MET4P
+ labels MET4P port
+ calma 71 5
+
+ layer  VIA3 VIA3
+ labels VIA3 
+ calma 70 44
+
+ layer  MET5 MET5,MET5T,MET5P,VIA4
+ calma 72 20
+
+ layer  MET5T
+ labels MET5T noport
+ calma 72 16
+
+ layer  MET5P
+ labels MET5P port
+ calma 72 5
+
+ layer  VIA4 VIA4
+ labels VIA4 
+ calma 71 44
+
+ layer  PAD PAD,PADT,PADP
+ calma 76 20
+
+ layer  PADT
+ labels PADT noport
+ calma 76 16
+
+ layer  PADP
+ labels PADP port
+ calma 76 5
+
+ layer  AREAID AREAID
+ labels AREAID
+ calma 81 4
+
+ layer  TEXT TEXT
+ labels TEXT
+ calma 83 44
+
+ layer HVTR HVTR
+ labels HVTR
+ calma 18 20
+
+ layer NCM NCM
+ labels NCM
+ calma 92 44
+
+ layer RPM RPM
+ labels RPM
+ calma 86 20
+
+ layer NSM NSM
+ labels NSM
+ calma 61 20
+
+ layer RDL RDL
+ labels RDL
+ calma 74 20
+
+ layer VHVI VHVI
+ labels VHVI
+ calma 74 21
+
+ layer LDNTM LDNTM
+ labels LDNTM
+ calma 11 44
+
+ layer HVNTM HVNTM
+ labels HVNTM
+ calma 125 20
+
+ layer PMM PMM
+ labels PMM
+ calma 85 44
+
+ layer PNP PNP
+ labels PNP
+ calma 82 44
+
+ layer CAP CAP
+ labels CAP
+ calma 82 64
+
+ layer IND IND
+ labels IND
+ calma 82 24
+
+ layer PWRES PWRES
+ labels PWRES
+ calma 64 13
+
+ layer POLYRES POLYRES
+ labels POLYRES
+ calma 66 13
+
+ layer DIFFRES DIFFRES
+ labels DIFFRES
+ calma 65 13
+
+ layer DIODE DIODE
+ labels DIODE
+ calma 81 23
+
+ layer POLYM POLYM
+ labels POLYM
+ calma 66 83
+
+ layer COREID COREID
+ labels COREID
+ calma 81 2
+
+ layer PWELLT PWELLT
+ labels PWELLT noport
+ calma 122 16
+
+ layer PWELLP PWELLP
+ labels PWELLP port
+ calma 64 59
+
+ layer CFOMDROP CFOMDROP
+ labels CFOMDROP
+ calma 22 22
+
+ layer CLI1MADD CLI1MADD
+ labels CLI1MADD
+ calma 115 43
+
+ layer CNTMADD CNTMADD
+ labels CNTMADD
+ calma 22 21
+
+ layer CP1MADD CP1MADD
+ labels CP1MADD
+ calma 33 43
+
+ layer BOUND BOUND
+ labels BOUND
+ calma 235 4
+end
+
+cifinput
+style ProgName
+  scalefactor 50 nanometers
+ layer l1  NWELL
+ layer l2  DNWELL
+ layer l3  DIFF
+ layer l4  TAP
+ layer l5  LVTN
+ layer l6  HVTP
+ layer l7  HVI
+ layer l8  TUNM
+ layer l9  POLY
+ layer l10 NPC
+ layer l11 PSDM
+ layer l12 NSDM
+ layer l13 LICON1
+ layer l14 LI1
+ layer l15 LI1T
+ layer l16 LI1P
+ layer l17 MCON
+ layer l18 MET1
+ layer l19 MET1T
+ layer l20 MET1P
+ layer l21 VIA1
+ layer l22 MET2
+ layer l23 MET2T
+ layer l24 MET2P
+ layer l25 VIA2
+ layer l26 MET3
+ layer l27 MET3T
+ layer l28 MET3P
+ layer l29 VIA3
+ layer l30 MET4
+ layer l31 MET4T
+ layer l32 MET4P
+ layer l33 VIA4
+ layer l34 MET5
+ layer l35 MET5T
+ layer l36 MET5P
+ layer l37 PAD
+ layer l38 PADT
+ layer l39 PADP
+ layer l40 AREAID
+ layer l41 TEXT
+ layer l42 HVTR
+ layer l43 NCM
+ layer l44 RPM
+ layer l45 NSM
+ layer l46 RDL
+ layer l47 VHVI
+ layer l48 LDNTM
+ layer l49 HVNTM
+ layer l50 PMM
+ layer l51 PNP
+ layer l52 CAP
+ layer l53 IND
+ layer l54 PWRES
+ layer l55 POLYRES
+ layer l56 DIFFRES
+ layer l57 DIODE
+ layer l58 POLYM
+ layer l59 COREID
+ layer l60 NWELLT
+ layer l61 PWELLT
+ layer l62 NWELLP
+ layer l63 POLYP
+ layer l64 PWELLP
+ layer l65 CFOMDROP
+ layer l66 CLI1MADD
+ layer l67 CNTMADD
+ layer l68 CP1MADD
+ layer l69 BOUND
+ layer l70 POLYT
+ calma NWELL  64 20
+ calma DNWELL 64 18
+ calma DIFF   65 20
+ calma TAP    65 44
+ calma LVTN  125 44
+ calma HVTP   78 44
+ calma HVI    75 20
+ calma TUNM   80 20
+ calma POLY   66 20
+ calma NPC    95 20
+ calma PSDM   94 20
+ calma NSDM   93 44
+ calma LICON1 66 44
+ calma LI1    67 20
+ calma LI1T   67 16
+ calma LI1P   67 5
+ calma MCON   67 44
+ calma MET1   68 20
+ calma MET1T  68 16
+ calma MET1P  68 5
+ calma VIA1   68 44
+ calma MET2   69 20
+ calma MET2T  69 16
+ calma MET2P  69 5
+ calma VIA2   69 44
+ calma MET3   70 20
+ calma MET3T  70 16
+ calma MET3P  70 5
+ calma VIA3   70 44
+ calma MET4   71 20
+ calma MET4T  71 16
+ calma MET4P  71 5
+ calma VIA4   71 44
+ calma MET5   72 20
+ calma MET5T  72 16
+ calma MET5P  72 5
+ calma PAD    76 20
+ calma PADT   76 16
+ calma PADP   76 5
+ calma AREAID 81 4
+ calma TEXT   83 44
+ calma HVTR   18 20
+ calma NCM    92 44
+ calma RPM    86 20
+ calma NSM    61 20
+ calma RDL    74 20
+ calma VHVI   74 21
+ calma LDNTM  11 44
+ calma HVNTM 125 20
+ calma PMM    85 44
+ calma PNP    82 44
+ calma CAP    82 64
+ calma IND    82 24
+ calma PWRES  64 13
+ calma POLYRES 66 13
+ calma DIFFRES 65 13
+ calma DIODE  81 23
+ calma POLYM  66 83
+ calma COREID 81 2
+ calma NWELLT  64 16
+ calma PWELLT 122 16
+ calma NWELLP  64 5
+ calma POLYP  66 5
+ calma PWELLP 64 59
+ calma CFOMDROP 22 22
+ calma CLI1MADD 115 43
+ calma CNTMADD  22 21
+ calma CP1MADD  33 43
+ calma BOUND  235 4
+ calma POLYT  66 16
+end
+ 
+mzrouter
+end
+
+drc
+end
+
+extract
+style default
+ planeorder p1 0
+ planeorder p2 1
+ planeorder p3 2
+ planeorder p4 3
+ planeorder p5 4
+ planeorder p6 5
+ planeorder p7 6
+ planeorder p8 7
+ planeorder p9 8
+ planeorder p10 9
+ planeorder p11 10
+ planeorder p12 11
+ planeorder p13 12
+ planeorder p14 13
+ planeorder p15 14
+ planeorder p16 15
+ planeorder p17 16
+ planeorder p18 17
+ planeorder p19 18
+ planeorder p20 19
+ planeorder p21 20
+ planeorder p22 21
+ planeorder p23 22
+ planeorder p24 23
+ planeorder p25 24
+ planeorder p26 25
+ planeorder p27 26
+ planeorder p28 27
+ planeorder p29 28
+ planeorder p30 29
+ planeorder p31 30
+ planeorder p32 31
+ planeorder p33 32
+ planeorder p34 33
+ planeorder p35 34
+ planeorder p36 35
+ planeorder p37 36
+ planeorder p38 37
+ planeorder p39 38
+ planeorder p40 39
+ planeorder p41 40
+ planeorder p42 41
+end
diff --git a/sky130/sky130osu.sh b/sky130/sky130osu.sh
new file mode 100644
index 0000000..4afd9bd
--- /dev/null
+++ b/sky130/sky130osu.sh
@@ -0,0 +1,93 @@
+#!/bin/tcsh
+#---------------------------------------------------------------
+# Shell script setting up all variables used by the qflow scripts
+# for this project
+#---------------------------------------------------------------
+
+# The LEF file containing standard cell macros
+
+#ifdef EF_FORMAT
+set leffile=STAGING_PATH/TECHNAME/libs.ref/lef/sky130_osu130/sky130_osu130.lef
+#else (!EF_FORMAT)
+set leffile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/lef/sky130_osu130.lef
+#endif (!EF_FORMAT)
+
+# The SPICE netlist containing subcell definitions for all the standard cells
+#ifdef EF_FORMAT
+set spicefile=STAGING_PATH/TECHNAME/libs.ref/spice/sky130_osu130/sky130_osu130.spice
+#else (!EF_FORMAT)
+set spicefile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/spice/sky130_osu130.spice
+#endif (!EF_FORMAT)
+
+# The liberty format file containing standard cell timing and function information
+#ifdef EF_FORMAT
+set libertyfile=STAGING_PATH/TECHNAME/libs.ref/lib/sky130_osu130/sky130_osu130.lib
+#else (!EF_FORMAT)
+set libertyfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/lib/sky130_osu130.lib
+#endif (!EF_FORMAT)
+
+# If there is another LEF file containing technology information
+# that is separate from the file containing standard cell macros,
+# set this.  Otherwise, leave it defined as an empty string.
+
+#ifdef METAL5
+#ifdef EF_FORMAT
+set techleffile=STAGING_PATH/TECHNAME/libs.ref/techLEF/sky130_osu130/sky130_osu130_tech.lef
+#else (!EF_FORMAT)
+set techleffile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/techLEF/sky130_osu130_tech.lef
+#endif (!EF_FORMAT)
+#else
+# NOTE:  There is no technology LEF file for the 3-metal stack!
+#endif
+
+# All cells below should be the lowest output drive strength value,
+# if the standard cell set has multiple cells with different drive
+# strengths.  Comment out any cells that do not exist.
+
+set bufcell=BUFX2		;# Minimum drive strength buffer cell
+set bufpin_in=A			;# Name of input port to buffer cell
+set bufpin_out=Y		;# Name of output port to buffer cell
+set clkbufcell=BUFX2		;# Minimum drive strength buffer cell
+set clkbufpin_in=A		;# Name of input port to buffer cell
+set clkbufpin_out=Y		;# Name of output port to buffer cell
+
+set fillcell=FILL		;# Spacer (filler) cell (prefix, if more than one)
+set decapcell=""		;# Decap (filler) cell (prefix, if more than one)
+set antennacell=""		;# Antenna (filler) cell (prefix, if more than one)
+set antennapin_in=""		;# Antenna cell input connection
+set bodytiecell=""		;# Body tie (filler) cell (prefix, if more than one)
+
+# yosys tries to eliminate use of these; depends on source .v
+set tiehi=""			;# Cell to connect to power, if one exists
+set tiehipin_out=""		;# Output pin name of tiehi cell, if it exists
+set tielo=""			;# Cell to connect to ground, if one exists
+set tielopin_out=""		;# Output pin name of tielo cell, if it exists
+
+set gndnet="vdd"		;# Name used for ground pins in standard cells
+set vddnet="vss"		;# Name used for power pins in standard cells
+
+set separator=""		;# Separator between gate names and drive strengths
+set techfile=STAGING_PATH/TECHNAME/MAGIC_CURRENT/TECHNAME.tech	    ;# magic techfile
+set magicrc=STAGING_PATH/TECHNAME/MAGIC_CURRENT/TECHNAME.magicrc    ;# magic startup script
+set magic_display="XR" 	;# magic display, defeat display query and OGL preference
+set netgen_setup=STAGING_PATH/TECHNAME/libs.tech/netgen/TECHNAME_setup.tcl	;# netgen setup file for LVS
+#ifdef EF_FORMAT
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/gds/sky130_osu130/sky130_osu130.gds	;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/verilog/sky130_osu130/sky130_osu130.v	;# Verilog models of standard cells
+#else (!EF_FORMAT)
+set gdsfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/gds/sky130_osu130.gds	;# GDS database of standard cells
+set verilogfile=STAGING_PATH/TECHNAME/libs.ref/sky130_osu130/verilog/sky130_osu130.v	;# Verilog models of standard cells
+#endif (!EF_FORMAT)
+
+# Set a conditional default in the project_vars.sh file for this process
+set postproc_options=""
+#ifdef METAL5
+# Normally one does not want to use the top metal for signal routing
+set route_layers = 5
+#else
+set route_layers = 3
+#endif
+set fill_ratios="100,0,0,0"
+set fanout_options="-l 100 -c 10"
+set addspacers_options="-stripe 1.6 40.0 PG"
+set xspice_options="-io_time=250p -time=50p -idelay=20p -odelay=50p -cload=250f"