diff --git a/sky130/sky130.tech b/sky130/sky130.tech
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+###
+###	Source file sky130.tech
+###	Process this file with the preproc.py macro processor
+###	Note that the tech name is always TECHNAME for
+###	magic;  this keeps compatibility between layouts
+###	for all process variants.
+###
+#----------------------------------------------------------
+# Copyright (c) 2020 R. Timothy Edwards
+# Revisions:  See below
+#
+# This file is an Open Source foundry process describing
+# the SkyWater S8 hybrid 0.18um / 0.13um fabrication
+# process.  The file may be distributed under the terms
+# of the (Apache 2.0(?)) license agreement.
+#
+#----------------------------------------------------------
+# This file is designed to be used with magic versions
+# 8.3.24 or newer.
+#----------------------------------------------------------
+tech
+  format 35
+  TECHNAME
+end
+
+version
+ version REVISION
+ description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
+end
+
+#----------------------------------------------------------
+# Status: 3/17/19: s8.tech created from xh018.tech
+#
+# Status: 3/20/19: Rev 0 (pre-alpha):
+# Work in progress.  Converted from original techfile to S8
+# with all sections updated with as much information as could
+# be immediately gleaned from the documentation.  Cifinput and
+# DRC sections have been checked against one standard cell
+# library.
+#
+# Status 5/5/20: Rev 1 (alpha):
+# Changed name from s8 to sky130
+#--------------------------------------------------------------
+
+#--------------------------------------------------------------
+# Supported device types
+#--------------------------------------------------------------
+# device name   magic ID layer  description
+#-------------------------------------------------------------
+# nshort	nfet		standard nFET
+# nshort	scnfet		standard nFET in standard cell**
+# nlowvt	nfetlvt		low Vt nFET
+# sonos_p/e	nsonos		SONOS nFET
+# pshort	pfet		standard pFET
+# pshort	scpfet		standard pFET in standard cell**
+# plowvt	pfetlvt		low Vt pFET
+# phighvt	pfethvt		high Vt pFET
+# ntvnative	---		native nFET
+# phv		mvpfet		thickox pFET
+# nhv		mvnfet		thickox nFET
+# nhvnative	mvnnfet		thickox native nFET
+# ndiode	ndiode		n+ diff diode
+# ndiode_h	mvndiode	thickox n+ diff diode
+# pdiode	pdiode		p+ diff diode
+# pdiode_h	mvpdiode	thickox p+ diff diode
+# ndiode_native	nndiode		diode with nndiff
+# ndiode_lvt	ndiodelvt	low Vt n+ diff diode
+# pdiode_lvt	pdiodelvt	low Vt p+ diff diode
+# pdiode_hvt	pdiodehvt	high Vt p+ diff diode
+# nwdiode	---		nwell diode
+# dnwdiode_psub	---		deep nwell diode to substrate
+# dnwdiode_pw	---		deep nwell diode to pwell
+# xcmimc1	mimcap		MiM cap 1st plate
+# xcmimc2	mimcap2		MiM cap 2nd plate
+# mrdn		rdn		n+ diff resistor
+# mrdn_hv	mvrdn		thickox n+ diff resistor
+# mrdp		rdp		p+ diff resistor
+# mrdp_hv	mvrdp		thickox p+ diff resistor
+# mrl1		rli		local interconnect resistor
+# mrp1		npres		n+ poly resistor
+# xhrpoly_*	ppres (*)	p+ poly resistor (300 Ohms/sq)
+# uhrpoly_*	xres (*)	p+ poly resistor (2k Ohms/sq)
+# xcnwvc	varactor	varactor (low Vt?)
+# xcnwvc2	varactorhvt	high Vt varactor
+# xchvnwc	mvvaractor	thickox varactor
+# xpwres	rpw		pwell resistor (in deep nwell)
+#
+# (*) Note that ppres may extract into some generic type
+# called "xhrpoly", but only specific sizes of xhrpoly are
+# allowed, and these are created from fixed layouts like the
+# types below.
+#
+# (**) nFET and pFET in standard cells are the same as devices
+# outside of the standard cell except for the DRC rule for
+# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
+#
+# To avoid creating a large number of types, a few ID layers are
+# used in conjunction with standard devices types:  "lvt" for
+# low threshold voltage, and "hvt" for high threshold voltage.
+# "dnwell" is used as an identifier layer where appropriate.
+# Layer HVI (thick oxide) is treated differently, and types
+# "mv*" are defined where thick oxide is required.
+#
+#-------------------------------------------------------------
+# The following devices are not extracted but are represented
+# only by script-generated subcells in the PDK.
+#-------------------------------------------------------------
+# nshortesd			ESD nFET
+# nhvesd			ESD thickox nFET
+# nhvnativeesd			ESD native nFET
+# phvesd			ESD thickox pFET
+# fnpass			flash nFET device
+# npnpar1x*			parasitic NPN
+# npn_1x1_2p0_hv		thickox gated parasitic NPN
+# pnppar			parasitic PNP
+# pnppar5x			parasitic PNP
+# xesd_ndiode_h_***		ESD n+ diode
+# xesd_pdiode_h_***		ESD p+ diode
+# reslocsub			local substrate island indicator
+# xcmvpp			Vpp cap
+# xcmvpp_2			Vpp cap
+# xcmvpp_*			Vpp cap
+# xcmvpp*			Vpp cap
+# balun				balun inductor
+# ind4				inductor
+# fuse				metal fuse device
+#--------------------------------------------------------------
+
+#-----------------------------------------------------
+# Tile planes
+#-----------------------------------------------------
+
+planes
+  dwell,dw
+  well,w
+  active,a
+  locali,li1,li
+  metal1,m1
+  metal2,m2
+  metal3,m3
+#ifdef METAL5
+#ifdef MIM
+  cap1,c1
+#endif (MIM)
+  metal4,m4
+#ifdef MIM
+  cap2,c2
+#endif (MIM)
+  metal5,m5
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+  metali,mi
+#endif
+  block,b
+  comment,c
+end
+
+#-----------------------------------------------------
+# Tile types
+#-----------------------------------------------------
+
+types
+# Deep nwell
+  dwell dnwell,dnw
+
+# Wells
+  well nwell,nw
+ -well pwell,pw
+ -well rpw,rpwell
+ -well obswell
+
+# Transistors
+  active nmos,ntransistor,nfet
+ -active scnmos,scntransistor,scnfet
+  active pmos,ptransistor,pfet
+ -active scpmos,scptransistor,scpfet
+ -active nnmos,nntransistor
+  active mvnmos,mvntransistor,mvnfet
+  active mvpmos,mvptransistor,mvpfet
+ -active mvnnmos,mvnntransistor,mvnnfet,nnfet
+ -active varactor,varact,var
+ -active mvvaractor,mvvaract,mvvar
+
+ -active pmoslvt,pfetlvt
+ -active pmoshvt,pfethvt
+ -active nmoslvt,nfetlvt
+ -active varactorhvt,varacthvt,varhvt
+ -active nsonos,sonos
+
+# Diffusions
+  active ndiff,ndiffusion,ndif
+  active pdiff,pdiffusion,pdif
+ -active mvndiff,mvndiffusion,mvndif
+ -active mvpdiff,mvpdiffusion,mvpdif
+  active ndiffc,ndcontact,ndc
+  active pdiffc,pdcontact,pdc
+ -active mvndiffc,mvndcontact,mvndc
+ -active mvpdiffc,mvpdcontact,mvpdc
+  active psubdiff,psubstratepdiff,ppdiff,ppd,psd
+  active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
+ -active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
+ -active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
+  active psubdiffcont,psubstratepcontact,psc
+  active nsubdiffcont,nsubstratencontact,nsc
+ -active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
+ -active mvnsubdiffcont,mvnsubstratencontact,mvnsc
+ -active obsactive
+ -active mvobsactive
+
+# Poly
+  active poly,p,polysilicon
+  active polycont,pc,pcontact,polycut,polyc
+  active xpolycontact,xpolyc,xpc
+
+# Resistors
+ -active npolyres,npres,mrp1
+ -active ppolyres,ppres,xhrpoly
+ -active xpolyres,xpres,xres,uhrpoly
+ -active ndiffres,rnd,rdn,rndiff
+ -active pdiffres,rpd,rdp,rpdiff
+ -active mvndiffres,mvrnd,mvrdn,mvrndiff
+ -active mvpdiffres,mvrpd,mvrdp,mvrpdiff
+ -active rmp
+
+# Diodes
+ -active pdiode,pdi
+ -active ndiode,ndi
+ -active nndiode,nndi
+ -active pdiodec,pdic
+ -active ndiodec,ndic
+ -active nndiodec,nndic
+ -active mvpdiode,mvpdi
+ -active mvndiode,mvndi
+ -active mvpdiodec,mvpdic
+ -active mvndiodec,mvndic
+ -active pdiodelvt,pdilvt
+ -active pdiodehvt,pdihvt
+ -active ndiodelvt,ndilvt
+ -active pdiodelvtc,pdilvtc
+ -active pdiodehvtc,pdihvtc
+ -active ndiodelvtc,ndilvtc
+
+# Local Interconnect 
+  locali locali,li1,li
+ -locali corelocali,coreli1,coreli
+ -locali rlocali,rli1,rli
+  locali viali,vial,lic,licon,m1c,v0
+ -locali obsli1,obsli
+ -locali obsli1c,obslic,obslicon
+
+# Metal 1
+  metal1 metal1,m1,met1
+ -metal1 rmetal1,rm1,rmet1
+  metal1 via1,m2contact,m2cut,m2c,via,v,v1
+ -metal1 obsm1
+ -metal1 padl
+
+# Metal 2
+  metal2 metal2,m2,met2
+ -metal2 rmetal2,rm2,rmet2
+  metal2 via2,m3contact,m3cut,m3c,v2
+ -metal2 obsm2
+
+# Metal 3
+  metal3 metal3,m3,met3
+ -metal3 rmetal3,rm3,rmet3
+ -metal3 obsm3
+#ifdef METAL5
+  metal3 via3,v3
+
+#ifdef MIM
+ -cap1 mimcap,mim,capm
+ -cap1 mimcapcontact,mimcapc,mimcc,capmc
+#endif
+
+# Metal 4
+  metal4 metal4,m4,met4
+ -metal4 rmetal4,rm4,rmet4
+ -metal4 obsm4
+  metal4 via4,v4
+
+#ifdef MIM
+ -cap2 mimcap2,mim2,capm2
+ -cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
+#endif
+
+# Metal 5
+  metal5 metal5,m5,met5
+ -metal5 rm5,rmetal5,rmet5
+ -metal5 obsm5
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+ -metal5 mrdlcontact,mrdlc
+ -metali metalrdl,mrdl,metrdl
+ -metali obsmrdl
+#endif (REDISTRIBUTION)
+
+# Miscellaneous
+ -block  glass
+ -block  fillblock
+ -comment comment
+ -comment obscomment
+
+end
+
+#-----------------------------------------------------
+# Magic contact types
+#-----------------------------------------------------
+
+contact
+  pc       poly       locali
+  ndc      ndiff      locali
+  pdc      pdiff      locali
+  nsc      nsd        locali
+  psc      psd        locali
+  ndic     ndiode     locali
+  ndilvtc  ndiodelvt  locali
+  nndic    nndiode    locali
+  pdic     pdiode     locali
+  pdilvtc  pdiodelvt  locali
+  pdihvtc  pdiodehvt  locali
+  xpc      xpc        locali
+
+  mvndc   mvndiff   locali
+  mvpdc   mvpdiff   locali
+  mvnsc   mvnsd     locali
+  mvpsc   mvpsd     locali
+  mvndic  mvndiode  locali
+  mvpdic  mvpdiode  locali
+
+  lic locali metal1
+  obslic obsli obsm1
+
+  via1   metal1 metal2
+  via2   metal2 metal3
+#ifdef METAL5
+  via3   metal3 metal4
+  via4   metal4 metal5
+#endif (METAL5)
+  stackable
+
+#ifdef METAL5
+#ifdef MIM
+  # MiM cap contacts are not stackable!
+  mimcc  mimcap metal4
+  mim2cc mimcap2 metal5
+#endif (MIM)
+
+  padl m1 m2 m3 m4 m5 glass
+#else
+  padl m1 m2 m3 glass
+#endif  (!METAL5)
+
+#ifdef REDISTRIBUTION
+  mrdlc metal5 mrdl
+#endif (REDISTRIBUTION)
+end
+
+#-----------------------------------------------------
+# Layer aliases
+#-----------------------------------------------------
+
+aliases
+
+  allwellplane     nwell
+  allnwell	   nwell,obswell
+
+  allnfets	   nfet,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
+  allpfets	   pfet,scpfet,mvpfet,pfethvt,pfetlvt
+  allfets	   allnfets,allpfets,varactor,mvvaractor,varhvt
+
+  allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
+  allnactive	   allnactivenonfet,allnfets
+  allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
+  allnactivetap	   *nsd,*mvnsd,var,varhvt,mvvar
+
+  allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
+  allpactive	   allpactivenonfet,allpfets
+  allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
+  allpactivetap    *psd,*mvpsd
+
+  allactivenonfet  allnactivenonfet,allpactivenonfet
+  allactive	   allactivenonfet,allfets
+
+  allactiveres	   ndiffres,pdiffres,mvndiffres,mvpdiffres
+
+  allndifflv       *ndif,*nsd,*ndiode,ndiffres,nfet,scnfet,nfetlvt,nsonos
+  allpdifflv       *pdif,*psd,*pdiode,pdiffres,pfet,scpfet,pfetlvt,pfethvt
+  alldifflv        allndifflv,allpdifflv
+  allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
+  allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
+  alldifflvnonfet  allndifflvnonfet,allpdifflvnonfet
+
+  allndiffmv       *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+  allpdiffmv       *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
+  alldiffmv        allndiffmv,allpdiffmv
+  allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+  allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
+  alldiffmvnontap  allndiffmvnontap,allpdiffmvnontap
+  allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
+  allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
+  alldiffmvnonfet  allndiffmvnonfet,allpdiffmvnonfet
+
+  alldiffnonfet	   alldifflvnonfet,alldiffmvnonfet
+  alldiff	   alldifflv,alldiffmv
+
+  allpolyres	   mrp1,xhrpoly,uhrpoly,rmp
+  allpolynonfet	   *poly,allpolyres,xpc
+  allpolynonres	   *poly,allfets,xpc
+
+  allpoly	   allpolynonfet,allfets
+  allpolynoncap	   *poly,xpc,allfets,allpolyres
+
+  allndiffcontlv   ndc,nsc,ndic,nndic,ndilvtc
+  allpdiffcontlv   pdc,psc,pdic,pdilvtc,pdihvtc
+  allndiffcontmv   mvndc,mvnsc,mvndic
+  allpdiffcontmv   mvpdc,mvpsc,mvpdic
+  allndiffcont	   allndiffcontlv,allndiffcontmv
+  allpdiffcont	   allpdiffcontlv,allpdiffcontmv
+  alldiffcontlv	   allndiffcontlv,allpdiffcontlv
+  alldiffcontmv	   allndiffcontmv,allpdiffcontmv
+  alldiffcont	   alldiffcontlv,alldiffcontmv
+
+  allcont	alldiffcont,pc
+
+  allres	allpolyres,allactiveres
+
+  allli		*locali,coreli,rli
+  allm1		*m1,rm1
+  allm2		*m2,rm2
+  allm3		*m3,rm3
+#ifdef METAL5
+  allm4	   	*m4,rm4
+  allm5	   	*m5,rm5
+#endif (METAL5)
+
+  allpad	padl
+
+  psub		pwell
+  
+end
+
+#-----------------------------------------------------
+# Layer drawing styles
+#-----------------------------------------------------
+
+styles
+ styletype mos
+  dnwell    cwell
+  nwell     nwell
+  pwell	    pwell
+  rpwell    pwell 	ptransistor_stripes
+  ndiff     ndiffusion
+  pdiff     pdiffusion
+  nsd       ndiff_in_nwell
+  psd       pdiff_in_pwell
+  nfet      ntransistor    ntransistor_stripes
+  scnfet    ntransistor    ntransistor_stripes
+  pfet      ptransistor    ptransistor_stripes
+  scpfet    ptransistor    ptransistor_stripes
+  var       polysilicon    ndiff_in_nwell
+  ndc       ndiffusion     metal1  contact_X'es
+  pdc       pdiffusion     metal1  contact_X'es
+  nsc       ndiff_in_nwell metal1  contact_X'es
+  psc       pdiff_in_pwell metal1  contact_X'es
+
+  pfetlvt   ptransistor	ptransistor_stripes implant1
+  pfethvt   ptransistor ptransistor_stripes implant2
+  nfetlvt   ntransistor ntransistor_stripes implant1
+  nsonos    ntransistor implant3
+  varhvt    polysilicon ndiff_in_nwell implant2
+
+  mvndiff   ndiffusion     hvndiff_mask
+  mvpdiff   pdiffusion     hvpdiff_mask
+  mvnsd     ndiff_in_nwell hvndiff_mask
+  mvpsd     pdiff_in_pwell hvpdiff_mask
+  mvnfet    ntransistor    ntransistor_stripes hvndiff_mask
+  mvnnfet   ntransistor    ndiff_in_nwell hvndiff_mask
+  mvpfet    ptransistor    ptransistor_stripes
+  mvvar     polysilicon    ndiff_in_nwell hvndiff_mask
+  mvndc     ndiffusion     metal1  contact_X'es hvndiff_mask
+  mvpdc     pdiffusion     metal1  contact_X'es hvpdiff_mask
+  mvnsc     ndiff_in_nwell metal1  contact_X'es hvndiff_mask
+  mvpsc     pdiff_in_pwell metal1  contact_X'es hvpdiff_mask
+
+  poly      polysilicon 
+  pc        polysilicon    metal1  contact_X'es
+  npolyres  polysilicon    silicide_block nselect2
+  ppolyres  polysilicon    silicide_block pselect2
+  xpc	    polysilicon	   pselect2  metal1  contact_X'es
+  rmp	    polysilicon	   poly_resist_stripes
+
+  pdiode    pdiffusion     pselect2
+  ndiode    ndiffusion     nselect2
+  pdiodec   pdiffusion     pselect2 metal1 contact_X'es
+  ndiodec   ndiffusion     nselect2 metal1 contact_X'es
+
+  nndiode   ndiffusion  nselect2 implant3
+  ndiodelvt ndiffusion	nselect2 implant1
+  pdiodelvt pdiffusion  pselect2 implant1
+  pdiodehvt pdiffusion  pselect2 implant2
+  pdilvtc   pdiffusion  pselect2 implant1 metal1 contact_X'es
+  pdihvtc   pdiffusion  pselect2 implant2 metal1 contact_X'es
+  ndilvtc   ndiffusion  nselect2 implant1 metal1 contact_X'es
+
+  mvpdiode    pdiffusion     pselect2 hvpdiff_mask
+  mvndiode    ndiffusion     nselect2 hvndiff_mask
+  mvpdiodec   pdiffusion     pselect2 metal1 contact_X'es hvpdiff_mask
+  mvndiodec   ndiffusion     nselect2 metal1 contact_X'es hvndiff_mask
+  nndiodec    ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
+
+  locali    metal1
+  coreli    metal1
+  rli       metal1         poly_resist_stripes
+  lic	    metal1	   metal2 via1arrow
+  obsli     metal1
+  obslic    metal1	   metal2 via1arrow
+
+  metal1    metal2
+  rm1       metal2         poly_resist_stripes
+  obsm1     metal2
+  m2c       metal2         metal3  via2arrow
+  metal2    metal3
+  rm2       metal3         poly_resist_stripes
+  obsm2     metal3
+  m3c       metal3         metal4  via3alt
+  metal3    metal4
+  rm3       metal4         poly_resist_stripes
+  obsm3     metal4
+#ifdef METAL5
+#ifdef MIM
+  mimcap    metal3         mems
+  mimcc     metal3         contact_X'es mems
+  mimcap2   metal4         mems
+  mim2cc    metal4         contact_X'es mems
+#endif (MIM)
+  via3      metal4         metal5  via4
+  metal4    metal5
+  rm4       metal5         poly_resist_stripes
+  obsm4     metal5
+  via4      metal5         metal6  via5
+  metal5    metal6
+  rm5       metal6         poly_resist_stripes
+  obsm5     metal6
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+  mrdlc	    metal6  metal7  via6
+  metalrdl  metal7
+  obsmrdl   metal7
+#endif (REDISTRIBUTION)
+
+  glass	    overglass
+  mrp1      poly_resist    poly_resist_stripes
+  xhrpoly   poly_resist    silicide_block
+  uhrpoly   poly_resist
+  ndiffres  ndiffusion	   ndop_stripes
+  pdiffres  pdiffusion	   pdop_stripes
+  mvndiffres  ndiffusion hvndiff_mask   ndop_stripes
+  mvpdiffres  pdiffusion hvpdiff_mask   pdop_stripes
+  comment   comment
+  error_p   error_waffle
+  error_s   error_waffle
+  error_ps  error_waffle
+  fillblock cwell
+
+  obswell   cwell
+  obsactive implant4
+
+#ifndef METAL5
+  padl      metal4 via4 overglass
+#else
+  padl      metal6 via6 overglass
+#endif
+
+  magnet    substrate_field_implant
+  rotate    via3alt
+  fence     via5
+end
+
+#-----------------------------------------------------
+# Special paint/erase rules
+#-----------------------------------------------------
+
+compose
+  compose  nfet  poly  ndiff
+  compose  pfet  poly  pdiff
+  compose  var   poly  nsd
+
+  compose  mvnfet  poly  mvndiff
+  compose  mvpfet  poly  mvpdiff
+  compose  mvvar   poly  mvnsd
+  
+  paint  ndc     nwell  pdc
+  paint  nfet    nwell  pfet
+  paint  scnfet  nwell  scpfet
+  paint  ndiff   nwell  pdiff
+  paint  psd     nwell  nsd
+  paint  psc     nwell  nsc
+
+  paint  pdc     pwell  ndc
+  paint  pfet    pwell  nfet
+  paint  scpfet  pwell  scnfet
+  paint  pdiff   pwell  ndiff
+  paint  nsd     pwell  psd
+  paint  nsc     pwell  psc
+
+  paint  pdc	 coreli pdc
+  paint  ndc	 coreli ndc
+  paint  pc	 coreli pc
+  paint  nsc 	 coreli pc
+  paint  psc 	 coreli pc
+  paint  viali 	 coreli viali
+
+  paint  coreli  pdc    pdc
+  paint  coreli  ndc    ndc
+  paint  coreli  pc     pc
+  paint  coreli  nsc    nsc
+  paint  coreli  psc    psc
+  paint  coreli  viali  viali
+
+#ifdef METAL5
+  paint  m4      obsm4  m4
+  paint  m5      obsm5  m5
+#endif (METAL5)
+end
+
+#-----------------------------------------------------
+# Electrical connectivity
+#-----------------------------------------------------
+
+connect
+  *nwell,*nsd,*mvnsd,dnwell *nwell,*nsd,*mvnsd,dnwell
+  pwell,*psd,*mvpsd  pwell,*psd,*mvpsd
+  *li,coreli	*li,coreli
+  *m1	*m1
+  *m2	*m2
+  *m3	*m3
+#ifdef METAL5
+  *m4	*m4
+  *m5	*m5
+#ifdef MIM
+  *mimcap     *mimcap
+  *mimcap2    *mimcap2
+#endif (MIM)
+#endif (METAL5)
+   allnactivenonfet	allnactivenonfet
+   allpactivenonfet	allpactivenonfet
+  *poly,xpc,allfets	*poly,xpc,allfets
+#ifdef REDISTRIBUTION
+  # RDL connects to m5 (i.e., padl) through glass cut
+  *mrdl			*mrdl
+  glass			metrdl
+#endif (REDISTRIBUTION)
+end
+
+#-----------------------------------------------------
+# CIF/GDS output layer definitions
+#-----------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+
+cifoutput
+
+#----------------------------------------------------------------
+style gdsii
+# NOTE: This section is used for actual GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Create a temp layer from the cell bounding box for use in
+# generating ID layers.  Note that "boundary", unlike "bbox",
+# requires the FIXED_BBOX property (abutment box) in the cell.
+#----------------------------------------------------------------
+ templayer CELLBOUND
+	boundary
+
+#----------------------------------------------------------------
+# BOUND
+#----------------------------------------------------------------
+ layer 	BOUND CELLBOUND
+	calma 235 4
+
+# Create a boundary outside of an abutment box, so that layers
+# can be made to stretch to the abutment box edges.  First strink
+# so that any box that would be so small as to interact with
+# itself will be removed.
+
+ templayer CELLRING CELLBOUND
+	shrink 345
+	grow 545
+	and-not CELLBOUND
+
+#----------------------------------------------------------------
+# DNWELL
+#----------------------------------------------------------------
+
+ layer DNWELL	dnwell
+	calma	64 18
+
+ layer PWRES    rpw
+	and	dnwell
+	calma	64 13
+
+#----------------------------------------------------------------
+# NWELL
+#----------------------------------------------------------------
+
+ layer NWELL 	allnwell
+	bloat-all rpw dnwell
+	and-not rpw,pwell
+ 	calma 	64 20
+
+ layer WELLTXT
+ 	labels allnwell noport
+	calma 64 16
+
+ layer WELLPIN
+ 	labels allnwell port
+	calma 64 5
+
+#----------------------------------------------------------------
+# SUB (text/port only)
+#----------------------------------------------------------------
+
+ layer SUBTXT
+ 	labels pwell noport
+	calma 122 16
+
+ layer SUBPIN
+ 	labels pwell port
+	calma 64 59
+
+#----------------------------------------------------------------
+# DIFF
+#----------------------------------------------------------------
+
+ layer DIFF 	allnactivenontap,allpactivenontap,allactiveres
+ 	labels 	allnactivenontap,allpactivenontap
+ 	calma 	65 20
+
+#----------------------------------------------------------------
+# TAP
+#----------------------------------------------------------------
+
+ layer TAP 	allnactivetap,allpactivetap
+ 	labels 	allnactivetap,allpactivetap
+ 	calma 	65 44
+
+#----------------------------------------------------------------
+# PPLUS, NPLUS (PSDM, NSDM)
+#----------------------------------------------------------------
+
+ templayer basePPLUS pdiffres,mvpdiffres
+	grow	15
+	or	xhrpoly,uhrpoly,xpc
+	grow	110
+	bloat-or allpactivetap * 125 allnactivenontap 0
+	bloat-or allpactivenontap * 125 allnactivetap 0
+	bridge	380 380
+
+ templayer extendPPLUS  basePPLUS,CELLRING
+	grow	185
+	shrink	185
+	and-not	CELLRING
+
+ layer PPLUS basePPLUS,extendPPLUS 
+	close   265000
+	calma	94 20
+
+ templayer baseNPLUS ndiffres,mvndiffres
+ 	grow	125
+	bloat-or allnactivetap * 125 allpactivenontap 0
+	bloat-or allnactivenontap * 125 allpactivetap 0
+	bridge	380 380
+
+ templayer extendNPLUS  baseNPLUS,CELLRING
+ 	grow	185
+ 	shrink	185
+	and-not	CELLRING
+
+ layer NPLUS baseNPLUS,extendNPLUS
+ 	close   265000
+ 	calma	93 44
+
+#----------------------------------------------------------------
+# LVTN
+#----------------------------------------------------------------
+
+ layer LVTN  pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
+        grow 180
+	bridge	380 380
+	grow	185
+	shrink	185
+	close  265000
+	calma 125 44
+
+#----------------------------------------------------------------
+# HVTP
+#----------------------------------------------------------------
+
+ layer HVTP pfethvt,varhvt,*pdiodehvt
+        grow 180
+	bridge	380 380
+	grow	185
+	shrink	185
+	close 265000
+	calma 78 44
+
+#----------------------------------------------------------------
+# SONOS
+#----------------------------------------------------------------
+
+ layer SONOS nsonos
+	grow 100
+	grow-min 410
+	bridge 500 410
+	grow 250
+	shrink 250
+	calma 80 20
+
+#----------------------------------------------------------------
+# SONOS requires COREID around area (areaid.ce).  Also, the
+# coreli layer indicates a cell needing COREID.
+#----------------------------------------------------------------
+
+ layer COREID
+	bloat-all nsonos,coreli CELLBOUND
+	calma 81 2
+
+#----------------------------------------------------------------
+# STDCELL applies to all cells containing scnfet or scpfet.
+#----------------------------------------------------------------
+
+ layer STDCELL scnfet
+	bloat-all scpfet,scnfet CELLBOUND
+	calma 81 4
+
+#----------------------------------------------------------------
+# RPM
+#----------------------------------------------------------------
+
+ layer RPM
+	bloat-all xhrpoly xpc
+	grow 200
+	grow-min 1270
+	grow 420
+	shrink 420
+	calma 86 20
+
+#----------------------------------------------------------------
+# URPM (2kOhms/sq. poly implant)
+#----------------------------------------------------------------
+
+ layer URPM
+	bloat-all uhrpoly xpc
+	grow 200
+	grow-min 1270
+	grow 420
+	shrink 420
+	calma 79 20
+
+#----------------------------------------------------------------
+# LDNTM (Tip implant for SONOS FETs)
+#----------------------------------------------------------------
+
+ layer LDNTM
+	bloat-all nsonos *ndiff
+	grow 185
+ 	grow 	345
+ 	shrink 	345
+	calma 11 44
+
+#----------------------------------------------------------------
+# HVNTM (Tip implant for MV ndiff devices)
+#----------------------------------------------------------------
+
+ templayer hvntm_block *mvpsd
+	grow 185
+
+ layer HVNTM
+	bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+	bloat-all mvvaractor *mvnsd
+	and-not hvntm_block
+        grow 185
+ 	grow 	345
+ 	shrink 	345
+	calma 125 20
+
+#----------------------------------------------------------------
+# POLY
+#----------------------------------------------------------------
+
+ layer POLY 	allpoly
+ 	calma 	66 20
+
+ layer POLYTXT
+	labels  allpoly noport
+	calma	66 16
+
+ layer POLYPIN
+	labels  allpoly port
+	calma	66 5
+
+#----------------------------------------------------------------
+# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
+#----------------------------------------------------------------
+
+ templayer baseTHKOX 	*mvpsd
+	grow-min 470
+	or alldiffmv,mvvar
+	grow	185
+        bloat-all alldiffmv nwell
+	grow-min 600
+	bridge	700 600
+
+ templayer extendTHKOX	baseTHKOX,CELLRING
+ 	grow 	345
+ 	shrink 	345
+	and-not	CELLRING
+
+ layer THKOX	baseTHKOX,extendTHKOX
+ 	calma 	75 20
+
+#----------------------------------------------------------------
+# CONT (LICON)
+#----------------------------------------------------------------
+
+ layer CONT allcont
+ 	squares-grid 0 170 170
+ 	calma	66 44
+
+ # Contact for pres is different than other LICON contacts
+ # See rules LICON 1b, 1c (width/length) and 2b (spacing)
+ templayer xpc_horiz xpc
+	shrink 1007
+	grow 1007
+
+ layer CONT xpc
+	and-not xpc_horiz
+	# Force long edge vertical for contacts narrower than 2um
+	# Minimum space is 350 but 520 satisfies no. of contacts rule
+ 	slots 80 190 520 80 2000 350
+ 	calma	66 44
+
+ layer CONT xpc
+	and xpc_horiz
+	# Force long edge vertical for contacts wider than 2um
+	# Minimum space is 350 but 520 satisfies no. of contacts rule
+ 	slots 80 2000 350 80 190 520
+ 	calma	66 44
+
+#----------------------------------------------------------------
+# NPC (Nitride poly cut)
+# surrounds CONT (LICON) on poly only (i.e., pc)
+#----------------------------------------------------------------
+
+ layer NPC pc
+ 	squares-grid 0 170 170
+	grow 100
+	bridge 270 270
+	grow 130
+	shrink 130
+	calma  95 20
+
+ # NPC is also generated on xhrpoly and uhrpoly resistors
+
+ layer NPC xpc,xhrpoly,uhrpoly
+        # xpc surrounds precision_resistor by 0.095um
+	grow 95
+	grow 130
+	shrink 130
+	calma  95 20
+
+#----------------------------------------------------------------
+# Device markers
+#----------------------------------------------------------------
+
+ layer DIFFRES rdn,mvrdn,rdp,mvrdp
+	calma 65 13
+
+ layer POLYRES mrp1
+	calma 66 13
+
+ # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
+ layer POLYSHORT rmp
+	calma 66 15
+
+ # POLYRES extends to edge of contact cut
+ layer POLYRES xhrpoly,uhrpoly
+	grow 60
+	and xpc
+	or xhrpoly,uhrpoly
+	calma 66 13
+
+ layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
+        # To be done:  Expand to include anode, cathode, and guard ring
+	calma 81 23
+
+#----------------------------------------------------------------
+# LI
+#----------------------------------------------------------------
+ layer LI allli
+	calma 67 20
+
+ layer LITXT
+ 	labels *locali,coreli noport
+	calma 67 16
+
+ layer LIPIN
+ 	labels *locali,coreli port
+	calma 67 5
+
+ layer LIRES rli
+	labels rli
+	calma 67 13
+
+#----------------------------------------------------------------
+# MCON
+#----------------------------------------------------------------
+ layer MCON lic
+ 	squares-grid 0 170 190
+ 	calma 	67 44
+
+#----------------------------------------------------------------
+# MET1
+#----------------------------------------------------------------
+ layer MET1 	allm1
+ 	calma 	68 20
+
+ layer MET1TXT
+	labels	allm1 noport
+	calma 	68 16
+
+ layer MET1PIN
+	labels	allm1 port
+	calma 	68 5
+
+ layer MET1RES rm1
+	labels rm1
+	calma 68 13
+
+#----------------------------------------------------------------
+# VIA1
+#----------------------------------------------------------------
+ layer VIA1 	via1
+ 	squares-grid 55 150 170
+ 	calma 	68 44
+
+#----------------------------------------------------------------
+# MET2
+#----------------------------------------------------------------
+ layer MET2 	allm2
+ 	calma 	69 20
+
+ layer MET2TXT
+	labels	allm2 noport
+	calma	69 16
+
+ layer MET2PIN
+	labels	allm2 port
+	calma	69 5
+
+ layer MET2RES rm2
+	labels rm2
+	calma 69 13
+
+#----------------------------------------------------------------
+# VIA2
+#----------------------------------------------------------------
+ layer VIA2 	via2
+ 	squares-grid 40 200 200
+ 	calma 	69 44
+
+#----------------------------------------------------------------
+# MET3
+#----------------------------------------------------------------
+ layer MET3 	allm3
+ 	calma 	70 20
+
+ layer MET3TXT
+ 	labels 	allm3 noport
+	calma	70 16 
+
+ layer MET3PIN
+	labels	allm3 port
+	calma	70 5
+
+ layer MET3RES rm3
+	labels rm3
+	calma 70 13
+
+#ifdef METAL5
+#----------------------------------------------------------------
+# VIA3
+#----------------------------------------------------------------
+ layer VIA3	via3
+#ifdef MIM
+	or mimcc
+#endif (MIM)
+ 	squares-grid 60 200 200
+ 	calma 	70 44
+
+#----------------------------------------------------------------
+# MET4
+#----------------------------------------------------------------
+ layer MET4 	allm4
+ 	calma 	71 20
+
+ layer MET4TXT
+	labels	allm4 noport
+	calma	71 16
+
+ layer MET4PIN
+	labels	allm4 port
+	calma	71 5
+
+ layer MET4RES rm4
+	labels rm4
+	calma 71 13
+
+#----------------------------------------------------------------
+# VIA4
+#----------------------------------------------------------------
+ layer VIA4	via4
+#ifdef MIM
+	or mim2cc
+#endif (MIM)
+ 	squares-grid 190 800 800
+ 	calma 	71 44
+
+#----------------------------------------------------------------
+# MET5
+#----------------------------------------------------------------
+ layer MET5 	allm5
+ 	calma 	72 20
+
+ layer MET5TXT
+	labels	allm5 noport
+	calma	72 16
+
+ layer MET5PIN
+	labels	allm5 port
+	calma	72 5
+
+ layer MET5RES rm5
+	labels rm5
+	calma 72 13
+
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+#----------------------------------------------------------------
+# RDL
+#----------------------------------------------------------------
+  layer RDL	*metrdl
+	calma   74 20
+
+  layer RDLTXT
+	labels	*metrdl noport
+	calma	74 16
+
+  layer RDLPIN
+	labels  *metrdl port
+	calma	74 5
+
+#endif REDISTRIBUTION
+
+#----------------------------------------------------------------
+# GLASS
+#----------------------------------------------------------------
+ layer GLASS 	glass
+ 	calma 	76 20
+
+#ifdef MIM
+#----------------------------------------------------------------
+# CAPM
+#----------------------------------------------------------------
+ layer CAPM 	*mimcap
+ 	labels 	mimcap
+ 	calma 	89 44
+
+ layer CAPM2 	*mimcap2
+ 	labels 	mimcap2
+ 	calma 	97 44
+#endif (MIM)
+
+#----------------------------------------------------------------
+# Chip top level marker for DRC latchup rules to check 15um
+# distance to taps (otherwise 6um is used)
+#----------------------------------------------------------------
+
+ layer LOWTAPDENSITY
+	bbox top
+	# Clear 200um for pads + 50um for required high tap density
+	# in critical area.
+	shrink 250000
+	calma	81 14
+
+#----------------------------------------------------------------
+# FILLBLOCK
+#----------------------------------------------------------------
+ layer FILLOBSM1 fillblock
+ 	calma 	62 24
+
+ layer FILLOBSM2 fillblock
+ 	calma 	105 52
+
+ layer FILLOBSM3 fillblock
+ 	calma 	107 24
+
+ layer FILLOBSM4 fillblock
+ 	calma 	112 4
+
+ render	DNWELL 	cwell       -0.1    0.1
+ render	NWELL	nwell        0.0    0.2062
+ render DIFF	ndiffusion   0.2062 0.12
+ render TAP	pdiffusion   0.2062 0.12
+ render POLY	polysilicon  0.3262 0.18
+ render CONT	via          0.5062 0.43
+ render LI	metal1       0.9361 0.10
+ render MCON	via          1.0361 0.34
+ render MET1	metal2       1.3761 0.36
+ render VIA1	via          1.7361 0.27
+ render MET2	metal3       2.0061 0.36
+ render VIA2	via          2.3661 0.42
+ render MET3	metal4       2.7861 0.845
+#ifdef METAL5
+ render VIA3	via          3.6311 0.39
+ render MET4	metal5       4.0211 0.845
+ render VIA4	via          4.8661 0.505
+ render MET5	metal6       5.3711 1.26
+ render CAPM	metal8       2.4661 0.2
+ render CAPM2	metal9       3.7311 0.2
+#ifdef REDISTRIBUTION
+ render RDL	metal7      11.8834 4.0
+#endif (!REDISTRIBUTION)
+#endif (!METAL5)
+
+#----------------------------------------------------------------
+style drc
+#----------------------------------------------------------------
+# NOTE:  This style is used for DRC only, not for GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+
+ # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
+ templayer dnwell_shrink dnwell
+ shrink 1030
+
+ templayer nwell_missing dnwell
+ grow 400
+ and-not dnwell_shrink
+ and-not nwell
+
+ # SONOS nFET devices must be in deep nwell
+ templayer dnwell_missing nsonos
+ and-not dnwell
+
+ # Define MiM cap bottom plate for spacing rule
+ templayer mim_bottom
+ bloat-all *mimcap *metal3
+
+ # Define MiM2 cap bottom plate for spacing rule
+ templayer mim2_bottom
+ bloat-all *mimcap2 *metal4
+
+ # Note that metal fill is performed by the foundry and so is not
+ # an option for a cifoutput style.
+
+ # Check latchup rule (15um minimum from tap LICON center to any
+ # non-tap diffusion.  Note that to count as a tap, the diffusion
+ # must be contacted to LI
+
+ templayer ptap_reach psc,mvpsc
+ and-not dnwell
+ # grow total is 15um.  grow in 0.84um increments to ensure that
+ # no nwell ring is crossed
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 635
+ and-not nwell,dnwell
+
+ templayer ptap_missing *ndiff,*mvndiff
+ and-not dnwell
+ and-not ptap_reach
+
+ templayer ntap_reach nsc,mvnsc
+ # grow total is 15um.  grow in 1.27um increments to ensure that
+ # no nwell ring is crossed.  There is no difference between
+ # ntaps in and out of deep nwell.
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 945
+ and nwell
+ 
+ templayer ntap_missing *pdiff,*mvpdiff
+ and-not dnwell
+ and-not ntap_reach
+
+ templayer dptap_reach psc,mvpsc
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 635
+ and-not nwell
+ and dnwell
+
+ templayer dptap_missing *ndiff,*mvndiff
+ and dnwell
+ and-not dptap_reach
+
+ templayer m1_small_hole *m1
+ close   140000
+
+ templayer m1_hole_empty m1_small_hole
+ and-not *m1
+
+ templayer m2_small_hole *m2
+ close   140000
+
+ templayer m2_hole_empty m2_small_hole
+ and-not *m2
+
+#ifdef EXPERIMENTAL
+#----------------------------------------------------------------
+style paint
+#----------------------------------------------------------------
+# NOTE:  This style is used for database manipulations only via
+# the "cif paint" command.
+#----------------------------------------------------------------
+
+ scalefactor 10  nanometers
+
+ templayer m1grow *m1
+    grow 290
+
+ # layer listrap:  Use the following set of commands to strap local
+ # interconnect wires with metal1 (inside the cursor box) to satisfy
+ # the maximum aspect ratio rule for local interconnect:
+ #
+ #    tech unlock *
+ #    cif ostyle paint
+ #    cif paint m1strap comment
+ #    cif paint m1strap m1
+ #    cif paint listrap licon
+ #    erase comment
+
+ templayer m1strap *li
+    and-not m1grow
+    grow 30
+
+ templayer listrap comment
+    slots 30 170 170 60
+
+#endif (EXPERIMENTAL)
+
+end
+
+#-----------------------------------------------------------------------
+cifinput
+#-----------------------------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+#-----------------------------------------------------------------------
+
+style  vendorimport
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+#ifndef MIM
+ ignore CAPM
+ ignore CAPM2
+#endif (!MIM)
+#ifndef METAL5
+ ignore MET4,VIA3
+ ignore MET5,VIA4
+#endif
+ ignore NPC
+ ignore SEALID
+ ignore NPNID
+ ignore PNPID
+ ignore CAPID
+ ignore LDNTM
+ ignore HVNTM
+ ignore POLYMOD
+ ignore LOWTAPDENSITY
+
+ layer nwell NWELL,WELLTXT,WELLPIN
+ labels NWELL
+ labels WELLTXT text
+ labels WELLPIN port
+
+ layer pwell SUBTXT,SUBPIN
+ labels SUBTXT text
+ labels SUBPIN port
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ layer rpw PWRES
+ and DNWELL
+ labels PWRES
+
+ templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and-not THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+ labels TAPPIN port
+
+ layer ndiff ndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvndiff mvndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+ labels DIFF
+
+ layer ndiodelvt DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NPLUS
+ and-not THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer ndiffres DIFFRES
+ and NPLUS
+ and-not THKOX
+ labels DIFF
+
+ templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and-not DIODE
+ and-not THKOX
+ and PPLUS
+ copyup pdifcheck
+ labels DIFF 
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiff pdiffarea
+
+ layer mvndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ labels DIFF
+
+ layer nndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NPLUS
+ and THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer mvndiffres DIFFRES
+ and NPLUS
+ and THKOX
+ labels DIFF
+
+ templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and THKOX
+ and-not DIODE
+ and-not DIFFRES
+ and PPLUS
+ copyup mvpdifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiff mvpdiffarea
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodelvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodehvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PPLUS
+ and-not THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff, regardless of the presence of a well.
+
+ templayer pfetarea DIFF
+ and-not NPLUS
+ and-not THKOX
+ and POLY
+
+ layer pfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and-not STDCELL
+ labels DIFF
+
+ layer scpfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and STDCELL
+ labels DIFF
+
+ layer pfetlvt pfetarea
+ and LVTN
+ labels DIFF
+
+ layer pfethvt pfetarea
+ and HVTP
+ labels DIFF
+
+ # Always force nwell under pfet (nwell encloses pdiff by 0.18)
+ layer nwell pfetarea
+ grow 180
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PPLUS
+ and THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF
+ and-not NPLUS
+ and THKOX
+ and POLY
+
+ layer mvpfet mvpfetarea
+ labels DIFF
+
+ layer pdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not DIODE
+ and-not DIFFRES
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and-not THKOX
+ labels DIFF
+
+ layer nfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and-not STDCELL
+ labels DIFF
+
+ layer scnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and STDCELL
+ labels DIFF
+
+ layer nfetlvt DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and-not SONOS
+ labels DIFF
+
+ layer nsonos DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and SONOS
+ labels DIFF
+
+ templayer nsdarea DIFF
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ copyup nsubcheck
+
+ layer nsd nsdarea
+ labels DIFF
+
+ layer nsd TAP,TAPPIN
+ and NPLUS
+ labels TAP
+ labels TAPPIN port
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels DIFF
+
+ layer psd TAP,TAPPIN
+ and PPLUS
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvpfetexpand
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and THKOX
+ and-not mvrdpioedge
+ labels DIFF
+
+ layer mvnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not LVTN
+ and THKOX
+ labels DIFF
+
+ layer mvnnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and LVTN
+ and THKOX
+ labels DIFF
+
+ templayer mvnsdarea DIFF
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and THKOX
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels DIFF
+
+ layer mvnsd TAP,TAPPIN
+ and NPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ layer mvpsd TAP,TAPPIN
+ and PPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and nsdexpand
+
+ layer mvpsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvnsdexpand
+
+ templayer hresarea POLY
+ and RPM
+ grow 3000
+
+ templayer uresarea POLY
+ and URPM
+ grow 3000
+
+ templayer diffresarea DIFFRES
+ and-not THKOX
+ grow 3000
+
+ templayer mvdiffresarea DIFFRES
+ and THKOX
+ grow 3000
+
+ templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
+
+ layer pfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and-not STDCELL
+
+ layer scpfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and STDCELL
+
+ templayer xpolyterm RPM,URPM
+ and POLY
+ and-not POLYRES
+ # add back the 0.06um contact surround in the direction of the resistor
+ grow 60
+ and POLY
+
+ layer xpc xpolyterm
+
+ templayer polyarea POLY
+ and-not POLYRES
+ and-not POLYSHORT
+ and-not DIFF
+ and-not RPM
+ and-not URPM
+ copyup polycheck
+
+ layer poly polyarea,POLYTXT,POLYPIN
+ labels POLY
+ labels POLYTXT text
+ labels POLYPIN port
+
+ # Copy (non-resistor) poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer mrp1 POLY
+ and POLYRES
+ and-not RPM
+ and-not URPM
+ labels POLY
+
+ layer rmp POLY
+ and POLYSHORT
+ labels POLY
+
+ layer xhrpoly POLY
+ and POLYRES
+ and RPM
+ and-not URPM
+ and PPLUS
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ layer uhrpoly POLY
+ and POLYRES
+ and URPM
+ and-not RPM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ templayer ndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and-not THKOX
+
+ layer ndc ndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndcbase
+ labels CONT
+
+ templayer nscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer nsc nscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nscbase
+ labels CONT
+
+ templayer pdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer pdc pdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcbase
+ labels CONT
+
+ templayer pdcnowell CONT
+ and DIFF
+ and PPLUS
+ and pfetexpand
+ and LI
+ and-not THKOX
+
+ layer pdc pdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcnowell
+ labels CONT
+
+ templayer pscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not pfetexpand
+ and LI
+ and-not THKOX
+
+ layer psc pscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pscbase
+ labels CONT
+
+ templayer pcbase CONT
+ and POLY
+ and-not DIFF
+ and-not RPM,URPM
+ and LI
+
+ layer pc pcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pcbase
+ labels CONT
+
+ templayer ndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+
+ layer ndic ndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndicbase
+ labels CONT
+
+ templayer ndilvtcbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+
+ layer ndilvtc ndilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndilvtcbase
+ labels CONT
+
+ templayer pdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+
+ layer pdic pdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdicbase
+ labels CONT
+
+ templayer pdilvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+
+ layer pdilvtc pdilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdilvtcbase
+ labels CONT
+
+ templayer pdihvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+
+ layer pdihvtc pdihvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdihvtcbase
+ labels CONT
+
+ templayer mvndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and THKOX
+
+ layer mvndc mvndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndcbase
+ labels CONT
+
+ templayer mvnscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvnsc mvnscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnscbase
+ labels CONT
+
+ templayer mvpdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvpdc mvpdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcbase
+ labels CONT
+
+ templayer mvpdcnowell CONT
+ and DIFF
+ and PPLUS
+ and mvpfetexpand
+ and MET1
+ and THKOX
+
+ layer mvpdc mvpdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcnowell
+ labels CONT
+
+ templayer mvpscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not mvpfetexpand
+ and LI
+ and THKOX
+
+ layer mvpsc mvpscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpscbase
+ labels CONT
+
+ templayer mvndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ and THKOX
+
+ layer mvndic mvndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndicbase
+ labels CONT
+
+ templayer nndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ and THKOX
+
+ layer nndic nndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nndicbase
+ labels CONT
+
+ templayer mvpdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+
+ layer mvpdic mvpdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdicbase
+ labels CONT
+
+ layer locali LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and-not COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer coreli LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer rli LI
+ and LIRES,LISHORT
+ labels LIRES,LISHORT
+
+ layer lic MCON
+ grow 95
+ shrink 95
+ shrink 85
+ grow 85
+ or MCON
+ labels MCON
+
+ layer m1 MET1,MET1TXT,MET1PIN
+ and-not MET1RES,MET1SHORT
+ labels MET1
+ labels MET1TXT text
+ labels MET1PIN port
+
+ layer rm1 MET1
+ and MET1RES,MET1SHORT
+ labels MET1RES,MET1SHORT
+
+#ifdef MIM
+ layer mimcap MET3
+ and CAPM
+ labels CAPM
+
+ layer mimcc VIA3
+ and CAPM
+ grow 60
+ grow 40
+ shrink 40
+ labels CAPM
+
+ layer mimcap2 MET4
+ and CAPM2
+ labels CAPM2
+
+ layer mim2cc VIA4
+ and CAPM2
+ grow 190
+ grow 210
+ shrink 210
+ labels CAPM2
+
+#endif (MIM)
+
+ templayer m2cbase VIA1
+ grow 55
+
+ layer m2c m2cbase
+ grow 30
+ shrink 30
+ shrink 130
+ grow 130
+ or m2cbase
+
+ layer m2 MET2,MET2TXT,MET2PIN
+ and-not MET2RES,MET2SHORT
+ labels MET2
+ labels MET2TXT text
+ labels MET2PIN port
+
+ layer rm2 MET2
+ and MET2RES,MET2SHORT
+ labels MET2RES,MET2SHORT
+
+ templayer m3cbase VIA2
+ grow 40
+
+ layer m3c m3cbase
+ grow 60
+ shrink 60
+ shrink 140 
+ grow 140
+ or m3cbase
+
+ layer m3 MET3,MET3TXT,MET3PIN
+ and-not MET3RES,MET3SHORT
+#ifdef MIM
+ and-not CAPM
+#endif (MIM)
+ labels MET3
+ labels MET3TXT text
+ labels MET3PIN port
+
+ layer rm3 MET3
+ and MET3RES,MET3SHORT
+ labels MET3RES,MET3SHORT
+
+#ifdef (METAL5)
+
+ templayer via3base VIA3
+#ifdef MIM
+ and-not CAPM
+#endif (MIM)
+ grow 60
+
+ layer via3 via3base
+ grow 40
+ shrink 40
+ shrink 160
+ grow 160
+ or via3base
+
+ layer m4 MET4,MET4TXT,MET4PIN
+ and-not MET4RES,MET4SHORT
+#ifdef MIM
+ and-not CAPM2
+#endif (MIM)
+ labels MET4
+ labels MET4TXT text
+ labels MET4PIN port
+
+ layer rm4 MET4
+ and MET4RES,MET4SHORT
+ labels MET4RES,MET4SHORT
+
+ layer m5 MET5,MET5TXT,MET5PIN
+ and-not MET5RES,MET5SHORT
+ labels MET5
+ labels MET5TXT text
+ labels MET5PIN port
+
+ layer rm5 MET5
+ and MET5RES,MET5SHORT
+ labels MET5RES,MET5SHORT
+
+ templayer via4base VIA4
+#ifdef MIM
+ and-not CAPM2
+#endif (MIM)
+ grow 190
+
+ layer via4 via4base
+ grow 210
+ shrink 210
+ shrink 590
+ grow 590
+ or via4base
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+ layer metrdl RDL,RDLTXT,RDLPIN
+ labels RDL
+ labels RDLTXT text
+ labels RDLPIN port
+#endif
+
+ # Find diffusion not covered in
+ # NPLUS or PPLUS and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and POLY
+ copyup DIFF,POLY
+
+ templayer gendiff DIFF,TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ copyup DIFF
+
+ # Handle contacts found by copyup
+
+ templayer ndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and-not THKOX
+
+ layer ndic ndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndiccopy
+ labels CONT
+
+ templayer mvndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and THKOX
+
+ layer mvndic mvndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndiccopy
+ labels CONT
+
+ templayer pdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and-not THKOX
+
+ layer pdic pdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdiccopy
+ labels CONT
+
+ templayer mvpdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and THKOX
+
+ layer mvpdic mvpdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdiccopy
+ labels CONT
+
+ templayer ndccopy CONT
+ and ndifcheck
+
+ layer ndc ndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndccopy
+ labels CONT
+
+ templayer mvndccopy CONT
+ and mvndifcheck
+
+ layer mvndc mvndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndccopy
+ labels CONT
+
+ templayer pdccopy CONT
+ and pdifcheck
+
+ layer pdc pdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdccopy
+ labels CONT
+
+ templayer mvpdccopy CONT
+ and mvpdifcheck
+
+ layer mvpdc mvpdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdccopy
+ labels CONT
+
+ templayer pccopy CONT
+ and polycheck
+
+ layer pc pccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pccopy
+ labels CONT
+
+ templayer nsccopy CONT
+ and nsubcheck
+
+ layer nsc nsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nsccopy
+ labels CONT
+
+ templayer mvnsccopy CONT
+ and mvnsubcheck
+
+ layer mvnsc mvnsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnsccopy
+ labels CONT
+
+ templayer psccopy CONT
+ and psubcheck
+
+ layer psc psccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or psccopy
+ labels CONT
+
+ templayer mvpsccopy CONT
+ and mvpsubcheck
+
+ layer mvpsc mvpsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpsccopy
+ labels CONT
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+ 
+ templayer gencont CONT
+ and LI
+ and-not DIFF,TAP
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT,LI
+
+ templayer barecont CONT
+ and-not LI
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT
+
+ layer glass GLASS,PADTXT,PADPIN
+ labels GLASS
+ labels PADTXT text
+ labels PADPIN port
+
+ templayer boundary BOUND,STDCELL,PADCELL
+ boundary
+
+ layer comment LVSTEXT
+ labels LVSTEXT text
+
+ layer comment TTEXT
+ labels TTEXT text
+
+ layer fillblock  FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+ labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+
+# MOS Varactor
+
+ layer var POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and-not HVTP
+ grow 25
+ labels POLY
+
+ layer varhvt POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and HVTP
+ grow 25
+ labels POLY
+
+ layer mvvar POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and THKOX
+ grow 25
+ labels POLY
+
+ calma NWELL 64 20
+ calma DIFF 65 20
+ calma DNWELL 64 18
+ calma PWRES 64 13
+ calma TAP  65 44
+ # LVTN
+ calma LVTN 125 44
+ # HVTP
+ calma HVTP 78 44
+ # SONOS (TUNM)
+ calma SONOS 80 20
+ # NPLUS = NSDM
+ calma NPLUS 93 44
+ # PPLUS = PSDM
+ calma PPLUS 94 20
+ # HVI
+ calma THKOX 75 20
+ # NPC
+ calma NPC 95 20
+ # P+ POLY MASK
+ calma RPM 86 20
+ calma URPM 79 20
+ calma LDNTM 11 44
+ calma HVNTM 125 20
+ # Poly resistor ID mark
+ calma POLYRES 66 13
+ # Diffusion resistor ID mark
+ calma DIFFRES 65 13
+ calma POLY 66 20
+ calma POLYMOD 66 83
+ # Diode ID mark
+ calma DIODE 81 23
+ # Bipolar NPN mark
+ calma NPNID 82 20
+ # Bipolar PNP mark
+ calma PNPID 82 20
+ # Capacitor ID
+ calma CAPID 82 64
+ # Core area ID mark
+ calma COREID 81 2
+ # Standard cell ID mark
+ calma STDCELL 81 4
+ # Padframe cell ID mark
+ calma PADCELL 81 3
+ # Seal ring ID mark
+ calma SEALID 81 1
+ # Low tap density ID mark
+ calma LOWTAPDENSITY 81 14
+ 
+ # LICON
+ calma CONT 66 44
+ calma LI   67 20
+ calma MCON 67 44
+
+ calma MET1 68 20
+ calma VIA1 68 44
+ calma MET2 69 20
+ calma VIA2 69 44
+ calma MET3 70 20
+#ifdef METAL5
+ calma VIA3 70 44
+ calma MET4 71 20
+ calma VIA4 71 44
+ calma MET5 72 20
+#endif
+#ifdef REDISTRIBUTION
+ calma RDL 74 20
+#endif
+ calma GLASS 76 20
+
+ calma SUBPIN  64 59
+ calma PADPIN  76 5
+ calma DIFFPIN 65 6
+ calma TAPPIN  65 5
+ calma WELLPIN  64 5
+ calma LIPIN 67 5
+ calma POLYPIN 66 5
+ calma MET1PIN 68 5
+ calma MET2PIN 69 5
+ calma MET3PIN 70 5
+#ifdef METAL5
+ calma MET4PIN 71 5
+ calma MET5PIN 72 5
+#endif
+#ifdef REDISTRIBUTION
+ calma RDLPIN 74 5
+#endif
+
+ calma LIRES 67 13
+ calma MET1RES 68 13
+ calma MET2RES 69 13
+ calma MET3RES 70 13
+#ifdef METAL5
+ calma MET4RES 71 13
+ calma MET5RES 72 13
+#endif
+
+ calma POLYSHORT 66 15
+ calma LISHORT 67 15
+ calma MET1SHORT 68 15
+ calma MET2SHORT 69 15
+ calma MET3SHORT 70 15
+#ifdef METAL5
+ calma MET4SHORT 71 15
+ calma MET5SHORT 72 15
+#endif
+
+ calma SUBTXT 122 16
+ calma PADTXT 76 16
+ calma DIFFTXT 65 16
+ calma POLYTXT 66 16
+ calma WELLTXT 64 16
+ calma LITXT 67 16
+ calma MET1TXT 68 16
+ calma MET2TXT 69 16
+ calma MET3TXT 70 16
+#ifdef METAL5
+ calma MET4TXT 71 16
+ calma MET5TXT 72 16
+#endif
+#ifdef REDISTRIBUTION
+ calma RDLPIN 74 16
+#endif
+
+ calma BOUND 235 4
+
+ calma LVSTEXT 83 44
+
+#ifdef (MIM)
+ calma CAPM 89 44
+ calma CAPM2 97 44
+#endif (MIM)
+
+ calma FILLOBSM1  62  24
+ calma FILLOBSM2  105 52
+ calma FILLOBSM3  107 24
+ calma FILLOBSM4  112 4
+
+end
+
+#-----------------------------------------------------
+# Digital flow maze router cost parameters
+#-----------------------------------------------------
+
+mzrouter
+end
+
+#-----------------------------------------------------
+# Vendor DRC rules
+#-----------------------------------------------------
+
+drc
+
+ style drc variants (fast),(full),(routing)
+
+ scalefactor 10 
+
+ cifstyle drc
+
+ variants (fast),(full)
+
+#-----------------------------
+# DNWELL
+#-----------------------------
+
+ width dnwell 3000 "Deep N-well width < %d (Dnwell 2)"
+ spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (Dnwell 3)"
+ spacing dnwell allnwell 4500 surround_ok \
+	"Deep N-well spacing to N-well < %d (Nwell 7)"
+ cifmaxwidth nwell_missing 0 bend_illegal \
+	"N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (Nwell 5a, 7)"
+ cifmaxwidth dnwell_missing 0 bend_illegal \
+	"SONOS nFET must be in Deep N-well (Tunm 6a)"
+
+#-----------------------------
+# NWELL
+#-----------------------------
+
+ width allnwell 840 "N-well width < %d (Nwell 1)"
+ spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (Nwell 2a)"
+
+#-----------------------------
+# DIFF
+#-----------------------------
+
+ width *ndiff,nfet,scnfet,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,*psd,*pdiode,pdiffres \
+	150 "Diffusion width < %d (Diff/tap 1)"
+ width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \
+	"MV Diffusion width < %d (Diff/tap 14)"
+ width *mvnsd,*mvpsd 150 "MV Tap width < %d (Diff/tap 1)"
+ extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (Diff/tap 16)"
+ extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (Diff/tap 16)"
+ extend *psd *ndiff 290 "Butting tap length < %d (Diff/tap 4)"
+ extend *nsd *pdiff 290 "Butting tap length < %d (Diff/tap 4)"
+ width mvpdiffres 150 "MV P-Diffusion resistor width < %d (Diff/tap 14a)"
+ spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
+	"Diffusion spacing < %d (Diff/tap 3)"
+ spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
+	"MV Diffusion spacing < %d (Diff/tap 15a)"
+ spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
+	"MV Diffusion to MV tap spacing < %d (Diff/tap 3)"
+ spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
+	touching_ok "MV P-Diffusion to MV N-tap spacing < %d (Diff/tap 15b)"
+ spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
+	"MV Diffusion in N-well to P-tap spacing < %d (Diff/tap 20 + Diff/tap 17,19)"
+ spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (Diff/tap 9)"
+ spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (Diff/tap 9)"
+ spacing *psd allnwell 130 touching_illegal \
+	"P-tap spacing to N-well < %d (Diff/tap 11)"
+ spacing *mvpsd allnwell 130 touching_illegal \
+	"P-tap spacing to N-well < %d (Diff/tap 11)"
+ surround *nsd allnwell 180 absence_illegal \
+	"N-well overlap of N-tap < %d (Diff/tap 10)"
+ surround *mvnsd allnwell 330 absence_illegal \
+	"N-well overlap of MV N-tap < %d (Diff/tap 19)"
+ surround *pdiff,*pdiode,pfet,scpfet allnwell 180 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (Diff/tap 8)"
+ surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (Diff/tap 17)"
+ surround mvvar allnwell 560 absence_illegal \
+	"N-well overlap of MV varactor < %d (LVTN 10 + LVTN 4b)"
+ spacing *mvndiode *mvndiode 1070 touching_ok \
+	"MV N-diode spacing < %d (HVNTM.2 + 2 * HVNTM.3)"
+
+ # Butting junction rules
+ edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
+	"N-Diffusion to P-tap spacing < %d across butted junction"
+ edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
+	"N-Diffusion to P-tap spacing < %d across butted junction"
+ edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
+	"P-Diffusion to N-tap spacing < %d across butted junction"
+ edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
+	"P-Diffusion to N-tap spacing < %d across butted junction"
+
+ edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
+	"MV N-Diffusion to MV P-tap spacing < %d across butted junction"
+ edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
+	"MV N-Diffusion to MV P-tap spacing < %d across butted junction"
+ edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
+	"MV P-Diffusion to MV N-tap spacing < %d across butted junction"
+ edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
+	"MV P-Diffusion to MV N-tap spacing < %d across butted junction"
+
+ variants (full)
+
+ # Latchup rules
+ cifmaxwidth ptap_missing 0 bend_illegal \
+	"N-diff distance to P-tap must be < 15.0um (LU 2)"
+ cifmaxwidth dptap_missing 0 bend_illegal \
+	"N-diff distance to P-tap in deep Nwell must be < 15.0um (LU 2.1)"
+ cifmaxwidth ntap_missing 0 bend_illegal \
+	"P-diff distance to N-tap must be < 15.0um (LU 3)"
+
+ variants *
+
+#-----------------------------
+# POLY
+#-----------------------------
+
+ width allpoly 150 "Poly width < %d (Poly 1a)"
+ spacing allpoly allpoly 210 touching_ok "Poly spacing < %d (Poly 2)"
+ spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \
+	"Poly spacing to Diffusion < %d (Poly 4a)"
+ spacing npres *nsd 480 touching_illegal \
+	"Poly resistor spacing to N-tap < %d (Poly 9)"
+ overhang *ndiff,rndiff nfet,scnfet 250 "N-Diffusion overhang of nmos < %d (Poly 7)"
+ overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
+	"N-Diffusion overhang of nmos < %d (Poly 7)"
+ overhang *pdiff,rpdiff pfet,scpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
+ overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
+ overhang *poly allfets 130 "Poly overhang of transistor < %d (Poly 8)"
+ rect_only allfets "No bends in transistors (Poly 11)"
+ rect_only xhrpoly,uhrpoly "No bends in poly resistors (Poly 11)"
+ extend  xpc/a xhrpoly,uhrpoly 2160 \
+ 	"Poly contact extends poly resistor by < %d (LIcon 1c + LI 5)"
+ spacing xhrpoly,uhrpoly xhrpoly,uhrpoly 1240 touching_illegal \
+	"Distance between precision resistors < %d (RPM 2 + 2 * RPM 3)"
+
+#--------------------------------------------------------------------
+# NPC (Nitride Poly Cut)
+#--------------------------------------------------------------------
+
+# Layer NPC is defined automatically around poly contacts (grow 0.1um)
+
+#--------------------------------------------------------------------
+# CONT (LICON, contact between poly/diff and LI)
+#--------------------------------------------------------------------
+
+ width ndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
+ width nsc/li 170 "N-tap contact width     < %d (LIcon 1)"
+ width pdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
+ width psc/li 170 "P-tap contact width     < %d (LIcon 1)"
+ width ndic/li 170 "N-diode contact width < %d (LIcon 1)"
+ width pdic/li 170 "P-diode contact width < %d (LIcon 1)"
+ width pc/li  170 "Poly contact width        < %d (LIcon 1)"
+
+ width xpc/li  350 "Poly resistor contact width < %d (LIcon 1b + 2 * LI 5)"
+
+ width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
+ width mvnsc/li 170 "N-tap contact width     < %d (LIcon 1)"
+ width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
+ width mvpsc/li 170 "P-tap contact width     < %d (LIcon 1)"
+ width mvndic/li 170 "N-diode contact width < %d (LIcon 1)"
+ width mvpdic/li 170 "P-diode contact width < %d (LIcon 1)"
+
+ spacing allpdiffcont allndiffcont 170 touching_illegal \
+	"Diffusion contact spacing < %d (LIcon 2)"
+ spacing allndiffcont allndiffcont 170 touching_ok \
+	"Diffusion contact spacing < %d (LIcon 2)"
+ spacing allpdiffcont allpdiffcont 170 touching_ok \
+	"Diffusion contact spacing < %d (LIcon 2)"
+ spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (LIcon 2)"
+
+ spacing pc alldiff 190 touching_illegal \
+	"Poly contact spacing to diffusion < %d (LIcon 14)"
+ spacing pc allpfets 235 touching_illegal \
+	"Poly contact spacing to pFET < %d (LIcon 9 + PSDM 5a)"
+
+ spacing ndc,pdc nfet,pfet 55 touching_illegal \
+	"Diffusion contact to gate < %d (LIcon 11)"
+ spacing ndc,pdc scnfet,scpfet 50 touching_illegal \
+	"Diffusion contact to standard cell gate < %d (LIcon 11)"
+ spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
+	"Diffusion contact to gate < %d (LIcon 11)"
+ spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d ()"
+ spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d ()"
+ spacing nsc varactor,varhvt 250 touching_illegal \
+	"Diffusion contact to varactor gate < %d (LIcon 10)"
+ spacing mvnsc mvvar 250 touching_illegal \
+	"Diffusion contact to varactor gate < %d (LIcon 10)"
+
+ surround ndc/a *ndiff,nfet,scnfet,nfetlvt 40 absence_illegal \
+	"N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
+ surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 40 absence_illegal \
+	"P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
+ surround ndic/a *ndi 40 absence_illegal \
+	"N-diode overlap of N-diode contact < %d (LIcon 5a)"
+ surround pdic/a *pdi 40 absence_illegal \
+	"P-diode overlap of N-diode contact < %d (LIcon 5a)"
+
+ surround ndc/a *ndiff,nfet,scnfet,nfetlvt 60 directional \
+	"N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
+ surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 60 directional \
+	"P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
+ surround ndic/a *ndi 60 directional \
+	"N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+ surround pdic/a *pdi 60 directional \
+	"P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+
+ surround nsc/a *nsd 120 directional \
+	"N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
+ surround psc/a *psd 120 directional \
+	"P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
+
+ surround mvndc/a *mvndiff,mvnfet 40 absence_illegal \
+	"N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
+ surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal \
+	"P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
+ surround mvndic/a *mvndi 40 absence_illegal \
+	"N-diode overlap of N-diode contact < %d (LIcon 5a)"
+ surround mvpdic/a *mvpdi 40 absence_illegal \
+	"P-diode overlap of N-diode contact < %d (LIcon 5a)"
+
+ surround mvndc/a *mvndiff,mvnfet 60 directional \
+	"N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
+ surround mvpdc/a *mvpdiff,mvpfet 60 directional \
+	"P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
+ surround mvndic/a *mvndi 60 directional \
+	"N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+ surround mvpdic/a *mvpdi 60 directional \
+	"P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+
+ surround mvnsc/a *mvnsd 120 directional \
+	"N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
+ surround mvpsc/a *mvpsd 120 directional \
+	"P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
+
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
+	"Poly overlap of poly contact < %d (LIcon 8)"
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
+	"Poly overlap of poly contact < %d in one direction (LIcon 8a)"
+
+ exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a
+ exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a
+
+#-------------------------------------------------------------
+# LI - Local interconnect layer
+#-------------------------------------------------------------
+
+ width *li,rli 170 "Local interconnect width < %d (LI 1)"
+ width coreli 140 "Core local interconnect width < %d (LI c1)"
+ spacing allli allli,*obsli 170 touching_ok  "Local interconnect spacing < %d (LI 3)"
+ spacing coreli allli,*obsli 140 touching_ok  "Core local interconnect spacing < %d (LI c2)"
+
+ surround pc/li *li 80 directional \
+	"Local interconnect overlap of poly contact < %d in one direction (LI 5)"
+
+ surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
+	*li,rli 80 directional \
+	"Local interconnect overlap of diffusion contact < %d in one direction (LI 5)"
+
+ area allli,*obsli 56100 170 "Local interconnect minimum area < %a (LI 6)"
+
+#-------------------------------------------------------------
+# MCON - Contact between local interconnect and metal1
+#-------------------------------------------------------------
+
+ width lic/m1 170 "Mcon width < %d (Mcon 1)"
+ spacing lic/m1 lic/m1,obslic/m1 170 touching_ok "Mcon spacing < %d (Mcon 2)"
+
+ exact_overlap lic/m1
+
+#-------------------------------------------------------------
+# METAL1 -
+#-------------------------------------------------------------
+
+ width *m1,rm1 140 "Metal1 width < %d (Met1 1)"
+ spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (Met1 2)"
+ area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (Met1 6)"
+
+ surround lic/m1 *met1 30 absence_illegal \
+	"Metal1 overlap of local interconnect contact < %d (Met1 4)"
+ surround lic/m1 *met1 60 directional \
+	"Metal1 overlap of local interconnect contact < %d in one direction (Met1 5)"
+
+variants (fast),(full)
+ widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
+	"Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
+ widespacing *obsm1 3000 allm1 280 touching_ok \
+	"Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
+
+variants (full)
+ cifmaxwidth m1_hole_empty 0 bend_illegal \
+	"Min area of metal1 holes > 0.14um^2 (Met1 7)"
+variants *
+
+#--------------------------------------------------
+# VIA1
+#--------------------------------------------------
+
+ width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a)"
+ spacing v1 v1 60 touching_ok "Via1 spacing < %d (Via 2 - 2 * Via 4a)"
+ surround v1/m1 *m1 30 directional \
+	"Metal1 overlap of Via1 < %d in one direction (Via 5a - Via 4a)"
+ surround v1/m2 *m2 30 directional \
+	"Metal2 overlap of Via1 < %d in one direction (Met2 5 - Met2 4)"
+
+ exact_overlap v1/m2
+
+#--------------------------------------------------
+# METAL2 - 
+#--------------------------------------------------
+
+ width allm2 140 "Metal2 width < %d (Met2 1)"
+ spacing allm2  allm2,obsm2 140 touching_ok       "Metal2 spacing < %d (Met2 2)"
+ area allm2,obsm2 67600 140 "Metal2 minimum area < %a (Met2 6)"
+
+variants (fast),(full)
+ widespacing allm2 3000 allm2,obsm2  280 touching_ok \
+	"Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
+ widespacing obsm2 3000 allm2  280 touching_ok \
+	"Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
+
+variants (full)
+ cifmaxwidth m2_hole_empty 0 bend_illegal \
+	"Min area of metal2 holes > 0.14um^2 (Met2 7)"
+variants *
+
+#--------------------------------------------------
+# VIA2
+#--------------------------------------------------
+
+ width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4)"
+
+ spacing v2 v2 120 touching_ok "Via2 spacing < 0.24um (Via2 2 - 2 * Via2 4)"
+
+ surround v2/m2 *m2 45 directional \
+	"Metal2 overlap of Via2 < %d in one direction (Via2 4a - Via2 4)"
+ surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of Via2 < %d (Met3 4)"
+
+ exact_overlap v2/m2
+
+#--------------------------------------------------
+# METAL3 - 
+#--------------------------------------------------
+
+ width allm3 300 "Metal3 width < %d (Met3 1)"
+ spacing allm3 allm3,obsm3  300 touching_ok "Metal3 spacing < %d (Met3 2)"
+ area allm3,obsm3 240000 300 "Metal3 minimum area < %a (Met3 6)"
+
+variants (fast),(full)
+ widespacing allm3 3000 allm3,obsm3  400 touching_ok \
+	"Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
+ widespacing obsm3 3000 allm3  400 touching_ok \
+	"Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
+variants *
+
+
+#ifdef METAL5
+#--------------------------------------------------
+# VIA3 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4)"
+ spacing v3 v3 80 touching_ok "Via3 spacing < %d (Via3 2 - 2 * Via3 4)"
+ surround v3/m3 *m3 30 directional \
+	"Metal3 overlap of Via3 in one direction < %d (Via3 5 - Via3 4)"
+ surround v3/m4 *m4 5 directional \
+	"Metal4 overlap of Via3 in one direction < %d (Met4 3 - Via3 4)"
+
+ exact_overlap v3/m3
+
+#-----------------------------
+# METAL4 - METAL4 Module
+#-----------------------------
+
+variants *
+
+ width allm4 300 "Metal4 width < %d (Met4 1)"
+ spacing allm4  allm4,obsm4 300 touching_ok      "Metal4 spacing < %d (Met4 2)"
+ area allm4,obsm4 240000 300 "Metal4 minimum area < %a (Met4 4a)"
+
+variants (fast),(full)
+ widespacing allm4 3000 allm4,obsm4  400 touching_ok \
+	"Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
+ widespacing obsm4 3000 allm4  400 touching_ok \
+	"Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
+variants *
+
+#--------------------------------------------------
+# VIA4 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4)"
+ spacing v4 v4 420 touching_ok "Via4 spacing < %d (Via4 2 - 2 * Via4 4)"
+ surround v4/m5 *m5 120 absence_illegal \
+	"Metal5 overlap of Via4 < %d (Met5 3 - Via4 4)"
+
+ exact_overlap v4/m4
+
+#-----------------------------
+# METAL5 - METAL5 Module
+#-----------------------------
+
+ width allm5 1600 "Metal5 width < %d (Met5 1)"
+ spacing allm5  allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (Met5 2)"
+ area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (Met5 4)"
+
+#endif (METAL5)
+
+#ifdef REDISTRIBUTION
+
+variants (full)
+
+ width metrdl 10000 "RDL width < %d (Rdl 1)"
+ spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (Rdl 2)"
+ surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (Rdl 3)"
+ spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (Rdl 6)"
+
+variants *
+
+#endif (REDISTRIBUTION)
+
+#--------------------------------------------------
+# NMOS, PMOS
+#--------------------------------------------------
+
+ extend allfets *poly 420 "Transistor width < %d (Diff/tap 2)"
+ # Except:  Note that standard cells allow transistor width minimum 0.36um
+ width pfetlvt 350 "LVT PMOS gate length < %d (Poly 1b)"
+
+ spacing *nsd,*mvnsd allpolynonfet 55 touching_illegal \
+	"N-tap spacing to field poly < %d (Poly 5)"
+ spacing *psd,*mvpsd allpolynonfet 55 touching_illegal \
+	"P-tap spacing to field poly < %d (Poly 5)"
+
+ # Full edge rule required to describe FET to butted tap distance
+ edge4way *psd *ndiff 300 *ndiff *psd 300 \
+	"Butting P-tap spacing to NMOS gate < %d (Poly 6)"
+ edge4way *nsd *pdiff 300 *pdiff *nsd 300 \
+	"Butting N-tap spacing to PMOS gate < %d (Poly 6)"
+ edge4way *mvpsd *mvndiff 300 *mvndiff *mvpsd 300 \
+	"Butting MV P-tap spacing to MV NMOS gate < %d (Poly 6)"
+ edge4way *mvnsd *mvpdiff 300 *mvpdiff *mvnsd 300 \
+	"Butting MV N-tap spacing to MV PMOS gate < %d (Poly 6)"
+
+ # No LV FETs in HV diff
+ spacing pfet,scpfet,pfetlvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
+	"LV P-diffusion to MV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ spacing nfet,scnfet,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
+	"LV N-diffusion to MV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ # No HV FETs in LV diff
+ spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
+	"MV P-diffusion to LV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
+	"MV N-diffusion to LV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ # Minimum length of MV FETs.  Note that this is larger than the minimum
+ # width (0.29um), so an edge rule is required
+
+ edge4way mvndiff mvnfet 500 mvnfet 0 0 \
+	"MV NMOS minimum length < %d (Poly 13)"
+
+ edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
+	"MV Varactor minimum length < %d (Poly 13)"
+
+ edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
+	"MV PMOS minimum length < %d (Poly 13)"
+
+#--------------------------------------------------
+# mrp1 (N+ poly resistor)
+#--------------------------------------------------
+
+  width mrp1 330 "mrp1 resistor width < %d (Poly 3)"
+
+#--------------------------------------------------
+# xhrpoly (P+ poly resistor)
+#--------------------------------------------------
+
+  width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a)"
+  # NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27.
+
+#--------------------------------------------------
+# uhrpoly (P+ poly resistor, 2kOhm/sq)
+#--------------------------------------------------
+
+  width uhrpoly 350 "uhrpoly resistor width < %d"
+  spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+	"xhrpoly/uhrpoly resistor spacing to diffusion < %d (Poly 9)"
+
+#------------------------------------
+# MOS Varactor device rules
+#------------------------------------
+
+ overhang *nsd var,varhvt 250 \
+ "N-Tap overhang of Varactor < %d (Var 4)"
+
+ overhang *mvnsd mvvar 250 \
+ "N-Tap overhang of Varactor < %d (Var 4)"
+
+ width var,varhvt,mvvar 180 "Varactor length < %d (Var 1)"
+ extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (Var 2)"
+
+#ifdef MIM
+#-----------------------------------------------------------
+# MiM CAP (CAPM) - 
+#-----------------------------------------------------------
+
+ width *mimcap 2000 "MiM cap width < %d (Capm 1)"
+ spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (Capm 2a)"
+ spacing *mimcap via2/m3 1270 touching_illegal \
+	"MiM cap spacing to via2 < %d (Capm 5)"
+ surround *mimcc *mimcap 200 absence_illegal \
+	"MiM cap must surround MiM cap contact by %d (Capm 4)"
+ rect_only *mimcap "MiM cap must be rectangular (Capm 7)
+
+ surround *mimcap *metal3/m3 140 absence_illegal \
+	"Metal3 must surround MiM cap by %d (Capm 3)"
+ spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 (Capm 8)"
+ spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (Capm 8)"
+ # (resolve scaling issue!)
+ # cifspacing mim_bottom mim_bottom 1200 touching_ok \
+ #	"MiM cap bottom plate spacing < %d (Capm 2b)"
+
+ # MiM cap contact rules (VIA3)
+
+ width mimcc/m3 320 "MiM cap contact width < %d (Via3 1 + 2 * Via3 4)"
+ spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (Via3 2 - 2 * Via3 4)"
+ surround mimcc/m4 *m4 5 directional \
+	"Metal4 overlap of MiM cap contact in one direction < %d (Met4 3 - Via3 4)"
+ exact_overlap mimcc/m3
+
+ width *mimcap2 2000 "MiM cap width < %d (Cap2m 1)"
+ spacing *mimcap2 *mimcap2 840 touching_ok "MiM cap spacing < %d (Cap2m 2a)"
+ spacing *mimcap2 via3/m4 1270 touching_illegal \
+	"MiM cap spacing to via3 < %d (Cap2m 5)"
+ surround *mim2cc *mimcap2 200 absence_illegal \
+	"MiM cap must surround MiM cap contact by %d (Cap2m 4)"
+ rect_only *mimcap2 "MiM cap must be rectangular (Cap2m 7)
+
+ surround *mimcap2 *metal4/m4 140 absence_illegal \
+	"Metal4 must surround MiM cap by %d (Cap2m 3)"
+ spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 (Cap2m 8)"
+ spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 (Cap2m 8)"
+ # (resolve scaling issue!)
+ # cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
+ #	"MiM2 cap bottom plate spacing < %d (Cap2m 2b)"
+
+ # MiM cap contact rules (VIA4)
+
+ width mim2cc/m4 1180 "MiM2 cap contact width < %d (Via4 1 + 2 * Via4 4)"
+ spacing mim2cc mim2cc 420 touching_ok \
+	"MiM2 cap contact spacing < %d (Via4 2 - 2 * Via4 4)"
+ surround mim2cc/m5 *m5 120 absence_illegal \
+	"Metal5 overlap of MiM2 cap contact < %d (Met5 3 - Via4 4)"
+ exact_overlap mim2cc/m4
+
+#endif (MIM)
+
+#----------------------------
+# End DRC style
+#----------------------------
+
+end
+
+#----------------------------
+# LEF format definitions
+#----------------------------
+
+lef
+
+ routing li	li1 LI1 LI li
+
+ routing m1	met1 MET1 m1
+ routing m2	met2 MET2 m2
+ routing m3	met3 MET3 m3
+#ifdef METAL5
+ routing m4	met4 MET4 m4
+ routing m5	met5 MET5 m5
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ routing mrdl	met6 MET6 m6 MRDL METRDL
+#endif
+
+ cut lic  mcon MCON Mcon
+ cut m2c  via via1 VIA VIA1 cont2 via12
+ cut m3c  via2 VIA2 cont3 via23
+#ifdef METAL5
+ cut via3 via3 VIA3 cont4 via34
+ cut via4 via4 VIA4 cont5 via45
+#endif (METAL5)
+
+ obs obsli   li1
+ obs obsm1   met1
+ obs obsm2   met2
+ obs obsm3   met3
+
+#ifdef METAL5
+ obs obsm4   met4
+ obs obsm5   met5
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ obs obsmrdl met6
+#endif
+
+ obs obslic mcon
+
+end
+
+#-----------------------------------------------------
+# Device and Parasitic extraction
+#-----------------------------------------------------
+
+
+extract
+ style ngspice variants (lvs),(sim),(si)
+ cscale 1
+ # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
+ # dimensions must be in units of microns in the extract file.
+ # Use extract style "ngspice(si)" to override this and produce
+ # a file with SI units for length/area.
+
+ variants (lvs),(sim)
+ lambda  1E6
+ variants (si)
+ lambda 1.0
+ variants *
+
+ units	microns
+ step   7
+ sidehalo 2
+
+ # NOTE:  MiM cap layers have been purposely put out of order,
+ # may want to reconsider.
+
+ planeorder dwell 	0
+ planeorder well 	1
+ planeorder active 	2
+ planeorder locali 	3
+ planeorder metal1 	4
+ planeorder metal2 	5
+ planeorder metal3 	6
+#ifdef METAL5
+ planeorder metal4 	7
+ planeorder metal5 	8
+#ifdef REDISTRIBUTION
+ planeorder metali	9
+ planeorder block      10
+ planeorder comment    11
+ planeorder cap1       12
+ planeorder cap2       13
+#else (!REDISTRIBUTION)
+ planeorder block       9	
+ planeorder comment    10
+ planeorder cap1       11
+ planeorder cap2       12
+#endif (!REDISTRIBUTION)
+#else (!METAL5)
+#ifdef REDISTRIBUTION
+ planeorder metali     7
+ planeorder block      8
+ planeorder comment    9
+ planeorder cap1       10
+ planeorder cap2       11
+#else (!REDISTRIBUTION)
+ planeorder block      7
+ planeorder comment    8
+ planeorder cap1       9
+ planeorder cap2       10
+#endif (!REDISTRIBUTION)
+#endif (!METAL5)
+
+ height	dnwell 	    -0.1    0.1
+ height	nwell,pwell  0.0    0.2062
+ height alldiff	     0.2062 0.12
+ height allpoly	     0.3262 0.18
+ height alldiffcont  0.3262 0.61
+ height pc	     0.5062 0.43
+ height allli	     0.9361 0.10
+ height lic	     1.0361 0.34
+ height allm1	     1.3761 0.36
+ height v1	     1.7361 0.27
+ height allm2	     2.0061 0.36
+ height v2	     2.3661 0.42
+ height allm3	     2.7861 0.845
+#ifdef METAL5
+ height v3	     3.6311 0.39
+ height allm4	     4.0211 0.845
+ height v4	     4.8661 0.505
+ height allm5	     5.3711 1.26
+ height mimcap	     2.4661 0.2
+ height mimcap2	     3.7311 0.2
+ height mimcc	     2.6661 0.12
+ height mim2cc	     3.9311 0.09
+#ifdef REDISTRIBUTION
+ height mrdlc	     6.6311 5.2523
+ height mrdl	    11.8834 4.0
+#endif (!REDISTRIBUTION)
+#endif (!METAL5)
+
+ # Antenna check parameters
+ # Note that checks w/diode diffusion are not modeled
+ model partial
+ antenna poly sidewall 50 none
+ antenna allcont surface 3 none
+ antenna li sidewall 75 0 450
+ antenna lic surface 3 0 18
+ antenna m1,m2,m3 sidewall 400 2600 400
+ antenna v1 surface 3 0 18
+ antenna v2 surface 6 0 36
+#ifdef METAL5
+ antenna m4,m5 sidewall 400 2600 400
+ antenna v3,v4 surface 6 0 36
+#endif (METAL5)
+
+ tiedown alldiffnonfet
+
+ substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
+
+# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
+
+# Resistances are in milliohms per square
+# Optional 3rd argument is the corner adjustment fraction
+# Device values come from trtc.cor (typical corner)
+ resist (dnwell)/dwell          2200000
+ resist (pwell)/well            3050000
+ resist (nwell)/well            1700000
+ resist (rpw)/well              3050000 0.5
+ resist (*ndiff,nsd)/active 	 120000
+ resist (*pdiff,*psd)/active	 197000
+ resist (*mvndiff,mvnsd)/active  114000
+ resist (*mvpdiff,*mvpsd)/active 191000
+
+ resist ndiffres/active 	120000 0.5
+ resist pdiffres/active 	197000 0.5
+ resist mvndiffres/active 	114000 0.5
+ resist mvpdiffres/active 	191000 0.5
+ resist mrp1/active		 48200 0.5
+ resist xhrpoly/active	        319800 0.5
+ resist uhrpoly/active	       2000000 0.5
+
+ resist (allpolynonres)/active   48200
+ resist rmp/active   		 48200
+
+ resist (allli)/locali		 12200
+ resist (allm1)/metal1		   125
+ resist (allm2)/metal2		   125
+ resist (allm3)/metal3	            47
+#ifdef METAL5
+ resist (allm4)/metal4  	    47
+ resist (allm5)/metal5  	    29
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ resist mrdl/metali		     5
+#endif (REDISTRIBUTION)
+
+ contact ndc,nsc		 15000
+ contact pdc,psc		 15000
+ contact mvndc,mvnsc		 15000
+ contact mvpdc,mvpsc	  	 15000
+ contact pc			 15000
+ contact lic			152000
+ contact m2c			  4500
+ contact m3c			  3410
+#ifdef METAL5
+#ifdef MIM
+ contact mimcc			  4500
+ contact mim2cc			  3410
+#endif (MIM)
+ contact via3			  3410
+ contact via4			   380
+#endif (METAL5)
+#ifdef REDISTRIBUTION
+ contact mrdlc			     6
+#endif (REDISTRIBUTION)
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values:  Use document (...)
+#-------------------------------------------------------------------------
+# This uses the new "default" definitions that determine the intervening
+# planes from the planeorder stack, take care of the reflexive sideoverlap
+# definitions, and generally clean up the section and make it more readable.
+#
+# Also uses "units microns" statement, so all parasitic capacitance values
+# are taken directly from the source document PDS_035_03, in units of
+# aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
+#-------------------------------------------------------------------------
+# Remember that device capacitances to substrate are taken care of by the
+# models.  Thus, active and poly definitions ignore all "fet" types.
+# fet types are excluded when computing parasitic capacitance to
+# active from layers above them because poly is a shield; fet types are
+# included for parasitics from layers above to poly.  Resistor types
+# should be removed from all parasitic capacitance calculations, or else
+# they just create floating caps.  Technically, the capacitance probably
+# should be split between the two terminals.  Unsure of the correct model.
+#-------------------------------------------------------------------------
+
+#n-well
+# NOTE:  This value not found in PEX files
+defaultareacap     nwell well 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  105
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active  63
+ defaultareacap     *poly active nwell,obswell,pwell well  63
+ defaultperimeter   *poly active nwell,obswell,pwell well  16
+
+#locali
+ defaultsidewall    allm1 metal1       113
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  37
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  8
+ defaultoverlap     allm1 metal1 nwell well 37
+
+#locali->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 36
+ defaultsideoverlap allm1 metal1 allactivenonfet active 9
+
+#locali->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 46
+ defaultsideoverlap allm1 metal1 allpolynonres active 10
+
+#metal1
+ defaultsidewall    allm1 metal1       113
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  17
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  8
+ defaultoverlap     allm1 metal1 nwell well 26
+
+#metal1->locali
+ defaultoverlap     allm1 metal1 allactivenonfet active 36
+ defaultsideoverlap allm1 metal1 allactivenonfet active 9
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 36
+ defaultsideoverlap allm1 metal1 allactivenonfet active 9
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 46
+ defaultsideoverlap allm1 metal1 allpolynonres active 10
+
+#metal2
+ defaultsidewall    allm2 metal2      101
+ defaultareacap     allm2 metal2 nwell,obswell,pwell well 12
+ defaultperimeter   allm2 metal2 nwell,obswell,pwell well 6
+ defaultoverlap     allm2 metal2 nwell well 13
+
+#metal2->diff
+ defaultoverlap     allm2 metal2 allactivenonfet active 14
+ defaultsideoverlap allm2 metal2 allactivenonfet active 7
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 16
+ defaultsideoverlap allm2 metal2 allpolynonres active 7
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 39
+ defaultsideoverlap allm2 metal2 allm1 metal1 10
+
+#metal3
+ defaultsidewall    allm3 metal3     102
+ defaultoverlap     allm3 metal3 nwell well 8
+ defaultareacap     allm3 metal3 nwell,obswell,pwell well 8
+ defaultperimeter   allm3 metal3 nwell,obswell,pwell well 5
+
+#metal3->diff
+ defaultoverlap     allm3 metal3 allactive active 9
+ defaultsideoverlap allm3 metal3 allactive active 6
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 10
+ defaultsideoverlap allm3 metal3 allpolynonres active 6
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 15
+ defaultsideoverlap allm3 metal3 allm1 metal1 7
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 39
+ defaultsideoverlap allm3 metal3 allm2 metal2 10
+
+#ifdef METAL5
+#metal4
+ defaultsidewall    allm4 metal4       102
+# defaultareacap     alltopm metal4 well  6
+ areacap     	    allm4/m4 8
+ defaultoverlap     allm4 metal4 nwell well 8
+ defaultperimeter   allm4 metal4 well  5
+
+#metal4->diff
+ defaultoverlap     allm4 metal4 allactivenonfet active 7
+ defaultsideoverlap allm4 metal4 allactivenonfet active 7
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 7
+ defaultsideoverlap allm4 metal4 allpolynonres active 5
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 9
+ defaultsideoverlap allm4 metal4 allm1 metal1 6
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 15
+ defaultsideoverlap allm4 metal4 allm2 metal2 7
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 39
+ defaultsideoverlap allm4 metal4 allm3 metal3 10
+
+#metal5
+ defaultsidewall    allm5 metal5       103
+# defaultareacap     allm5 metal5 well  6
+ areacap     	    allm5/m5 6
+ defaultoverlap     allm5 metal5 nwell well 6
+ defaultperimeter   allm5 metal5 well  5
+
+#metal5->diff
+ defaultoverlap     allm5 metal5 allactivenonfet active 5
+ defaultsideoverlap allm5 metal5 allactivenonfet active 5
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 5
+ defaultsideoverlap allm5 metal5 allpolynonres active 5
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 7
+ defaultsideoverlap allm5 metal5 allm1 metal1 5
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 9
+ defaultsideoverlap allm5 metal5 allm2 metal2 6
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 15
+ defaultsideoverlap allm5 metal5 allm3 metal3 7
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 39
+ defaultsideoverlap allm5 metal5 allm4 metal4 10
+#endif (METAL5)
+
+# Devices:  Use document (...)
+
+variants (sim)
+
+ device msubcircuit pshort pfet,scpfet *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit plowvt pfetlvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit phighvt pfethvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+
+ device msubcircuit nshort nfet,scnfet *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit nlowvt nfetlvt *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit sonos_e nsonos *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w
+ device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w
+ device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w
+
+ device msubcircuit phv mvpfet *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
+ device msubcircuit nhv mvnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+ device msubcircuit nhvnative mvnnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+
+ device rsubcircuit short rmp     *poly	 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rli1    *li,coreli space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal1 *metal1 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal2 *metal2 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal3 *metal3 space/w,pwell,nwell error l=l w=w
+#ifdef METAL5
+ device rsubcircuit short rm4 *m4 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rm5 *m5 space/w,pwell,nwell error l=l w=w
+#endif (METAL5)
+
+ device rsubcircuit xhrpoly  xhrpoly xpc pwell,space/w error l=l w=w
+ device rsubcircuit uhrpoly  uhrpoly xpc pwell,space/w error l=l w=w
+ device rsubcircuit mrp1     mrp1    *poly pwell,space/w error 	l=l w=w
+
+ device rsubcircuit mrdn     ndiffres *ndiff pwell,space/w  error l=l w=w
+ device rsubcircuit mrdp     pdiffres *pdiff nwell    error l=l w=w
+ device rsubcircuit xpwres   rpw       pwell dnwell error l=l w=w
+
+ device rsubcircuit mrdn_hv  mvndiffres *mvndiff pwell,space/w error l=l w=w
+ device rsubcircuit mrdp_hv  mvpdiffres *mvpdiff nwell   error l=l w=w
+
+ device subcircuit  pdiode *pdiode nwell a=a p=p
+ device msubcircuit ndiode *ndiode pwell,space/w a=a p=p
+ device subcircuit  pdiode_h *mvpdiode nwell a=a p=p
+ device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p
+
+ # These are parasitic devices
+ device msubcircuit ndiode_lvt *ndiodelvt pwell,space/w a=a p=p
+ device subcircuit  pdiode_lvt *pdiodelvt nwell a=a p=p
+ device subcircuit  pdiode_hvt *pdiodehvt nwell a=a p=p
+ device msubcircuit ndiode_native *nndiode pwell,space/w a=a p=p
+
+#ifdef MIM
+ device subcircuit xcmimc1 *mimcap  m3 nwell,pwell,space/w error a=a p=p s=subs
+ device subcircuit xcmimc2 *mimcap2 m4,mimcc/m4 nwell,pwell,space/w error a=a p=p s=subs
+#endif (MIM)
+
+ variants (lvs),(si)
+
+ device mosfet pshort scpfet,pfet pdiff,pdiffres,pdc nwell 
+ device mosfet plowvt pfetlvt pdiff,pdiffres,pdc nwell 
+ device mosfet phighvt pfethvt pdiff,pdiffres,pdc nwell 
+ device mosfet nshort scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
+ device mosfet nlowvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sonos_e nsonos ndiff,ndiffres,ndc pwell,space/w
+ device mosfet phv mvpfet mvpdiff,mvpdiffres,mvpdc nwell 
+ device mosfet nhv mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet nhvnative mvnnfet *mvndiff,mvndiffres pwell,space/w
+
+ # These devices always extract as subcircuits
+ device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w
+ device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w
+ device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w
+
+ device resistor short rmp     *poly
+ device resistor short rli1    *li,coreli
+ device resistor short rmetal1 *metal1
+ device resistor short rmetal2 *metal2
+ device resistor short rmetal3 *metal3
+#ifdef METAL5
+ device resistor short rm4 *m4
+ device resistor short rm5 *m5
+#endif (METAL5)
+
+ device resistor xhrpoly xhrpoly xpc 
+ device resistor uhrpoly uhrpoly xpc 
+ device resistor mrp1 mrp1       *poly 
+ device resistor mrdn  ndiffres *ndiff 
+ device resistor mrdp  pdiffres *pdiff 
+ device resistor mrdn_hv   mvndiffres *mvndiff 
+ device resistor mrdp_hv   mvpdiffres *mvpdiff 
+ device resistor xpwres   rpw    pwell
+
+ device pdiode pdiode *pdiode nwell a=a p=p
+ device ndiode ndiode *ndiode pwell,space/w a=a p=p
+ device pdiode pdiode_h *mvpdiode nwell a=a p=p
+ device ndiode ndiode_h *mvndiode pwell,space/w a=a p=p
+
+ # These are parasitic devices
+ device ndiode ndiode_lvt *ndiodelvt pwell,space/w a=a p=p
+ device pdiode pdiode_lvt *pdiodelvt nwell a=a p=p
+ device pdiode pdiode_hvt *pdiodehvt nwell a=a p=p
+ device ndiode ndiode_native *nndiode pwell,space/w a=a p=p
+
+ device subcircuit  pdiode_h *mvpdiode nwell a=a p=p
+ device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p
+
+
+#ifdef MIM
+ device capacitor xcmimc1 *mimcap  *m3 1
+ device capacitor xcmimc2 *mimcap2 *m4 1
+#endif (MIM)
+
+end
+
+#-----------------------------------------------------
+# Wiring tool definitions
+#-----------------------------------------------------
+
+wiring
+ # All wiring values are in nanometers
+ scalefactor 10
+
+ contact lic 170 li 0  0 m1 30 60
+ contact v1  260 m1 0 30 m2  0 30  
+ contact v2  280 m2 0 45 m3 25  0
+#ifdef METAL5
+ contact v3  320 m3 0 30 m4  0  5
+ contact v4 1180 m4 0    m5 120 
+#endif (METAL5)
+
+ contact pc  170  poly 50 80 li 0 80
+ contact pdc 170 pdiff 40 60 li 0 80
+ contact ndc 170 ndiff 40 60 li 0 80
+ contact psc 170   psd 40 60 li 0 80
+ contact nsc 170   nsd 40 60 li 0 80
+
+end
+
+#-----------------------------------------------------
+# Plain old router. . . 
+#-----------------------------------------------------
+
+router
+end
+
+#------------------------------------------------------------
+# Plowing (restored in magic 8.2, need to fill this section)
+#------------------------------------------------------------
+
+plowing
+end
+
+#-----------------------------------------------------------------
+# No special plot layers defined (use default PNM color choices)
+#-----------------------------------------------------------------
+
+plot
+  style pnm
+     default
+     draw fillblock no_color_at_all
+     draw nwell cwell
+end
+