)]}'
{
  "commit": "50f669114fdede0bd4c808c681f720e482b9f3d7",
  "tree": "23dab0ffc084dbc05f50fce4e5f3a066a65c1f32",
  "parents": [
    "143afc201a91ccbdd595c310370233af22093528"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed May 10 21:11:21 2023 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed May 10 21:13:03 2023 -0400"
  },
  "message": "Added a patched version of the SRAM build space column end cell, as\nthe original version has an incorrect label and nwell directly under\nan nFET which is a DRC violation and illegal layout.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "90d6830c171c6cb07d6bab2d33efbbbb82796b5a",
      "old_mode": 33188,
      "old_path": "sky130/Makefile.in",
      "new_id": "2c77d21368060ca981fa895bcaa12a19c6d956c0",
      "new_mode": 33188,
      "new_path": "sky130/Makefile.in"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5aa0a060b191a3b4c2d11bc280d794aacdb85382",
      "new_mode": 33188,
      "new_path": "sky130/custom/sky130_fd_bd_sram/sky130_fd_bd_sram__sram_sp_colenda.gds"
    }
  ]
}