)]}'
{
  "commit": "50b373baa92fa4e006ef82dfd92e5fd70c80ca4b",
  "tree": "9527d478c2342784be1f386af9fc316e5d002cca",
  "parents": [
    "24f2950002b49d905c83bd851195d14629f3e5cf"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Oct 14 14:56:09 2021 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Oct 14 14:56:09 2021 +0200"
  },
  "message": "Update synth drving cell and cap load for all std cell variants\n",
  "tree_diff": [
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