Update synth drving cell and cap load for all std cell variants
diff --git a/sky130/openlane/sky130_fd_sc_hd/config.tcl b/sky130/openlane/sky130_fd_sc_hd/config.tcl
index 5265875..db8bd12 100755
--- a/sky130/openlane/sky130_fd_sc_hd/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hd/config.tcl
@@ -30,11 +30,11 @@
set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hd__decap_3"
# defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
#capacitance : 0.017653;
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-# update these
-set ::env(SYNTH_CAP_LOAD) "17.65" ; # femtofarad __inv_8 pin A cap
+# update these
+set ::env(SYNTH_CAP_LOAD) "33.442" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/main/cells/inv/sky130_fd_sc_hd__inv_16__tt_025C_1v80.lib.json)
set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
diff --git a/sky130/openlane/sky130_fd_sc_hdll/config.tcl b/sky130/openlane/sky130_fd_sc_hdll/config.tcl
index b77b5cb..200d22b 100755
--- a/sky130/openlane/sky130_fd_sc_hdll/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hdll/config.tcl
@@ -27,11 +27,11 @@
set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hdll__decap_3"
# defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hdll__inv_8"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hdll__inv_1"
#capacitance : 0.017653;
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
# update these
-set ::env(SYNTH_CAP_LOAD) "17.895" ; # femtofarad _inv_8 pin A cap
+set ::env(SYNTH_CAP_LOAD) "33.468" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/inv/sky130_fd_sc_hdll__inv_16__tt_025C_1v80.lib.json)
set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hdll__buf_2 A X"
set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hdll__conb_1 HI"
set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hdll__conb_1 LO"
diff --git a/sky130/openlane/sky130_fd_sc_hs/config.tcl b/sky130/openlane/sky130_fd_sc_hs/config.tcl
index 9567587..f7b4072 100755
--- a/sky130/openlane/sky130_fd_sc_hs/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hs/config.tcl
@@ -30,11 +30,11 @@
set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hs__decap_4"
# defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hs__inv_8"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hs__inv_1"
#capacitance : 0.02104;
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
# update these
-set ::env(SYNTH_CAP_LOAD) "21.04" ; # femtofarad _inv_8 pin A cap
+set ::env(SYNTH_CAP_LOAD) "43.39" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs/blob/main/cells/inv/sky130_fd_sc_hs__inv_16__tt_025C_1v68.lib.json)
set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hs__buf_2 A X"
set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hs__conb_1 HI"
set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hs__conb_1 LO"
diff --git a/sky130/openlane/sky130_fd_sc_hvl/config.tcl b/sky130/openlane/sky130_fd_sc_hvl/config.tcl
index 22fa3a6..287aefb 100644
--- a/sky130/openlane/sky130_fd_sc_hvl/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hvl/config.tcl
@@ -36,11 +36,11 @@
set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hvl__decap_4"
# defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hvl__inv_16"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hvl__inv_1"
#capacitance : 0.017653;
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-# update these
-set ::env(SYNTH_CAP_LOAD) "35.49" ; # femtofarad __inv_8 pin A cap
+# update these
+set ::env(SYNTH_CAP_LOAD) "70.77" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl/blob/main/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json)
set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hvl__buf_1 A X"
set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hvl__conb_1 HI"
set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hvl__conb_1 LO"
diff --git a/sky130/openlane/sky130_fd_sc_ls/config.tcl b/sky130/openlane/sky130_fd_sc_ls/config.tcl
index e77d34e..86e4fd4 100755
--- a/sky130/openlane/sky130_fd_sc_ls/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_ls/config.tcl
@@ -30,11 +30,11 @@
set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_ls__decap_4"
# defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_ls__inv_8"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_ls__inv_1"
#capacitance : 0.017653;
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
# update these
-set ::env(SYNTH_CAP_LOAD) "22.050" ; # femtofarad _inv_8 pin A cap
+set ::env(SYNTH_CAP_LOAD) "46.690" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls/blob/main/cells/inv/sky130_fd_sc_ls__inv_16__tt_100C_1v80.lib.json)
set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_ls__buf_2 A X"
set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_ls__conb_1 HI"
set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_ls__conb_1 LO"
diff --git a/sky130/openlane/sky130_fd_sc_ms/config.tcl b/sky130/openlane/sky130_fd_sc_ms/config.tcl
index dc3ca5b..9f2531b 100755
--- a/sky130/openlane/sky130_fd_sc_ms/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_ms/config.tcl
@@ -30,7 +30,7 @@
set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_ms__decap_4"
# defaults (can be overridden by designs):
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_ms__inv_8"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_ms__inv_1"
#capacitance : 0.017653;
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
# update these
