commit 4ddcc61de302ddf8a6706e813d31a5f7c468669f
author agorararmard <aagouhar@efabless.com> Thu Oct 08 17:05:03 2020 +0200
committer Tim Edwards <tim@opencircuitdesign.com> Tue Oct 20 16:42:00 2020 -0400
tree 5abd04ca7b3b16def598d61a4b6a93c98d095eae
parent 97ffd66fd882290f90d4ec6c22d2715009d94aea

openlane config updates (PR #30 and #31):

-    no_synth.cells cleanup
-    first go at no_synth.cells reduction
-    variables cleanup
-    core_ring support
-    Initial attempt at creating a more generic common_pdn.tcl (covering macros and cores)

sky130/openlane/common_pdn.tcl

diff --git a/sky130/openlane/common_pdn.tcl b/sky130/openlane/common_pdn.tcl
index 51f9329..a7a271b 100644
--- a/sky130/openlane/common_pdn.tcl
+++ b/sky130/openlane/common_pdn.tcl
@@ -4,10 +4,11 @@
 
 set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
 
-pdngen::specify_grid stdcell {
+# Used if the design is the core of the chip
+set stdcell_core {
     name grid
     rails {
-	    met1 {width $::env(PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+	    met1 {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)}
     }
     straps {
 	    met4 {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
@@ -16,6 +17,42 @@
     connect {{met1 met4} {met4 met5}}
 }
 
+# Used if the design is a macro in the core
+set stdcell_macro {
+    name grid
+    rails {
+	    met1 {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)}
+    }
+    straps {
+	    met4 {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+    }
+    connect {{met1 met4}}
+}
+
+# Assesses whether the deisgn is the core of the chip or not based on the value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
+if { [info exists ::env(DESIGN_IS_CORE)] } {
+    if { $::env(DESIGN_IS_CORE) == 1 } {
+        set stdcell $stdcell_core
+    } else {
+        set stdcell $stdcell_macro
+    }
+} else {
+    set stdcell $stdcell_core
+}
+
+# Adds the core ring if enabled.
+if { [info exists ::env(FP_PDN_CORE_RING)] } {
+    if { $::env(FP_PDN_CORE_RING) == 1 } {
+        dict append stdcell core_ring {
+                met4 {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)}
+                met5 {width $::env(FP_PDN_CORE_RING_HWIDTH) spacing $::env(FP_PDN_CORE_RING_HSPACING) core_offset $::env(FP_PDN_CORE_RING_HOFFSET)}
+            }
+    }
+}
+
+pdngen::specify_grid stdcell $stdcell
+
+# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
 pdngen::specify_grid macro {
     orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
     power_pins "VDDE"
@@ -23,7 +60,7 @@
     blockages "li1 met1 met2 met3 met4 met5" 
     straps { 
     } 
-    connect { }
+    connect {{met4_PIN_ver met5}}
 }
 
 set ::halo 0