Made a small change to the library compiler scripts so that if they are presented with a single already-compiled library file, they keep it rather than delete it. Also: Revised the gf180mcu Makefile to correct for the complete change in structure of the OSU 3.3V library repository. The OSU standard cell libraries should now compile and install properly again.
diff --git a/VERSION b/VERSION index 1eb314e..d1e8534 100644 --- a/VERSION +++ b/VERSION
@@ -1 +1 @@ -1.0.538 +1.0.539
diff --git a/common/create_gds_library.py b/common/create_gds_library.py index 6c5235a..96874bc 100755 --- a/common/create_gds_library.py +++ b/common/create_gds_library.py
@@ -66,7 +66,7 @@ glist = natural_sort.natural_sort(glist) - if alllibname in glist: + if alllibname in glist and len(glist) != 1: glist.remove(alllibname) # Create exclude list with glob-style matching using fnmatch
diff --git a/common/create_lef_library.py b/common/create_lef_library.py index 3834296..7c9f5cc 100755 --- a/common/create_lef_library.py +++ b/common/create_lef_library.py
@@ -56,7 +56,7 @@ llist = glob.glob(destlibdir + '/*.lef') llist = natural_sort.natural_sort(llist) - if alllibname in llist: + if alllibname in llist and len(llist) != 1: llist.remove(alllibname) # Create exclude list with glob-style matching using fnmatch
diff --git a/common/create_spice_library.py b/common/create_spice_library.py index b2ed037..c145c5f 100755 --- a/common/create_spice_library.py +++ b/common/create_spice_library.py
@@ -77,7 +77,7 @@ slist = natural_sort.natural_sort(slist) - if alllibname in slist: + if alllibname in slist and len(slist) != 1: slist.remove(alllibname) if allstubname in slist:
diff --git a/common/create_verilog_library.py b/common/create_verilog_library.py index 39d671b..d5aa63c 100755 --- a/common/create_verilog_library.py +++ b/common/create_verilog_library.py
@@ -65,7 +65,7 @@ vlist = glob.glob(destlibdir + '/*.v') vlist = natural_sort.natural_sort(vlist) - if alllibname in vlist: + if alllibname in vlist and len(vlist) != 1: vlist.remove(alllibname) # Create exclude list with glob-style matching using fnmatch
diff --git a/common/foundry_install.py b/common/foundry_install.py index ddbf5f7..5a53278 100755 --- a/common/foundry_install.py +++ b/common/foundry_install.py
@@ -89,7 +89,7 @@ # stub : Remove contents of subcircuits from CDL or SPICE # netlist files. # -# priv : Mark the contents being installed as privleged, and +# priv : Mark the contents being installed as privileged, and # put them in a separate root directory libs.priv # where they can be given additional read/write # restrictions.
diff --git a/gf180mcu/Makefile.in b/gf180mcu/Makefile.in index 59fa46b..1872dfc 100644 --- a/gf180mcu/Makefile.in +++ b/gf180mcu/Makefile.in
@@ -1132,11 +1132,11 @@ rename=gf180mcu_osu_sc_gp9t3v3__nom.tlef \ -lib lib/gf180mcu_osu_sc_gp9t3v3_TT_25C.ccs.lib \ rename=gf180mcu_osu_sc_gp9t3v3__tt_025C_3v30 \ - -verilog cells/*/*.v compile-only \ - -lef cells/*/*.lef compile-only \ - -gds cells/*/*.gds compile-only \ - -spice cells/*/*.spice compile-only \ - -xschem cells/*/*.sch \ + -verilog verilog/*.v rename=gf180mcu_osu_sc_gp9t3v3.v \ + -lef lef/*.lef \ + -gds gds/*.gds compile-only \ + -spice spice/*.spice \ + -xschem xschem/*.sch compile-only \ -library digital gf180mcu_osu_sc_gp9t3v3 2>&1 | \ tee -a ${GF180MCU$*}_make.log @@ -1146,11 +1146,11 @@ rename=gf180mcu_osu_sc_gp12t3v3__nom.tlef \ -lib lib/gf180mcu_osu_sc_gp12t3v3_TT_25C.ccs.lib \ rename=gf180mcu_osu_sc_gp12t3v3__tt_025C_3v30 \ - -verilog cells/*/*.v compile-only \ - -lef cells/*/*.lef compile-only \ - -gds cells/*/*.gds compile-only \ - -spice cells/*/*.spice compile-only \ - -xschem cells/*/*.sch \ + -verilog verilog/*.v rename=gf180mcu_osu_sc_gp12t3v3.v \ + -lef lef/*.lef \ + -gds gds/*.gds compile-only \ + -spice spice/*.spice \ + -xschem xschem/*.sch \ -library digital gf180mcu_osu_sc_gp12t3v3 2>&1 | \ tee -a ${GF180MCU$*}_make.log