diff --git a/VERSION b/VERSION
index ea38dc4..797f1f6 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.168
+1.0.169
diff --git a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
index 6a31b41..d1045f7 100644
--- a/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
+++ b/sky130/custom/sky130_fd_io/cdl/sky130_ef_io.cdl
@@ -569,4 +569,26 @@
 
 .ENDS
 
+*----------------------------------------------------------
+* sky130_ef_io__top_power_hvc
+* Power pad instantiates top_power_hvc_wpadv2 unchanged
+* except for tripling the amount of metal at the core
+* connection, for high-current supply applications.
+*----------------------------------------------------------
+
+.SUBCKT sky130_ef_io__top_power_hvc
++ AMUXBUS_A AMUXBUS_B DRN_HVC P_CORE P_PAD
++ SRC_BDY_HVC VCCD_PAD VSSA VDDA VSWITCH VDDIO_Q VCCHIB
++ VDDIO VCCD VSSIO VSSD VSSIO_Q
+
+* Instantiate the underlying power pad (connects P_PAD to VCCD)
+Xsky130_fd_io__top_power_hvc_base
++ AMUXBUS_A AMUXBUS_B DRN_HVC VDDIO
++ P_CORE P_PAD
++ SRC_BDY_HVC VCCD VCCHIB VDDA VDDIO VDDIO_Q
++ VSSA VSSD VSSIO VSSIO_Q VSWITCH
++ sky130_fd_io__top_power_hvc_wpadv2
+
+.ENDS
+
 *--------------------------------------------------------------------------
diff --git a/sky130/custom/sky130_fd_io/gds/sky130_ef_io.gds b/sky130/custom/sky130_fd_io/gds/sky130_ef_io.gds
index 7395c7c..d46ab8c 100644
--- a/sky130/custom/sky130_fd_io/gds/sky130_ef_io.gds
+++ b/sky130/custom/sky130_fd_io/gds/sky130_ef_io.gds
Binary files differ
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__top_power_hvc.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__top_power_hvc.lef
new file mode 100644
index 0000000..7106209
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__top_power_hvc.lef
@@ -0,0 +1,421 @@
+VERSION 5.7 ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+MACRO sky130_ef_io__top_power_hvc
+  CLASS PAD POWER ;
+  FOREIGN sky130_ef_io__top_power_hvc ;
+  ORIGIN 0.000 -47.000 ;
+  SIZE 169.000 BY 197.965 ;
+  PIN AMUXBUS_A
+    DIRECTION INOUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 0.000 98.090 169.000 101.070 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 98.090 1.270 101.070 ;
+    END
+  END AMUXBUS_A
+  PIN AMUXBUS_B
+    DIRECTION INOUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER met4 ;
+        RECT 0.000 93.330 169.000 96.310 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 93.330 1.270 96.310 ;
+    END
+  END AMUXBUS_B
+  PIN DRN_HVC
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met2 ;
+        RECT 97.390 44.965 121.290 70.625 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 84.890 44.965 95.890 56.295 ;
+    END
+  END DRN_HVC
+  PIN P_CORE
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met3 ;
+        RECT 0.000 44.965 71.395 60.650 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 97.390 44.965 169.000 60.650 ;
+    END
+  END P_CORE
+  PIN P_PAD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 54.050 150.085 114.890 210.910 ;
+    END
+  END P_PAD
+  PIN SRC_BDY_HVC
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met2 ;
+        RECT 47.495 44.965 71.395 47.020 ;
+    END
+    PORT
+      LAYER met3 ;
+        RECT 72.895 44.965 83.895 47.690 ;
+    END
+  END SRC_BDY_HVC
+  PIN VSSA
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 92.700 169.000 101.700 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 125.885 81.800 169.000 85.050 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 96.610 169.000 97.790 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 101.370 169.000 101.700 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 92.700 169.000 93.030 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 81.700 169.000 85.150 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 92.700 47.240 101.700 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 81.800 47.715 85.050 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 92.700 1.270 93.030 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 96.610 47.240 97.790 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 101.370 1.270 101.700 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 81.700 47.715 85.150 ;
+    END
+  END VSSA
+  PIN VDDA
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 121.205 60.000 169.000 63.250 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.205 59.900 169.000 63.350 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 60.000 47.715 63.250 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 59.900 47.715 63.350 ;
+    END
+  END VDDA
+  PIN VSWITCH
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 76.950 169.000 80.200 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 76.850 169.000 80.300 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 76.950 47.715 80.200 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 76.850 47.715 80.300 ;
+    END
+  END VSWITCH
+  PIN VDDIO_Q
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 109.150 169.000 113.400 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 109.050 169.000 113.500 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 109.150 47.715 113.400 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 109.050 47.715 113.500 ;
+    END
+  END VDDIO_Q
+  PIN VCCHIB
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 47.100 169.000 52.350 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 47.000 169.000 52.450 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 47.100 47.715 52.350 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 47.000 47.715 52.450 ;
+    END
+  END VCCHIB
+  PIN VDDIO
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 115.000 169.000 139.950 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 125.885 64.850 169.000 69.300 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 121.205 64.750 169.000 69.400 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 115.000 169.000 139.965 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 115.000 47.715 139.950 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 64.850 47.715 69.300 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 64.750 47.715 69.400 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 115.000 47.715 139.965 ;
+    END
+  END VDDIO
+  PIN VCCD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 53.950 169.000 58.400 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 53.850 169.000 58.500 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 53.950 47.715 58.400 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 53.850 47.715 58.500 ;
+    END
+  END VCCD
+  PIN VSSIO
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met4 ;
+        RECT 128.245 220.750 169.000 244.965 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 168.360 236.565 168.370 236.575 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 125.885 70.900 169.000 75.350 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 70.800 169.000 75.450 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 167.730 220.750 169.000 244.965 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 220.750 48.205 244.965 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.630 236.565 0.640 236.575 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 70.900 47.715 75.350 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 220.750 1.270 244.965 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 70.800 47.715 75.450 ;
+    END
+  END VSSIO
+  PIN VSSD
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 86.650 169.000 91.100 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 86.550 169.000 91.200 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 86.650 47.715 91.100 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 86.550 47.250 91.200 ;
+    END
+  END VSSD
+  PIN VSSIO_Q
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER met5 ;
+        RECT 125.885 103.300 169.000 107.550 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 125.885 103.200 169.000 107.650 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 103.300 47.715 107.550 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 103.200 47.715 107.650 ;
+    END
+  END VSSIO_Q
+  OBS
+      LAYER pwell ;
+        RECT 50.495 45.900 58.285 68.755 ;
+      LAYER nwell ;
+        RECT 58.860 45.650 117.965 47.170 ;
+      LAYER li1 ;
+        RECT 47.610 47.000 119.855 244.660 ;
+        RECT 47.610 46.030 58.155 47.000 ;
+        RECT 59.035 46.885 60.045 47.000 ;
+        RECT 116.730 46.885 117.680 47.000 ;
+        RECT 59.035 45.935 117.680 46.885 ;
+      LAYER met1 ;
+        RECT 47.185 47.000 119.915 244.690 ;
+        RECT 50.625 46.095 55.855 47.000 ;
+        RECT 59.035 46.885 60.350 47.000 ;
+        POLYGON 60.350 47.000 60.465 46.885 60.350 46.885 ;
+        POLYGON 116.540 47.000 116.540 46.885 116.425 46.885 ;
+        RECT 116.540 46.885 117.680 47.000 ;
+        RECT 59.035 45.935 117.680 46.885 ;
+      LAYER met2 ;
+        RECT 47.265 70.905 121.290 240.040 ;
+        RECT 47.265 47.300 97.110 70.905 ;
+        RECT 71.675 47.000 97.110 47.300 ;
+        RECT 72.895 44.965 74.895 46.885 ;
+      LAYER met3 ;
+        RECT 0.000 61.050 169.000 244.965 ;
+        RECT 0.000 60.650 21.535 61.050 ;
+        RECT 71.795 56.695 96.990 61.050 ;
+        RECT 71.795 48.090 84.490 56.695 ;
+        RECT 71.795 47.690 72.495 48.090 ;
+        RECT 84.295 47.690 84.490 48.090 ;
+        RECT 96.290 47.690 96.990 56.695 ;
+      LAYER met4 ;
+        RECT 48.605 220.350 127.845 244.965 ;
+        RECT 47.240 140.365 128.245 220.350 ;
+        RECT 48.115 114.600 125.485 140.365 ;
+        RECT 47.240 113.900 128.245 114.600 ;
+        RECT 48.115 108.650 125.485 113.900 ;
+        RECT 47.240 108.050 128.245 108.650 ;
+        RECT 48.115 102.800 125.485 108.050 ;
+        RECT 47.240 102.100 128.245 102.800 ;
+        RECT 47.640 96.710 125.485 97.690 ;
+        RECT 47.240 91.600 128.245 92.300 ;
+        RECT 47.650 86.150 125.485 91.600 ;
+        RECT 47.240 85.550 128.245 86.150 ;
+        RECT 48.115 81.300 125.485 85.550 ;
+        RECT 47.240 80.700 128.245 81.300 ;
+        RECT 48.115 76.450 125.485 80.700 ;
+        RECT 47.240 75.850 128.245 76.450 ;
+        RECT 48.115 70.400 125.485 75.850 ;
+        RECT 47.240 69.800 128.245 70.400 ;
+        RECT 48.115 64.350 120.805 69.800 ;
+        RECT 47.240 63.750 128.245 64.350 ;
+        RECT 48.115 59.500 120.805 63.750 ;
+        RECT 47.240 58.900 128.245 59.500 ;
+        RECT 48.115 53.450 125.485 58.900 ;
+        RECT 47.240 52.850 128.245 53.450 ;
+        RECT 48.115 47.000 125.485 52.850 ;
+      LAYER met5 ;
+        RECT 0.000 212.510 169.000 244.965 ;
+        RECT 0.000 148.485 52.450 212.510 ;
+        RECT 116.490 148.485 169.000 212.510 ;
+        RECT 0.000 141.550 169.000 148.485 ;
+        RECT 49.315 101.700 124.285 141.550 ;
+        RECT 48.840 92.700 124.285 101.700 ;
+        RECT 49.315 64.850 124.285 92.700 ;
+        RECT 49.315 58.400 119.605 64.850 ;
+        RECT 49.315 47.100 124.285 58.400 ;
+  END
+END sky130_ef_io__top_power_hvc
+END LIBRARY
+
diff --git a/sky130/custom/sky130_fd_io/mag/sky130_ef_io__top_power_hvc.mag b/sky130/custom/sky130_fd_io/mag/sky130_ef_io__top_power_hvc.mag
new file mode 100644
index 0000000..090c2ad
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/sky130_ef_io__top_power_hvc.mag
@@ -0,0 +1,338 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622214379
+<< error_s >>
+rect 11669 43353 11682 43589
+rect 22118 43573 22142 43589
+rect 22142 43353 22145 43573
+rect 11350 43265 11583 43281
+rect 11347 43062 11350 43265
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+rect 22504 42991 22507 43211
+rect 11030 42945 11147 42961
+rect 11027 42725 11030 42945
+rect 22591 42891 22824 42907
+rect 22824 42671 22827 42891
+rect 10710 42625 10943 42641
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+rect 10384 42291 10387 42302
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+rect 22450 28881 22453 29101
+rect 22217 28865 22450 28881
+rect 11655 28573 11658 28793
+rect 11658 28557 11682 28573
+rect 22118 28557 22131 28793
+<< metal2 >>
+rect 9499 8993 14279 9141
+rect 14579 8993 14979 9189
+rect 19478 8993 24258 9141
+<< metal3 >>
+tri 0 36705 6919 43624 se
+rect 6919 36705 9579 43624
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+rect 5093 12130 8904 12327
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+rect 9499 12130 9579 12330
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+rect 24146 9384 33800 12130
+rect 0 8993 14279 9384
+rect 14579 8993 16779 9141
+rect 16978 8993 19178 9311
+rect 19478 8993 33800 9384
+<< metal4 >>
+rect 0 44150 254 48993
+rect 33546 44150 33800 48993
+rect 0 23000 254 27993
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+rect 0 10770 254 11700
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+rect 0 9400 254 10490
+rect 33546 9400 33800 10490
+<< metal5 >>
+rect 0 44150 254 48993
+rect 33546 44150 33800 48993
+rect 16729 36858 16994 38180
+rect 0 23000 254 27990
+rect 33546 23000 33800 27990
+rect 0 21830 254 22680
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+rect 33546 12000 33800 12650
+rect 0 10790 254 11680
+rect 33546 10790 33800 11680
+rect 0 9420 254 10470
+rect 33546 9420 33800 10470
+use sky130_ef_io__com_bus_slice_1um  sky130_ef_io__com_bus_slice_1um_2
+timestamp 1576684134
+transform 1 0 0 0 1 9400
+box 0 0 200 39593
+use sky130_ef_io__com_bus_slice_1um  sky130_ef_io__com_bus_slice_1um_3
+timestamp 1576684134
+transform 1 0 200 0 1 9400
+box 0 0 200 39593
+use sky130_ef_io__com_bus_slice_5um  sky130_ef_io__com_bus_slice_5um_1
+timestamp 1602609416
+transform 1 0 400 0 1 9400
+box 0 0 1000 39593
+use sky130_ef_io__com_bus_slice_20um  sky130_ef_io__com_bus_slice_20um_2
+timestamp 1602609570
+transform 1 0 1400 0 1 9400
+box 0 0 4000 39593
+use sky130_ef_io__com_bus_slice_20um  sky130_ef_io__com_bus_slice_20um_3
+timestamp 1602609570
+transform 1 0 5400 0 1 9400
+box 0 0 4000 39593
+use sky130_fd_io__top_power_hvc_wpadv2  sky130_fd_io__top_power_hvc_wpadv2_1 $PDKPATH/libs.ref/sky130_fd_io/mag
+timestamp 1622147639
+transform 1 0 9400 0 1 8993
+box 0 0 15000 40000
+use sky130_ef_io__com_bus_slice_20um  sky130_ef_io__com_bus_slice_20um_0
+timestamp 1602609570
+transform 1 0 24400 0 1 9400
+box 0 0 4000 39593
+use sky130_ef_io__com_bus_slice_20um  sky130_ef_io__com_bus_slice_20um_1
+timestamp 1602609570
+transform 1 0 28400 0 1 9400
+box 0 0 4000 39593
+use sky130_ef_io__com_bus_slice_5um  sky130_ef_io__com_bus_slice_5um_0
+timestamp 1602609416
+transform 1 0 32400 0 1 9400
+box 0 0 1000 39593
+use sky130_ef_io__com_bus_slice_1um  sky130_ef_io__com_bus_slice_1um_0
+timestamp 1576684134
+transform 1 0 33400 0 1 9400
+box 0 0 200 39593
+use sky130_ef_io__com_bus_slice_1um  sky130_ef_io__com_bus_slice_1um_1
+timestamp 1576684134
+transform 1 0 33600 0 1 9400
+box 0 0 200 39593
+<< labels >>
+flabel metal2 s 19478 8993 24258 9141 2 FreeSans 2000 90 0 0 DRN_HVC
+port 2 nsew power bidirectional
+flabel metal2 s 9499 8993 14279 9141 2 FreeSans 2000 90 0 0 SRC_BDY_HVC
+port 5 nsew ground bidirectional
+flabel metal3 s 16978 8993 19178 9311 0 FreeSans 2000 0 0 0 DRN_HVC
+port 2 nsew power bidirectional
+flabel metal3 s 14579 8993 16779 9141 2 FreeSans 2000 90 0 0 SRC_BDY_HVC
+port 5 nsew ground bidirectional
+flabel metal3 s 0 8993 14279 9384 0 FreeSans 2000 0 0 0 P_CORE
+port 3 nsew power bidirectional
+flabel metal3 s 19478 8993 33757 9384 0 FreeSans 2000 0 0 0 P_CORE
+port 3 nsew power bidirectional
+flabel metal5 s 16729 36858 16994 38180 0 FreeSans 2000 0 0 0 P_PAD
+port 4 nsew power bidirectional
+flabel metal4 s 33673 47325 33673 47325 3 FreeSans 520 180 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal4 s 33673 47314 33673 47314 3 FreeSans 520 180 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal5 s 33546 18540 33800 20340 3 FreeSans 520 180 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal5 s 33607 12000 33800 12650 3 FreeSans 520 180 0 0 VDDA
+port 8 nsew power bidirectional
+flabel metal5 s 33546 17330 33800 18220 3 FreeSans 520 180 0 0 VSSD
+port 15 nsew ground bidirectional
+flabel metal5 s 33546 20660 33800 21510 3 FreeSans 520 180 0 0 VSSIO_Q
+port 16 nsew ground bidirectional
+flabel metal5 s 33546 14180 33800 15070 3 FreeSans 520 180 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal5 s 33546 15390 33800 16040 3 FreeSans 520 180 0 0 VSWITCH
+port 9 nsew power bidirectional
+flabel metal5 s 33546 16361 33800 17010 3 FreeSans 520 180 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal5 s 33546 10790 33800 11680 3 FreeSans 520 180 0 0 VCCD
+port 13 nsew power bidirectional
+flabel metal5 s 33546 21830 33800 22680 3 FreeSans 520 180 0 0 VDDIO_Q
+port 10 nsew power bidirectional
+flabel metal5 s 33546 23000 33800 27990 3 FreeSans 520 180 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal5 s 33546 9420 33800 10470 3 FreeSans 520 180 0 0 VCCHIB
+port 11 nsew power bidirectional
+flabel metal5 s 33546 12970 33800 13860 3 FreeSans 520 180 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal4 s 33546 17310 33800 18240 3 FreeSans 520 180 0 0 VSSD
+port 15 nsew ground bidirectional
+flabel metal4 s 33607 11980 33800 12670 3 FreeSans 520 180 0 0 VDDA
+port 8 nsew power bidirectional
+flabel metal4 s 33546 20640 33800 21530 3 FreeSans 520 180 0 0 VSSIO_Q
+port 16 nsew ground bidirectional
+flabel metal4 s 33546 14160 33800 15090 3 FreeSans 520 180 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal4 s 33546 15370 33800 16060 3 FreeSans 520 180 0 0 VSWITCH
+port 9 nsew power bidirectional
+flabel metal4 s 33546 19322 33800 19558 3 FreeSans 520 180 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 33546 20274 33800 20340 3 FreeSans 520 180 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 33546 9400 33800 10490 3 FreeSans 520 180 0 0 VCCHIB
+port 11 nsew power bidirectional
+flabel metal4 s 33546 12950 33800 13880 3 FreeSans 520 180 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal4 s 33546 18540 33800 18606 3 FreeSans 520 180 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 33546 16340 33800 17030 3 FreeSans 520 180 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 33546 21810 33800 22700 3 FreeSans 520 180 0 0 VDDIO_Q
+port 10 nsew power bidirectional
+flabel metal4 s 33546 10770 33800 11700 3 FreeSans 520 180 0 0 VCCD
+port 13 nsew power bidirectional
+flabel metal4 s 33546 18666 33800 19262 3 FreeSans 520 180 0 0 AMUXBUS_B
+port 1 nsew signal bidirectional
+flabel metal4 s 33546 44150 33800 48993 3 FreeSans 520 180 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal4 s 33546 19618 33800 20214 3 FreeSans 520 180 0 0 AMUXBUS_A
+port 0 nsew signal bidirectional
+flabel metal4 s 33546 23000 33800 27993 3 FreeSans 520 180 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal4 s 127 47325 127 47325 3 FreeSans 520 0 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal4 s 127 47314 127 47314 3 FreeSans 520 0 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal5 s 0 23000 254 27990 3 FreeSans 520 0 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal5 s 0 17330 254 18220 3 FreeSans 520 0 0 0 VSSD
+port 15 nsew ground bidirectional
+flabel metal5 s 0 20660 254 21510 3 FreeSans 520 0 0 0 VSSIO_Q
+port 16 nsew ground bidirectional
+flabel metal5 s 0 15390 254 16040 3 FreeSans 520 0 0 0 VSWITCH
+port 9 nsew power bidirectional
+flabel metal5 s 0 14180 254 15070 3 FreeSans 520 0 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal5 s 0 12000 193 12650 3 FreeSans 520 0 0 0 VDDA
+port 8 nsew power bidirectional
+flabel metal5 s 0 12970 254 13860 3 FreeSans 520 0 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal5 s 0 10790 254 11680 3 FreeSans 520 0 0 0 VCCD
+port 13 nsew power bidirectional
+flabel metal5 s 0 21830 254 22680 3 FreeSans 520 0 0 0 VDDIO_Q
+port 10 nsew power bidirectional
+flabel metal5 s 0 18540 254 20340 3 FreeSans 520 0 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal5 s 0 16361 254 17010 3 FreeSans 520 0 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal5 s 0 9420 254 10470 3 FreeSans 520 0 0 0 VCCHIB
+port 11 nsew power bidirectional
+flabel metal4 s 0 44150 254 48993 3 FreeSans 520 0 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal4 s 0 12950 254 13880 3 FreeSans 520 0 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal4 s 0 21810 254 22700 3 FreeSans 520 0 0 0 VDDIO_Q
+port 10 nsew power bidirectional
+flabel metal4 s 0 23000 254 27993 3 FreeSans 520 0 0 0 VDDIO
+port 12 nsew power bidirectional
+flabel metal4 s 0 10770 254 11700 3 FreeSans 520 0 0 0 VCCD
+port 13 nsew power bidirectional
+flabel metal4 s 0 18540 254 18606 3 FreeSans 520 0 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 0 15370 254 16060 3 FreeSans 520 0 0 0 VSWITCH
+port 9 nsew power bidirectional
+flabel metal4 s 0 9400 254 10490 3 FreeSans 520 0 0 0 VCCHIB
+port 11 nsew power bidirectional
+flabel metal4 s 0 19322 254 19558 3 FreeSans 520 0 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 0 20640 254 21530 3 FreeSans 520 0 0 0 VSSIO_Q
+port 16 nsew ground bidirectional
+flabel metal4 s 0 14160 254 15090 3 FreeSans 520 0 0 0 VSSIO
+port 14 nsew ground bidirectional
+flabel metal4 s 0 11980 193 12670 3 FreeSans 520 0 0 0 VDDA
+port 8 nsew power bidirectional
+flabel metal4 s 0 19618 254 20214 3 FreeSans 520 0 0 0 AMUXBUS_A
+port 0 nsew signal bidirectional
+flabel metal4 s 0 20274 254 20340 3 FreeSans 520 0 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 0 16340 254 17030 3 FreeSans 520 0 0 0 VSSA
+port 7 nsew ground bidirectional
+flabel metal4 s 0 17310 254 18240 3 FreeSans 520 0 0 0 VSSD
+port 15 nsew ground bidirectional
+flabel metal4 s 0 18666 254 19262 3 FreeSans 520 0 0 0 AMUXBUS_B
+port 1 nsew signal bidirectional
+<< properties >>
+string LEFclass PAD POWER
+string FIXED_BBOX 0 9400 33800 48993
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
index aa9f681..57e2655 100644
--- a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
+++ b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
@@ -11,7 +11,7 @@
 
 module sky130_ef_io__vccd_hvc_pad (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
 	SRC_BDY_HVC, VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VCCD_PAD, VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -22,6 +22,7 @@
   inout VDDIO_Q;
   inout VDDA;
   inout VCCD;
+  inout VCCD_PAD;
   inout VSWITCH;
   inout VCCHIB;
   inout VSSA;
@@ -41,7 +42,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VCCD),
+	.P_CORE(VCCD),
+	.P_PAD(PAD_VCCD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -53,7 +55,7 @@
 
 module sky130_ef_io__vccd_lvc_pad (AMUXBUS_A, AMUXBUS_B,
 	DRN_LVC1, DRN_LVC2, SRC_BDY_LVC1, SRC_BDY_LVC2, BDY2_B2B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VCCD_PAD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -68,6 +70,7 @@
   inout VDDIO_Q;	
   inout VDDA;
   inout VCCD;
+  inout VCCD_PAD;
   inout VSWITCH;
   inout VCCHIB;
   inout VSSA;
@@ -87,7 +90,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VCCD),
+	.P_CORE(VCCD),
+	.P_PAD(VCCD_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(BDY2_B2B),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -102,7 +106,7 @@
 
 module sky130_ef_io__vdda_lvc_pad (AMUXBUS_A, AMUXBUS_B,
 	DRN_LVC1, DRN_LVC2, SRC_BDY_LVC1, SRC_BDY_LVC2, BDY2_B2B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VDDA, VDDA_PAD, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -116,6 +120,7 @@
   inout VDDIO;	
   inout VDDIO_Q;	
   inout VDDA;
+  inout VDDA_PAD;
   inout VCCD;
   inout VSWITCH;
   inout VCCHIB;
@@ -136,7 +141,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VDDA),
+	.P_CORE(VDDA),
+	.P_PAD(VDDA_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(BDY2_B2B),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -150,8 +156,8 @@
 endmodule
 
 module sky130_ef_io__vdda_hvc_pad (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
-	SRC_BDY_HVC,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	SRC_BDY_HVC,VSSA, VDDA, VDDA_PAD, VSWITCH, VDDIO_Q, VCCHIB,
+	VDDIO, VCCD, VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -161,6 +167,7 @@
   inout VDDIO;	
   inout VDDIO_Q;	
   inout VDDA;
+  inout VDDA_PAD;
   inout VCCD;
   inout VSWITCH;
   inout VCCHIB;
@@ -181,7 +188,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VDDA),
+	.P_CORE(VDDA),
+	.P_PAD(VDDA_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -193,7 +201,7 @@
 
 module sky130_ef_io__vddio_lvc_pad (AMUXBUS_A, AMUXBUS_B,
 	DRN_LVC1, DRN_LVC2, SRC_BDY_LVC1, SRC_BDY_LVC2, BDY2_B2B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VDDIO_PAD, VCCD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -205,6 +213,7 @@
   inout SRC_BDY_LVC2;
   inout BDY2_B2B;
   inout VDDIO;	
+  inout VDDIO_PAD;	
   inout VDDIO_Q;	
   inout VDDA;
   inout VCCD;
@@ -227,7 +236,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VDDIO),
+	.P_CORE(VDDIO),
+	.P_PAD(VDDIO_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(BDY2_B2B),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -243,8 +253,8 @@
 endmodule
 
 module sky130_ef_io__vddio_hvc_pad (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
-	SRC_BDY_HVC,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	SRC_BDY_HVC,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO,
+	VDDIO_PAD, VCCD, VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -252,6 +262,7 @@
   inout DRN_HVC;
   inout SRC_BDY_HVC;
   inout VDDIO;	
+  inout VDDIO_PAD;	
   inout VDDIO_Q;	
   inout VDDA;
   inout VCCD;
@@ -274,7 +285,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VDDIO),
+	.P_CORE(VDDIO),
+	.P_PAD(VDDIO_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -289,7 +301,7 @@
 module sky130_ef_io__vssd_lvc_pad (AMUXBUS_A, AMUXBUS_B,
 	DRN_LVC1, DRN_LVC2, SRC_BDY_LVC1, SRC_BDY_LVC2, BDY2_B2B,
 	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VSSIO, VSSD, VSSD_PAD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -307,6 +319,7 @@
   inout VCCHIB;
   inout VSSA;
   inout VSSD;
+  inout VSSD_PAD;
   inout VSSIO_Q;
   inout VSSIO;
 
@@ -322,7 +335,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSD),
+	.G_CORE(VSSD),
+	.G_PAD(VSSD_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(BDY2_B2B),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -337,7 +351,7 @@
 
 module sky130_ef_io__vssd_hvc_pad (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
 	SRC_BDY_HVC, VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VSSIO, VSSD, VSSD_PAD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -352,6 +366,7 @@
   inout VCCHIB;
   inout VSSA;
   inout VSSD;
+  inout VSSD_PAD;
   inout VSSIO_Q;
   inout VSSIO;
 
@@ -367,7 +382,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSD),
+	.G_CORE(VSSD),
+	.G_PAD(VSSD_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -380,7 +396,7 @@
 module sky130_ef_io__vssio_lvc_pad (AMUXBUS_A, AMUXBUS_B,
 	DRN_LVC1, DRN_LVC2, SRC_BDY_LVC1, SRC_BDY_LVC2, BDY2_B2B,
 	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VSSIO, VSSIO_PAD, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -400,6 +416,7 @@
   inout VSSD;
   inout VSSIO_Q;
   inout VSSIO;
+  inout VSSIO_PAD;
 
   // Instantiate the underlying ground pad (connects G_PAD and VSSIO_Q to VSSIO)
   sky130_fd_io__top_ground_lvc_wpad sky130_fd_io__top_ground_lvc_base ( 
@@ -413,7 +430,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSIO),
+	.G_CORE(VSSIO),
+	.G_PAD(VSSIO_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(BDY2_B2B),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -431,7 +449,7 @@
 
 module sky130_ef_io__vssio_hvc_pad (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
 	SRC_BDY_HVC,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VSSIO, VSSIO_PAD, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -448,6 +466,7 @@
   inout VSSD;
   inout VSSIO_Q;
   inout VSSIO;
+  inout VSSIO_PAD;
 
   // Instantiate the underlying ground pad (connects G_PAD and VSSIO_Q to VSSIO)
   sky130_fd_io__top_ground_hvc_wpad sky130_fd_io__top_ground_hvc_base ( 
@@ -461,7 +480,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSIO),
+	.G_CORE(VSSIO),
+	.G_PAD(VSSIO_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -475,7 +495,7 @@
 
 module sky130_ef_io__vssa_lvc_pad (AMUXBUS_A, AMUXBUS_B,
 	DRN_LVC1, DRN_LVC2, SRC_BDY_LVC1, SRC_BDY_LVC2, BDY2_B2B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VSSA_PAD, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -493,6 +513,7 @@
   inout VSWITCH;
   inout VCCHIB;
   inout VSSA;
+  inout VSSA_PAD;
   inout VSSD;
   inout VSSIO_Q;
   inout VSSIO;
@@ -509,7 +530,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSA),
+	.G_CORE(VSSA),
+	.G_PAD(VSSA_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(BDY2_B2B),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -523,8 +545,8 @@
 endmodule
 
 module sky130_ef_io__vssa_hvc_pad (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
-	SRC_BDY_HVC,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	SRC_BDY_HVC,VSSA, VSSA_PAD, VDDA, VSWITCH, VDDIO_Q, VCCHIB,
+	VDDIO, VCCD, VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -538,6 +560,7 @@
   inout VSWITCH;
   inout VCCHIB;
   inout VSSA;
+  inout VSSA_PAD;
   inout VSSD;
   inout VSSIO_Q;
   inout VSSIO;
@@ -554,7 +577,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSA),
+	.G_CORE(VSSA),
+	.G_PAD(VSSA_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -776,13 +800,14 @@
 // sky130_ef_io__vddio_hvc_pad with HV clamp connections to VDDIO and VSSIO
 
 module sky130_ef_io__vddio_hvc_clamped_pad (AMUXBUS_A, AMUXBUS_B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VDDIO_PAD, VCCD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
 
-  inout VDDIO;	
+  inout VDDIO;
+  inout VDDIO_PAD;
   inout VDDIO_Q;	
   inout VDDA;
   inout VCCD;
@@ -805,6 +830,7 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
+	.P_CORE(VDDIO_PAD),
 	.P_PAD(VDDIO),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -821,7 +847,7 @@
 
 module sky130_ef_io__vssio_hvc_clamped_pad (AMUXBUS_A, AMUXBUS_B,
 	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VSSIO, VSSIO_PAD, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -836,6 +862,7 @@
   inout VSSD;
   inout VSSIO_Q;
   inout VSSIO;
+  inout VSSIO_PAD;
 
   // Instantiate the underlying ground pad (connects G_PAD and VSSIO_Q to VSSIO)
   sky130_fd_io__top_ground_hvc_wpad sky130_fd_io__top_ground_hvc_base ( 
@@ -849,7 +876,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSIO),
+	.G_CORE(VSSIO),
+	.G_PAD(VSSIO_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -864,7 +892,7 @@
 // sky130_ef_io__vdda_hvc_pad with HV clamp connections to VDDA and VSSA
 
 module sky130_ef_io__vdda_hvc_clamped_pad (AMUXBUS_A, AMUXBUS_B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VDDA, VDDA_PAD, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -873,6 +901,7 @@
   inout VDDIO;	
   inout VDDIO_Q;	
   inout VDDA;
+  inout VDDA_PAD;
   inout VCCD;
   inout VSWITCH;
   inout VCCHIB;
@@ -893,7 +922,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VDDA),
+	.P_CORE(VDDA),
+	.P_PAD(VDDA_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -906,7 +936,7 @@
 // sky130_ef_io__vssa_hvc_pad with HV clamp connections to VDDA and VSSA
 
 module sky130_ef_io__vssa_hvc_clamped_pad (AMUXBUS_A, AMUXBUS_B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA_PAD, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -919,6 +949,7 @@
   inout VSWITCH;
   inout VCCHIB;
   inout VSSA;
+  inout VSSA_PAD;
   inout VSSD;
   inout VSSIO_Q;
   inout VSSIO;
@@ -935,7 +966,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSA),
+	.G_CORE(VSSA),
+	.G_PAD(VSSA_PAD),
 	.OGC_HVC(),
 	.AMUXBUS_A(AMUXBUS_A),
 	.AMUXBUS_B(AMUXBUS_B),
@@ -949,7 +981,7 @@
 // and back-to-back diodes connecting VSSIO to VSSA
 
 module sky130_ef_io__vccd_lvc_clamped_pad (AMUXBUS_A, AMUXBUS_B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VCCD_PAD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -959,6 +991,7 @@
   inout VDDIO_Q;	
   inout VDDA;
   inout VCCD;
+  inout VCCD_PAD;
   inout VSWITCH;
   inout VCCHIB;
   inout VSSA;
@@ -978,7 +1011,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VCCD),
+	.P_CORE(VCCD),
+	.P_PAD(VCCD_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(VSSA),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -996,7 +1030,7 @@
 
 module sky130_ef_io__vssd_lvc_clamped_pad (AMUXBUS_A, AMUXBUS_B,
 	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VSSIO, VSSD, VSSD_PAD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -1009,6 +1043,7 @@
   inout VCCHIB;
   inout VSSA;
   inout VSSD;
+  inout VSSD_PAD;
   inout VSSIO_Q;
   inout VSSIO;
 
@@ -1024,7 +1059,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.G_PAD(VSSD),
+	.G_CORE(VSSD),
+	.G_PAD(VSSD_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(VSSA),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -1041,7 +1077,7 @@
 // and back-to-back diodes connecting VSSD to VSSIO
 
 module sky130_ef_io__vccd_lvc_clamped2_pad (AMUXBUS_A, AMUXBUS_B,
-	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VCCD_PAD,
 	VSSIO, VSSD, VSSIO_Q
 );
   inout AMUXBUS_A;
@@ -1051,6 +1087,7 @@
   inout VDDIO_Q;	
   inout VDDA;
   inout VCCD;
+  inout VCCD_PAD;
   inout VSWITCH;
   inout VCCHIB;
   inout VSSA;
@@ -1070,7 +1107,8 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
-	.P_PAD(VCCD),
+	.P_CORE(VCCD),
+	.P_PAD(VCCD_PAD),
 	.OGC_LVC(),
 	.BDY2_B2B(VSSIO),
 	.AMUXBUS_A(AMUXBUS_A),
@@ -1088,7 +1126,7 @@
 
 module sky130_ef_io__vssd_lvc_clamped2_pad (AMUXBUS_A, AMUXBUS_B,
 	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
-	VSSIO, VSSD, VSSIO_Q
+	VSSIO, VSSD, VSSD_PAD, VSSIO_Q
 );
   inout AMUXBUS_A;
   inout AMUXBUS_B;
@@ -1101,6 +1139,7 @@
   inout VCCHIB;
   inout VSSA;
   inout VSSD;
+  inout VSSD_PAD;
   inout VSSIO_Q;
   inout VSSIO;
 
@@ -1116,6 +1155,7 @@
 	.VSSIO(VSSIO),
 	.VSSD(VSSD),
 	.VSSIO_Q(VSSIO_Q),
+	.G_CORE(VSSD_PAD),
 	.G_PAD(VSSD),
 	.OGC_LVC(),
 	.BDY2_B2B(VSSIO),
@@ -1129,3 +1169,50 @@
 
 endmodule
 
+// 
+
+module sky130_ef_io__top_power_hvc (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
+	P_CORE, P_PAD, SRC_BDY_HVC, VSSA, VDDA, VSWITCH, VDDIO_Q,
+	VCCHIB, VDDIO, VCCD, VSSIO, VSSD, VSSIO_Q
+);
+  inout AMUXBUS_A;
+  inout AMUXBUS_B;
+
+  inout DRN_HVC;
+  inout P_CORE;
+  inout P_PAD;
+  inout SRC_BDY_HVC;
+  inout VDDIO;	
+  inout VDDIO_Q;
+  inout VDDA;
+  inout VCCD;
+  inout VSWITCH;
+  inout VCCHIB;
+  inout VSSA;
+  inout VSSD;
+  inout VSSIO_Q;
+  inout VSSIO;
+
+  // Instantiate the underlying power pad (connects P_PAD to VCCD)
+  sky130_fd_io__top_power_hvc_wpadv2 sky130_fd_io__top_power_hvc_base ( 
+	.VSSA(VSSA),
+	.VDDA(VDDA),
+	.VSWITCH(VSWITCH),
+	.VDDIO_Q(VDDIO_Q),
+	.VCCHIB(VCCHIB),
+	.VDDIO(VDDIO),
+	.VCCD(VCCD),
+	.VSSIO(VSSIO),
+	.VSSD(VSSD),
+	.VSSIO_Q(VSSIO_Q),
+	.P_CORE(P_CORE),
+	.P_PAD(P_PAD),
+	.OGC_HVC(),
+	.AMUXBUS_A(AMUXBUS_A),
+	.AMUXBUS_B(AMUXBUS_B),
+	.DRN_HVC(DRN_HVC),
+	.SRC_BDY_HVC(SRC_BDY_HVC)
+  );
+
+endmodule
+