)]}'
{
  "commit": "3f3e1b6b29b4c6a5fbafec6cbe360498a1ef3931",
  "tree": "122b122f7c7ba12fd0656620ecc9d1c4cbd6b209",
  "parents": [
    "0a5e52bd3f7e8e7ae2506b2761b383d3d37e941a"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Wed Jun 16 16:55:48 2021 +0200"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Jun 21 11:44:13 2021 -0400"
  },
  "message": "fixed VSSD_PAD connection\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "426e9d06010ca0b9cf47e360b408a74f46019212",
      "old_mode": 33188,
      "old_path": "sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v",
      "new_id": "7462169e08fc7bd05bce9d4e651f02af7baeba0e",
      "new_mode": 33188,
      "new_path": "sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v"
    }
  ]
}