[openlane] Parameterize the PDN configs even more
diff --git a/sky130/openlane/common_pdn.tcl b/sky130/openlane/common_pdn.tcl index 21ba7ba..bbbf7f5 100644 --- a/sky130/openlane/common_pdn.tcl +++ b/sky130/openlane/common_pdn.tcl
@@ -1,9 +1,18 @@ # Power nets -set ::power_nets $::env(VDD_PIN) -set ::ground_nets $::env(GND_PIN) + +if { ! [info exists ::env(VDD_NET)] } { + set ::env(VDD_NET) $::env(VDD_PIN) +} + +if { ! [info exists ::env(GND_NET)] } { + set ::env(GND_NET) $::env(GND_PIN) +} + +set ::power_nets $::env(VDD_NET) +set ::ground_nets $::env(GND_NET) if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } { - if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } { + if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } { # to parameterize -- needs a PDNGEN fix set pdngen::global_connections { VPWR { @@ -21,26 +30,20 @@ # Used if the design is the core of the chip set stdcell_core { name grid - rails { - met1 {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)} - } straps { - met4 {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} - met5 {width $::env(FP_PDN_HWIDTH) pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_HWIDTH) pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} } - connect {{met1 met4} {met4 met5}} + connect {{$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}} } # Used if the design is a macro in the core set stdcell_macro { name grid - rails { - met1 {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)} - } straps { - met4 {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} } - connect {{met1 met4}} + connect {} } # Assesses whether the deisgn is the core of the chip or not based on the value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section @@ -58,23 +61,38 @@ if { [info exists ::env(FP_PDN_CORE_RING)] } { if { $::env(FP_PDN_CORE_RING) == 1 } { dict append stdcell core_ring { - met4 {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)} - met5 {width $::env(FP_PDN_CORE_RING_HWIDTH) spacing $::env(FP_PDN_CORE_RING_HSPACING) core_offset $::env(FP_PDN_CORE_RING_HOFFSET)} + $::env(FP_PDN_LOWER_LAYER) {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)} + $::env(FP_PDN_UPPER_LAYER) {width $::env(FP_PDN_CORE_RING_HWIDTH) spacing $::env(FP_PDN_CORE_RING_HSPACING) core_offset $::env(FP_PDN_CORE_RING_HOFFSET)} } } } +# Adds the core ring if enabled. +if { [info exists ::env(FP_PDN_ENABLE_RAILS)] } { + if { $::env(FP_PDN_ENABLE_RAILS) == 1 } { + dict append stdcell rails { + $::env(FP_PDN_RAILS_LAYER) {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)} + } + dict update stdcell connect current_connect { + append current_connect { {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}} + } + } else { + dict append stdcell rails {} + } +} + pdngen::specify_grid stdcell $stdcell # A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs +# TODO: generate automatically per instance: pdngen::specify_grid macro { orient {R0 R180 MX MY R90 R270 MXR90 MYR90} - power_pins "VDD VPWR vdd" - ground_pins "VSS VGND gnd" + power_pins $::env(VDD_NET) + ground_pins $::env(GND_NET) blockages "li1 met1 met2 met3 met4" straps { } - connect {{met4_PIN_ver met5}} + connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}} } set ::halo [expr min($::env(FP_HORIZONTAL_HALO), $::env(FP_VERTICAL_HALO))]
diff --git a/sky130/openlane/config.tcl b/sky130/openlane/config.tcl index 9aebeb3..01ebf69 100755 --- a/sky130/openlane/config.tcl +++ b/sky130/openlane/config.tcl
@@ -73,17 +73,22 @@ set ::env(GLB_RT_L1_ADJUSTMENT) 0.99 # Extra PDN configs +set ::env(FP_PDN_RAILS_LAYER) met1 +set ::env(FP_PDN_LOWER_LAYER) met4 +set ::env(FP_PDN_UPPER_LAYER) met5 set ::env(FP_PDN_RAIL_OFFSET) 0 set ::env(FP_PDN_VWIDTH) 1.6 set ::env(FP_PDN_HWIDTH) 1.6 +set ::env(FP_PDN_VSPACING) 1.7 +set ::env(FP_PDN_HSPACING) 1.7 # Core Ring PDN defaults -set ::env(FP_PDN_CORE_RING_VWIDTH) 20 -set ::env(FP_PDN_CORE_RING_HWIDTH) 20 -set ::env(FP_PDN_CORE_RING_VSPACING) 5 -set ::env(FP_PDN_CORE_RING_HSPACING) 5 -set ::env(FP_PDN_CORE_RING_VOFFSET) 20 -set ::env(FP_PDN_CORE_RING_HOFFSET) 20 +set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6 +set ::env(FP_PDN_CORE_RING_HWIDTH) 1.6 +set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 +set ::env(FP_PDN_CORE_RING_HSPACING) 1.7 +set ::env(FP_PDN_CORE_RING_VOFFSET) 6 +set ::env(FP_PDN_CORE_RING_HOFFSET) 6 # Used for estimate_parasitics set ::env(WIRE_RC_LAYER) "met1";