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foss-eda-tools/third_party/opencircuitdesign.com/open_pdks/2680a611d26f3448b9640fcba86d380bed7616b4^!/.
commit
2680a611d26f3448b9640fcba86d380bed7616b4
[log] [tgz]
author
Donn <me@donn.website>
Sun Jul 09 16:03:26 2023 +0300
committer
Donn <me@donn.website>
Sun Jul 09 16:03:26 2023 +0300
tree
b2335d76a994a4d40cc48bd40c7d56ffb7696dfe
parent
d9f6d3870385a580b19bc800942eedb0d5df9848 [diff]
Rename some variables to be step-independent + move MAX_FANOUT to PDK

diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl
index d8d0b9d..dd69d8f 100644
--- a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl

@@ -17,7 +17,7 @@
 set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "ZN"
 
 # update these
-set ::env(SYNTH_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file
+set ::env(OUTPUT_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file
 set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 I Z"
 set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Z"
 set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel ZN"
@@ -41,12 +41,13 @@
 # TritonCTS configurations
 set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16"
 set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8"
-set ::env(CTS_MAX_CAP) 0.5
+set ::env(MAX_CAP) 0.5
 
 set ::env(FP_PDN_RAIL_WIDTH) 0.6
 
 # The library maximum transition is 8.9ns; setting it to lower value
-set ::env(DEFAULT_MAX_TRAN) 3
+set ::env(MAX_SLEW) 3
+set ::env(MAX_FANOUT) 10
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}

diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl
index 8c34ef3..66a2719 100644
--- a/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl

@@ -17,7 +17,7 @@
 set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "ZN"
 
 # update these
-set ::env(SYNTH_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file
+set ::env(OUTPUT_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file
 set ::env(SYNTH_MIN_BUF_PORT) "$::env(STD_CELL_LIBRARY)__buf_1 I Z"
 set ::env(SYNTH_TIEHI_PORT) "$::env(STD_CELL_LIBRARY)__tieh Z"
 set ::env(SYNTH_TIELO_PORT) "$::env(STD_CELL_LIBRARY)__tiel ZN"
@@ -41,12 +41,13 @@
 # TritonCTS configurations
 set ::env(CTS_ROOT_BUFFER) "$::env(STD_CELL_LIBRARY)__clkbuf_16"
 set ::env(CTS_CLK_BUFFER_LIST) "$::env(STD_CELL_LIBRARY)__clkbuf_2 $::env(STD_CELL_LIBRARY)__clkbuf_4 $::env(STD_CELL_LIBRARY)__clkbuf_8"
-set ::env(CTS_MAX_CAP) 0.5
+set ::env(MAX_CAP) 0.5
 
 set ::env(FP_PDN_RAIL_WIDTH) 0.6
 
 # The library maximum transition is 8.9ns; setting it to lower value
-set ::env(DEFAULT_MAX_TRAN) 3
+set ::env(MAX_SLEW) 3
+set ::env(MAX_FANOUT) 10
 
 set ::env(GPL_CELL_PADDING) {0}
 set ::env(DPL_CELL_PADDING) {0}

diff --git a/sky130/openlane/sky130_fd_sc_hd/config.tcl b/sky130/openlane/sky130_fd_sc_hd/config.tcl
index e5dd71a..ade7687 100755
--- a/sky130/openlane/sky130_fd_sc_hd/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hd/config.tcl

@@ -34,7 +34,7 @@
 #capacitance : 0.017653;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 # update these
-set ::env(SYNTH_CAP_LOAD) "33.442" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/main/cells/inv/sky130_fd_sc_hd__inv_16__tt_025C_1v80.lib.json)
+set ::env(OUTPUT_CAP_LOAD) "33.442" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/main/cells/inv/sky130_fd_sc_hd__inv_16__tt_025C_1v80.lib.json)
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
 set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
@@ -68,7 +68,8 @@
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2"
 set ::env(FP_PDN_RAIL_WIDTH) 0.48
 # Determined from https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/ac7fb61f06e6470b94e8afdf7c25268f62fbd7b1/cells/clkbuf/sky130_fd_sc_hd__clkbuf_16__tt_025C_1v80.lib.json
-set ::env(CTS_MAX_CAP) 1.53169
-set ::env(DEFAULT_MAX_TRAN) 0.75
+set ::env(MAX_CAP) 1.53169
+set ::env(MAX_SLEW) 0.75
+set ::env(MAX_FANOUT) 10
 
 set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__ebuf"

diff --git a/sky130/openlane/sky130_fd_sc_hdll/config.tcl b/sky130/openlane/sky130_fd_sc_hdll/config.tcl
index 9a34844..d7d87c9 100755
--- a/sky130/openlane/sky130_fd_sc_hdll/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hdll/config.tcl

@@ -31,7 +31,7 @@
 #capacitance : 0.017653;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 # update these
-set ::env(SYNTH_CAP_LOAD) "33.468" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/inv/sky130_fd_sc_hdll__inv_16__tt_025C_1v80.lib.json)
+set ::env(OUTPUT_CAP_LOAD) "33.468" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/main/cells/inv/sky130_fd_sc_hdll__inv_16__tt_025C_1v80.lib.json)
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hdll__buf_2 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hdll__conb_1 HI"
 set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hdll__conb_1 LO"
@@ -65,7 +65,8 @@
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hdll__clkbuf_8 sky130_fd_sc_hdll__clkbuf_4 sky130_fd_sc_hdll__clkbuf_2"
 set ::env(FP_PDN_RAIL_WIDTH) 0.48
 # Determined from https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll/blob/0694bd23893de20f5233ef024acf6cca1e750ac6/cells/clkbuf/sky130_fd_sc_hdll__clkbuf_16__tt_025C_1v80.lib.json
-set ::env(CTS_MAX_CAP) 1.03547
-set ::env(DEFAULT_MAX_TRAN) 0.75
+set ::env(MAX_CAP) 1.03547
+set ::env(MAX_SLEW) 0.75
+set ::env(MAX_FANOUT) 10
 
 set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__ebuf"

diff --git a/sky130/openlane/sky130_fd_sc_hs/config.tcl b/sky130/openlane/sky130_fd_sc_hs/config.tcl
index eed9de4..bee06e6 100755
--- a/sky130/openlane/sky130_fd_sc_hs/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hs/config.tcl

@@ -34,7 +34,7 @@
 #capacitance : 0.02104;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 # update these
-set ::env(SYNTH_CAP_LOAD) "43.39" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs/blob/main/cells/inv/sky130_fd_sc_hs__inv_16__tt_025C_1v68.lib.json)
+set ::env(OUTPUT_CAP_LOAD) "43.39" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs/blob/main/cells/inv/sky130_fd_sc_hs__inv_16__tt_025C_1v68.lib.json)
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hs__buf_2 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hs__conb_1 HI"
 set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hs__conb_1 LO"
@@ -63,8 +63,9 @@
 set ::env(CLK_BUFFER_INPUT) A
 set ::env(CLK_BUFFER_OUTPUT) X
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hs__clkbuf_8 sky130_fd_sc_hs__clkbuf_4 sky130_fd_sc_hs__clkbuf_2"
-set ::env(CTS_MAX_CAP) 1.8894300000
-set ::env(DEFAULT_MAX_TRAN) 0.75
+set ::env(MAX_CAP) 1.8894300000
+set ::env(MAX_SLEW) 0.75
+set ::env(MAX_FANOUT) 10
 set ::env(FP_PDN_RAIL_WIDTH) 0.48
 
 set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__ebuf"

diff --git a/sky130/openlane/sky130_fd_sc_hvl/config.tcl b/sky130/openlane/sky130_fd_sc_hvl/config.tcl
index b99d2cd..3f3b27c 100644
--- a/sky130/openlane/sky130_fd_sc_hvl/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hvl/config.tcl

@@ -38,7 +38,7 @@
 #capacitance : 0.017653;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 # update these
-set ::env(SYNTH_CAP_LOAD) "70.77" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl/blob/main/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json)
+set ::env(OUTPUT_CAP_LOAD) "70.77" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl/blob/main/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json)
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hvl__buf_1 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hvl__conb_1 HI"
 set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hvl__conb_1 LO"
@@ -69,6 +69,7 @@
 set ::env(CLK_BUFFER_INPUT) A
 set ::env(CLK_BUFFER_OUTPUT) X
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_4 sky130_fd_sc_hvl__buf_2"
-set ::env(CTS_MAX_CAP) 5.57100
-set ::env(DEFAULT_MAX_TRAN) 0.75
+set ::env(MAX_CAP) 5.57100
+set ::env(MAX_SLEW) 0.75
+set ::env(MAX_FANOUT) 10
 set ::env(FP_PDN_RAIL_WIDTH) 0.51

diff --git a/sky130/openlane/sky130_fd_sc_ls/config.tcl b/sky130/openlane/sky130_fd_sc_ls/config.tcl
index 4f70f8f..1cfff0e 100755
--- a/sky130/openlane/sky130_fd_sc_ls/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_ls/config.tcl

@@ -34,7 +34,7 @@
 #capacitance : 0.017653;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 # update these
-set ::env(SYNTH_CAP_LOAD) "46.690" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls/blob/main/cells/inv/sky130_fd_sc_ls__inv_16__tt_100C_1v80.lib.json)
+set ::env(OUTPUT_CAP_LOAD) "46.690" ; # femtofarad _inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls/blob/main/cells/inv/sky130_fd_sc_ls__inv_16__tt_100C_1v80.lib.json)
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_ls__buf_2 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_ls__conb_1 HI"
 set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_ls__conb_1 LO"
@@ -66,8 +66,9 @@
 set ::env(CLK_BUFFER_INPUT) A
 set ::env(CLK_BUFFER_OUTPUT) X
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_ls__clkbuf_8 sky130_fd_sc_ls__clkbuf_4 sky130_fd_sc_ls__clkbuf_2"
-set ::env(CTS_MAX_CAP) 1.53169
-set ::env(DEFAULT_MAX_TRAN) 0.75
+set ::env(MAX_CAP) 1.53169
+set ::env(MAX_SLEW) 0.75
+set ::env(MAX_FANOUT) 10
 set ::env(FP_PDN_RAIL_WIDTH) 0.48
 
 set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__ebuf"

diff --git a/sky130/openlane/sky130_fd_sc_ms/config.tcl b/sky130/openlane/sky130_fd_sc_ms/config.tcl
index 9275f4d..36f0cea 100755
--- a/sky130/openlane/sky130_fd_sc_ms/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_ms/config.tcl

@@ -34,7 +34,7 @@
 #capacitance : 0.017653;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 # update these
-set ::env(SYNTH_CAP_LOAD) "22.66" ; # femtofarad _inv_8 pin A cap
+set ::env(OUTPUT_CAP_LOAD) "22.66" ; # femtofarad _inv_8 pin A cap
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_ms__buf_2 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_ms__conb_1 HI"
 set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_ms__conb_1 LO"
@@ -65,8 +65,9 @@
 set ::env(CLK_BUFFER_INPUT) A
 set ::env(CLK_BUFFER_OUTPUT) X
 set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_ms__clkbuf_8 sky130_fd_sc_ms__clkbuf_4 sky130_fd_sc_ms__clkbuf_2"
-set ::env(CTS_MAX_CAP) 1.53169
-set ::env(DEFAULT_MAX_TRAN) 0.75
+set ::env(MAX_CAP) 1.53169
+set ::env(MAX_SLEW) 0.75
+set ::env(MAX_FANOUT) 10
 set ::env(FP_PDN_RAIL_WIDTH) 0.48
 
 set ::env(TRISTATE_CELL_PREFIX) "$::env(STD_CELL_LIBRARY)__ebuf"

diff --git a/sky130/openlane/sky130_osu_sc_t18/config.tcl b/sky130/openlane/sky130_osu_sc_t18/config.tcl
index 5b729ce..b9d6273 100755
--- a/sky130/openlane/sky130_osu_sc_t18/config.tcl
+++ b/sky130/openlane/sky130_osu_sc_t18/config.tcl

@@ -29,7 +29,7 @@
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
 # capacitance : 0.037357;
 # update these
-set ::env(SYNTH_CAP_LOAD) "37.357" ; # femtofarad INVX8 pin A cap
+set ::env(OUTPUT_CAP_LOAD) "37.357" ; # femtofarad INVX8 pin A cap
 set ::env(SYNTH_MIN_BUF_PORT) "BUFX1 A Y"
 set ::env(SYNTH_TIEHI_PORT) "TIEHI Y"
 set ::env(SYNTH_TIELO_PORT) "TIELO Y"
@@ -69,6 +69,6 @@
 # TODO...
 set ::env(CTS_SQR_CAP) 0.258e-3
 set ::env(CTS_SQR_RES) 0.125
-set ::env(CTS_MAX_CAP) 1.53169
+set ::env(MAX_CAP) 1.53169
 
 set ::env(FP_PDN_RAIL_WIDTH) 0.48