tree 3a51cd9a321b69a9ed75f2999ed4c7c73942bf8f
parent 56605365440121d991c2bb93fd8342764e63bddc
author Tim Edwards <tim@opencircuitdesign.com> 1634154540 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1634154540 -0400

Added a patch for the "wire 1" syntax error in the sky130_fd_sc_hd
library verilog.  This error shows up when a specific flop type is
used in a gate-level verilog simulation.