)]}'
{
  "commit": "24f2950002b49d905c83bd851195d14629f3e5cf",
  "tree": "3a51cd9a321b69a9ed75f2999ed4c7c73942bf8f",
  "parents": [
    "56605365440121d991c2bb93fd8342764e63bddc"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Oct 13 15:49:00 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Wed Oct 13 15:49:00 2021 -0400"
  },
  "message": "Added a patch for the \"wire 1\" syntax error in the sky130_fd_sc_hd\nlibrary verilog.  This error shows up when a specific flop type is\nused in a gate-level verilog simulation.\n",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
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      "new_mode": 33188,
      "new_path": "VERSION"
    },
    {
      "type": "modify",
      "old_id": "f2a2c46df41394642be2a9ffced317f0b57bf672",
      "old_mode": 33188,
      "old_path": "sky130/Makefile.in",
      "new_id": "ead6552ee66690e0cb60d2afaafb9efcb1d26971",
      "new_mode": 33188,
      "new_path": "sky130/Makefile.in"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "024fbccc0aa155f7ed1fe6142c75c7f4b97dd729",
      "new_mode": 33188,
      "new_path": "sky130/custom/patches/hd_wire_syntax.patch"
    }
  ]
}