)]}'
{
  "commit": "234707136a5b5a9544302ed5714c6c7f946a056c",
  "tree": "aefdb8b00e7a6ad3828aa0d77faaa8e7763c90ac",
  "parents": [
    "68f22710b8e7275d9e4189607c3bafdd66fc5798"
  ],
  "author": {
    "name": "Iztok Jeras",
    "email": "iztok.jeras@gmail.com",
    "time": "Wed May 20 13:21:35 2026 +0200"
  },
  "committer": {
    "name": "R. Timothy Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu May 28 13:49:47 2026 -0400"
  },
  "message": "sky130: updated synth_excluded.cells and pnr_excluded.cells\n\nUpdates done to synth_excluded.cells lists accross all SCLs:\n\n- remove cells that don\u0027t exist in the SCL\n  (lists for SCLs asside from HD seem to have been copy/pasted)\n- remove all combinational/sequential `*_1` cells\n- remove all delay flops/latches (except for the ones for scan chain)\n- remove all multiplexers (`mux2i`/`mux4`/`mux8`/`mux16`), majority (`maj3`) cells\n\n- add all `*fill*`/`*decap*`/`*tap*`/`*diode*` cells (should be handled by PNR)\n- add all `*macro_sparecell*` cells (should be used for ECO)\n- add all `probe*` cells (???)\n- add all power domain crossing (isolation) related cells `*lpflow*`/`*bleeder*`/`*kapwr*`/`*iso*`\n  (should be used by future flow)\n- add all scan chain related cells `s*` (should be used by DFT)\n- add all clock tree cells `clkbuf*`/`clkinv*`/`clkmux*` (should be used by CTS)\n  except for clock gating cells (handled by Yosys synthesis)\n- add all signal/clock delay cells `*dly*` (should be used by PNR timing repair,\n  can also be used for all digital FLL, CDR, adaptive IO timing, ...)\n\nUpdates done to pnr_excluded.cells lists accross all SCLs:\n\n- remove cells that don\u0027t exist in the SCL\n  (lists for SCLs asside from HD seem to have been copy/pasted)\n- remove all combinational `*_0` cells\n- remove all `clkdlybuf*` delay cells\n- remove cells with unknown exclusion reasons `buf_16`, `fa_4`, `mux4_4`\n- remove all unusual cells `xnor3*`, `xor3`\n\n- keep or add cells related to power domain crossing\n",
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