)]}'
{
  "commit": "217bc1d18cdaa268cba96c75737b70b15eb507c7",
  "tree": "2977befc08d0a36abce20e07ded849939f036f18",
  "parents": [
    "64349cc1f20fdece32bd741e847915b9efe7dcb3"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Dec 02 13:19:46 2022 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Dec 02 13:19:46 2022 -0500"
  },
  "message": "Corrects an error in the verilog where an `endif is followed by\ntext not within a comment in the sky130_fd_sc_hd verilog library.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "03dfe2976c5113070eee3eb6932370907862553c",
      "old_mode": 33188,
      "old_path": "VERSION",
      "new_id": "fa8ad76689a11591bd2d7bb058eacfed0bf36f34",
      "new_mode": 33188,
      "new_path": "VERSION"
    },
    {
      "type": "modify",
      "old_id": "727de74f8439952221da8be8954a1b5b1d68439c",
      "old_mode": 33188,
      "old_path": "sky130/Makefile.in",
      "new_id": "a0cfd35803a0e0395d0a638ad907996fd866405d",
      "new_mode": 33188,
      "new_path": "sky130/Makefile.in"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "90162f042dee29a8ad6cd582430af916d30347bc",
      "new_mode": 33261,
      "new_path": "sky130/custom/scripts/fix_verilog.py"
    }
  ]
}