)]}'
{
  "commit": "11af1927d0866ecd23e7cd611c51aa8fc31e780d",
  "tree": "7cd41309deca93360b2ea24d7b5785e37ddf32ad",
  "parents": [
    "0059588eebfc704681dc2368bd1d33d96281d10f"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Oct 27 14:58:52 2022 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Oct 27 14:58:52 2022 -0400"
  },
  "message": "A number of changes in support of correctly reading and extracting the\nSkyWater I/O cells.  This set of patches has been a long time in coming!\n(1) Corrected the vendor cells for the VDDIO and VSSIO pads such that\nthe metal3 area under VDDIO_Q and VSSIO_Q, respectively, is separated\nby metal resistors.  This allows the overlay cell to contact the\ndomains while keeping the net names separate.  Changed the SPICE and\nCDL netlists to add the metal resistor devices.  (2) Corrected an\nissue in the magic tech file that caused some high voltage transistors\nin the I/O to get split.  (3) Corrected the netlist for the hvsbt_nor\ncell, which had an incorrect count of pFET transistors (each device\nhas M\u003d2, not M\u003d1).  (4) Modified the netgen entries for metal resistors\nto allow a very large tolerance for L and W, based on the assumption\nthat these are net-splitters, not devices.  This avoids the need to\ntrack down each one and ensure its W and L is correct.  (5) Created an\nimport Tcl script for the vendor GPIO library that flattens specific\ncells to ensure that devices are correctly generated.  (6) Corrected\nthe units for diodes created by magic\u0027s extractor to match the\n(bizarre) model units.  (7) Corrected a couple of port ordering issues\nin the netlists for the Efabless combined overlay I/O cells.  The\nbottom line is that it is now possible to read in the I/O cell library\nand extract an LVS clean netlist from a layout using the SkyWater I/O\npads.\n",
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