Added adder mapping files for yosys
- to enable $add/$sub operator mapping to different types of adders
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index 334d040..32feebe 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -449,6 +449,8 @@
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/latch_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/latch_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/mux2_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/mux2_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/mux4_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/mux4_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/fa_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/fa_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hd/rca_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hd/rca_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/tracks.info
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/no_synth.cells
@@ -456,6 +458,8 @@
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/latch_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/latch_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/mux2_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/mux2_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/mux4_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/mux4_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/fa_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/fa_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hs/rca_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hs/rca_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/tracks.info
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/no_synth.cells
@@ -463,6 +467,8 @@
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/latch_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/latch_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/mux2_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/mux2_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/mux4_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/mux4_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/fa_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/fa_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ms/rca_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ms/rca_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/tracks.info
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/no_synth.cells
@@ -470,12 +476,16 @@
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/latch_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/latch_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/mux2_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/mux2_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/mux4_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/mux4_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/fa_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/fa_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_ls/rca_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_ls/rca_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/tracks.info
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/no_synth.cells
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/tribuff_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/tribuff_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/latch_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/latch_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/mux2_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/mux2_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/fa_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/fa_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hdll/rca_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hdll/rca_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/config.tcl > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/tracks.info > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/tracks.info
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/no_synth.cells > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/no_synth.cells
@@ -483,6 +493,8 @@
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/latch_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/latch_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/mux2_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/mux2_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/mux4_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/mux4_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/fa_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/fa_map.v
+ ${CPP} ${SKY130A_DEFS} openlane/sky130_fd_sc_hvl/rca_map.v > ${OPENLANE_STAGING_A}/sky130_fd_sc_hvl/rca_map.v
${CPP} ${SKY130A_DEFS} openlane/sky130_osu_sc_t18/config.tcl > ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/config.tcl
${CPP} ${SKY130A_DEFS} openlane/sky130_osu_sc_t18/tracks.info > ${OPENLANE_STAGING_A}/sky130_osu_sc_t18/tracks.info
diff --git a/sky130/openlane/config.tcl b/sky130/openlane/config.tcl
index e5be7e7..78548de 100755
--- a/sky130/openlane/config.tcl
+++ b/sky130/openlane/config.tcl
@@ -78,6 +78,12 @@
# Tri-state buffer mapping
set ::env(TRISTATE_BUFFER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/tribuff_map.v"
+# Full adder mapping
+set ::env(FULL_ADDER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/fa_map.v"
+
+# Ripple carry adder mapping
+set ::env(RIPPLE_CARRY_ADDER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/rca_map.v"
+
set ::env(GLB_RT_L1_ADJUSTMENT) 0.99
# Extra PDN configs
diff --git a/sky130/openlane/sky130_fd_sc_hd/fa_map.v b/sky130/openlane/sky130_fd_sc_hd/fa_map.v
new file mode 100644
index 0000000..f040b34
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hd/fa_map.v
@@ -0,0 +1,19 @@
+`define FA_CELL sky130_fd_sc_hd__fa_1
+
+(* techmap_celltype = "$fa" *)
+module _90_fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A, B, C;
+ (* force_downto *)
+ output [WIDTH-1:0] X, Y;
+
+ (* force_downto *)
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ wire _TECHMAP_FAIL_ = WIDTH > 1;
+
+ `FA_CELL FA ( .COUT(X), .CIN(C), .A(A), .B(B), .SUM(Y) );
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hd/rca_map.v b/sky130/openlane/sky130_fd_sc_hd/rca_map.v
new file mode 100644
index 0000000..54807be
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hd/rca_map.v
@@ -0,0 +1,84 @@
+`define FA_CELL sky130_fd_sc_hd__fa_1
+
+(* techmap_celltype = "$add" *)
+module sky130_rca (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b0};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
+
+(* techmap_celltype = "$sub" *)
+module sky130_rca_sub (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ //input CI, BI;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = ~B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b1};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hdll/fa_map.v b/sky130/openlane/sky130_fd_sc_hdll/fa_map.v
new file mode 100644
index 0000000..4236d91
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hdll/fa_map.v
@@ -0,0 +1,19 @@
+`define FA_CELL sky130_fd_sc_hdll__fa_1
+
+(* techmap_celltype = "$fa" *)
+module _90_fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A, B, C;
+ (* force_downto *)
+ output [WIDTH-1:0] X, Y;
+
+ (* force_downto *)
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ wire _TECHMAP_FAIL_ = WIDTH > 1;
+
+ `FA_CELL FA ( .COUT(X), .CIN(C), .A(A), .B(B), .SUM(Y) );
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hdll/rca_map.v b/sky130/openlane/sky130_fd_sc_hdll/rca_map.v
new file mode 100644
index 0000000..cf6dfba
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hdll/rca_map.v
@@ -0,0 +1,84 @@
+`define FA_CELL sky130_fd_sc_hdll__fa_1
+
+(* techmap_celltype = "$add" *)
+module sky130_rca (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b0};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
+
+(* techmap_celltype = "$sub" *)
+module sky130_rca_sub (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ //input CI, BI;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = ~B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b1};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hs/fa_map.v b/sky130/openlane/sky130_fd_sc_hs/fa_map.v
new file mode 100644
index 0000000..0102b63
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hs/fa_map.v
@@ -0,0 +1,19 @@
+`define FA_CELL sky130_fd_sc_hs__fa_1
+
+(* techmap_celltype = "$fa" *)
+module _90_fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A, B, C;
+ (* force_downto *)
+ output [WIDTH-1:0] X, Y;
+
+ (* force_downto *)
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ wire _TECHMAP_FAIL_ = WIDTH > 1;
+
+ `FA_CELL FA ( .COUT(X), .CIN(C), .A(A), .B(B), .SUM(Y) );
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hs/rca_map.v b/sky130/openlane/sky130_fd_sc_hs/rca_map.v
new file mode 100644
index 0000000..d1e9e58
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hs/rca_map.v
@@ -0,0 +1,84 @@
+`define FA_CELL sky130_fd_sc_hs__fa_1
+
+(* techmap_celltype = "$add" *)
+module sky130_rca (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b0};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
+
+(* techmap_celltype = "$sub" *)
+module sky130_rca_sub (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ //input CI, BI;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = ~B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b1};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hvl/fa_map.v b/sky130/openlane/sky130_fd_sc_hvl/fa_map.v
new file mode 100644
index 0000000..a24a928
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hvl/fa_map.v
@@ -0,0 +1,19 @@
+`define FA_CELL sky130_fd_sc_hvl__fa_1
+
+(* techmap_celltype = "$fa" *)
+module _90_fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A, B, C;
+ (* force_downto *)
+ output [WIDTH-1:0] X, Y;
+
+ (* force_downto *)
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ wire _TECHMAP_FAIL_ = WIDTH > 1;
+
+ `FA_CELL FA ( .COUT(X), .CIN(C), .A(A), .B(B), .SUM(Y) );
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_hvl/rca_map.v b/sky130/openlane/sky130_fd_sc_hvl/rca_map.v
new file mode 100644
index 0000000..47a8e82
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_hvl/rca_map.v
@@ -0,0 +1,84 @@
+`define FA_CELL sky130_fd_sc_hvl__fa_1
+
+(* techmap_celltype = "$add" *)
+module sky130_rca (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b0};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
+
+(* techmap_celltype = "$sub" *)
+module sky130_rca_sub (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ //input CI, BI;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = ~B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b1};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_ls/fa_map.v b/sky130/openlane/sky130_fd_sc_ls/fa_map.v
new file mode 100644
index 0000000..e9f70e0
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_ls/fa_map.v
@@ -0,0 +1,19 @@
+`define FA_CELL sky130_fd_sc_ls__fa_1
+
+(* techmap_celltype = "$fa" *)
+module _90_fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A, B, C;
+ (* force_downto *)
+ output [WIDTH-1:0] X, Y;
+
+ (* force_downto *)
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ wire _TECHMAP_FAIL_ = WIDTH > 1;
+
+ `FA_CELL FA ( .COUT(X), .CIN(C), .A(A), .B(B), .SUM(Y) );
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_ls/rca_map.v b/sky130/openlane/sky130_fd_sc_ls/rca_map.v
new file mode 100644
index 0000000..878c7a1
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_ls/rca_map.v
@@ -0,0 +1,84 @@
+`define FA_CELL sky130_fd_sc_ls__fa_1
+
+(* techmap_celltype = "$add" *)
+module sky130_rca (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b0};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
+
+(* techmap_celltype = "$sub" *)
+module sky130_rca_sub (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ //input CI, BI;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = ~B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b1};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_ms/fa_map.v b/sky130/openlane/sky130_fd_sc_ms/fa_map.v
new file mode 100644
index 0000000..a847f37
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_ms/fa_map.v
@@ -0,0 +1,19 @@
+`define FA_CELL sky130_fd_sc_ms__fa_1
+
+(* techmap_celltype = "$fa" *)
+module _90_fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A, B, C;
+ (* force_downto *)
+ output [WIDTH-1:0] X, Y;
+
+ (* force_downto *)
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ wire _TECHMAP_FAIL_ = WIDTH > 1;
+
+ `FA_CELL FA ( .COUT(X), .CIN(C), .A(A), .B(B), .SUM(Y) );
+
+endmodule
diff --git a/sky130/openlane/sky130_fd_sc_ms/rca_map.v b/sky130/openlane/sky130_fd_sc_ms/rca_map.v
new file mode 100644
index 0000000..cf6dfba
--- /dev/null
+++ b/sky130/openlane/sky130_fd_sc_ms/rca_map.v
@@ -0,0 +1,84 @@
+`define FA_CELL sky130_fd_sc_hdll__fa_1
+
+(* techmap_celltype = "$add" *)
+module sky130_rca (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b0};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
+
+(* techmap_celltype = "$sub" *)
+module sky130_rca_sub (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ //input CI, BI;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = ~B_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] C = {CO, 1'b1};
+
+
+ generate
+ genvar i;
+ for(i=0; i<Y_WIDTH; i=i+1) begin: stage
+ `FA_CELL FA ( .COUT(CO[i]), .CIN(C[i]), .A(AA[i]), .B(BB[i]), .SUM(Y[i]) );
+ end endgenerate
+
+endmodule
