tree 08c11ca2b51d34d07231415b80b73a00893e4fa3
parent 48db3e1a428ae16f5d4c86e0b7679656cf8afe3d
author Tim Edwards <tim@opencircuitdesign.com> 1600967519 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1600967519 -0400

Various modifications to accommodate the somewhat complicated
management of include statements in verilog files in order to
build the compiled libraries.