)]}'
{
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  "tree": "08c11ca2b51d34d07231415b80b73a00893e4fa3",
  "parents": [
    "48db3e1a428ae16f5d4c86e0b7679656cf8afe3d"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Sep 24 13:11:59 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Sep 24 13:11:59 2020 -0400"
  },
  "message": "Various modifications to accommodate the somewhat complicated\nmanagement of include statements in verilog files in order to\nbuild the compiled libraries.\n",
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