Various modifications to accommodate the somewhat complicated
management of include statements in verilog files in order to
build the compiled libraries.
diff --git a/common/create_verilog_library.py b/common/create_verilog_library.py
index fb530ab..32ce2c5 100755
--- a/common/create_verilog_library.py
+++ b/common/create_verilog_library.py
@@ -37,11 +37,14 @@
def create_verilog_library(destlibdir, destlib, do_compile_only=False, do_stub=False, excludelist=[]):
- alllibname = destlibdir + '/' + destlib + '.v'
+ # 'destlib' should not have an extension, because one will be generated.
+ destlibroot = os.path.splitext(destlib)[0]
+
+ alllibname = destlibdir + '/' + destlibroot + '.v'
if os.path.isfile(alllibname):
os.remove(alllibname)
- print('Diagnostic: Creating consolidated verilog library ' + destlib + '.v')
+ print('Diagnostic: Creating consolidated verilog library ' + destlibroot + '.v')
vlist = glob.glob(destlibdir + '/*.v')
if alllibname in vlist:
vlist.remove(alllibname)
