)]}'
{
  "commit": "033872fcb033df5003674b6eca87109bb20ef291",
  "tree": "c10cd64f5ff7e3fc3d05524b963a6a6bc934c501",
  "parents": [
    "4e7a1f4de1b219bc7b48865dd3a511e9547af6ba"
  ],
  "author": {
    "name": "R. Timothy Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Sep 22 11:20:53 2025 -0400"
  },
  "committer": {
    "name": "R. Timothy Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Sep 22 11:20:53 2025 -0400"
  },
  "message": "Corrected the handling of the \"endcap\" cell in GF180MCU standard\ncell libraries;  the VPW and VNW pins were being added to the\nnetlist, whereas the cell is a well/substrate tie and does not\nhave those pins, and is not supposed to.  Thanks to Shep Pitts\nfor reporting the issue.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2fa6312ae0851d8096fd8681f938a18f969183b7",
      "old_mode": 33188,
      "old_path": "VERSION",
      "new_id": "77f8e860f597ea6b17199f9322aedd9a2cfdf2a6",
      "new_mode": 33188,
      "new_path": "VERSION"
    },
    {
      "type": "modify",
      "old_id": "26f3c7a17d6b5352ec11f9ec56fe996ba98751e7",
      "old_mode": 33261,
      "old_path": "gf180mcu/custom/scripts/convert_sc_cdl.py",
      "new_id": "7e9c70517c31d6f720605376f10c6f4b67c29f97",
      "new_mode": 33261,
      "new_path": "gf180mcu/custom/scripts/convert_sc_cdl.py"
    }
  ]
}