Corrected the handling of the "endcap" cell in GF180MCU standard
cell libraries;  the VPW and VNW pins were being added to the
netlist, whereas the cell is a well/substrate tie and does not
have those pins, and is not supposed to.  Thanks to Shep Pitts
for reporting the issue.

VERSION

diff --git a/VERSION b/VERSION
index 2fa6312..77f8e86 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.544
+1.0.545

gf180mcu/custom/scripts/convert_sc_cdl.py

diff --git a/gf180mcu/custom/scripts/convert_sc_cdl.py b/gf180mcu/custom/scripts/convert_sc_cdl.py
index 26f3c7a..7e9c705 100755
--- a/gf180mcu/custom/scripts/convert_sc_cdl.py
+++ b/gf180mcu/custom/scripts/convert_sc_cdl.py
@@ -42,9 +42,7 @@
         fixedline = re.sub('^d', 'D', fixedline)
 	# 4) Convert $m to M
         fixedline = re.sub(r'\$m=', 'M=', fixedline, flags=re.IGNORECASE)
-	# 5) Fix incorrect endcap (endcap does not have VNW VPW)
-        fixedline = re.sub('endcap VDD VNW VPW', 'endcap VDD', fixedline, flags=re.IGNORECASE)
-	# 6) Fix incorrect diode properties in antenna cell (missing key)
+	# 5) Fix incorrect diode properties in antenna cell (missing key)
         fixedline = re.sub('0.2052p 1.86u', 'AREA=0.2052p PJ=1.86u', fixedline, flags=re.IGNORECASE)
         fixedline = re.sub('0.2034p 1.85u', 'AREA=0.2034p PJ=1.85u', fixedline, flags=re.IGNORECASE)