)]}'
{
  "commit": "002b5dd29d81e9affec60cb6d57ed867c888e23c",
  "tree": "7c0b450a947476077bdaad34228f663c8efedad2",
  "parents": [
    "11af1927d0866ecd23e7cd611c51aa8fc31e780d"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 29 17:55:04 2022 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 29 17:55:04 2022 -0400"
  },
  "message": "One more pass---since magic had difficulty correctly extracting the \"C\"\nshaped resistors cutting VDDIO from VDDIO_Q and VSSIO from VSSIO_Q, I\nadded one more resistor to make them a ring, and now the resistors\nextract with the correct (effective) L and W.  Created a LEF view for\ntop_power_hvc_wpadv2 which previously did not exist in the PDK, and\ncreated a script to modify the LEF views of the cells for which the\nresistor ring was added, so that the port annotation does not overwrite\nthe resistors.  I now have LVS scripts running on 12 pad types and they\nall come out clean, including properties and pins.\n",
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